T Efficient Test Solution for Integrated Power Devices

Transcription

1 T Efficient Test Solution for Integrated Power Devices

2 Integrated Power Device Test Challenge Device markets - Automotive - Industrial/Medical - Consumer (e.g. Power Management) Device characteristics Voltages > 40 V Pulse currents on multiple pins >10 A Digital data rates > 100 Mbps Embedded AD/DA Linearity > 12 Bit Timing requirements < 10ns Analog Precision na, uv Mixed Signal Mixed Signal Power Stages ADC DAC Complex test requirements Multiple functions per device pins (analog, digital, power) Complex I/O pin structure Limited accessibility to function blocks

3 Integrated Power Solution (IPS) Conventional System Architecture Conventional Systems LB PB - Modules have dedicated functions - Limited parallel measurements - Complex load board circuitry & muxing - Limited time to market due to complexity PMU Digital TMU DGT AWG New T2000 IPS Multifunctional Architecture Multiple functions per channel Matrix functionality built-in high current modules Less LB circuitry design, correlation, checkers 2-4x parallelism of competitor Multifunctional DUT DUT MMXH PMU AWG PMU Digital Relay AWG DGT Relay TMU Pattern Control LB

4 Effective Test Solution for Integrated Power Devices Mixed Signal Power Stages Power Matrix 72 power ports Mixed Signal ADC DAC LOAD High Voltage Mixed Signal Low Voltage Mixed Signal General Purpose Generator + Digitizer Floating Power 32 Analog (85V) & 32 Digital (24V) 64 Analog (18V) 64 Digital (8V) 8/16 Generators 8 Digitizers 6 Sources 80V/12A Stackable & Gangable

5 High Throughput Design Multiple functions available per pin enable Different tests in parallel = fast test time DC Parametric tests Functional tests Timing tests Waveform characteristics A V A V High Multi DUT Efficiency Add tests during product life cycle without load board redesign A V A V

6 Flexible Time Measurements Multiple precise timing measurements in parallel On same signal Across signals Across signal types tdelay = T1 T1 tfall = T2 T1 trise = T4 T3 tmatch = T1 T1 ton = T2 T1 tperiod = T3 T1 All timing measurements in one shot! >> Reduced Test Time

7 Outstanding Analog Performance Reduced test time by Fast analog source settling Seamless range switching avoids power down of device Protection of DUT and ATE Spike free operation guaranteed by HW design Fast settling, no overshoot No Spikes while changing ranges

8 Flexible Power Subsystem Floating source design for maximum flexibility upon test requirement Stacking for high voltage test +160V Short power pulses for fast test time 100us 300W -160V Ganging for high current tests +60V +5A

9 Efficient DUT Power Routing Fast Switching Sequence 2ms (1ms toff + 1ms ton) Test FET1 Test FET2 Test FET3 Matrix Column Matrix Column Matrix Column Cost optimized usage of high power channels Fewer power sources required Higher parallel DUT count by saving load board relays Faster test time/reliable switching using solid state design Flexible power routing to multiple DUT pins Test FET4 Matrix Column

10 Overcoming Load Board Restriction Other ATE T2000 Loadboard More DUTs in Parallel Reduced CoT Other ATE: T2000: R=Relays, B=Board Components Available area limits parallel test expansion Separate instruments require load board multiplexing Large load board increases available application area Unique system architecture minimizes need for load board multiplexing

11 Fast Test Development Separation of Test Method development from Test Application DUT specific Generic High code reusability = faster test development!

12 Modular Test Development Modular test plan enables Concurrent test development Easy rearrangement of tests Easy program link Digital Test Development Digital Interface DSP Core Processor Core Multimedia Processor Memory Test Development SRAM Flash DRAM Power Audio AD/DA Mixed Signal Test Development Link Production More efficient development + better manpower utilization!

13 T2000 Meets Demands for Integrated Power Testing Cost-of-Test High parallel DUT count by multifunctional architecture Fast test times by high throughput system design Cost optimized/flexible usage of power subsystem Time-to-Production Fast test development by Separation of Test Methods & Test Conditions Concurrent development by modular test plan

14 Thank you for your kind attention!