MODELING SHARED- MEMORY MULTIPROCESSOR SYSTEMS WITH AADL

Transcription

1 MODELING SHARED- MEMORY MULTIPROCESSOR SYSTEMS WITH AADL Stéphane Rubini, Frank Singhoff Lab-STICC, University of Western Brittany (UBO), Brest, France Contact: Pierre Dissaux Ellidiss Technologies, Brest, France Smart and Cheddar Projects Workshop, Valencia, Spain, September 29 th, 2014

2 Monday, September 29, Scheduling Analysis on Multiprocessor Systems The multiprocessor execution platform model CPU1 CPU2 CPU3 in the real-time scheduling theory and a real one on a single chip (TI OMAP 4430).

3 3 Hidden Sharing of some Resources The scheduling goal is to manage the temporal sharing of resources (typically processing unit allocations). But, hardware systems is build to hide some of them. Example of the SPEC program slowdowns when running in parallel with another program on a parallel core sharing of the L2 cache. From Christos Kozyrakis lectures, citation of DasCMP 06

4 4 Abstraction level of the execution platform What is the right level of abstraction? The usage of a complete hardware description is not tractable (cycle accurate simulation), or not available. ADL components more abstract descriptions The execution platform models must be able to express: the hardware capabilities (processing units, IO devices, ); the resource sharing.

5 5 Outline Modeling of Programmable Heterogonous Multiprocesors (PHM) to perform scheduling analysis. Processing units Identification for the allocation of tasks Shared resources Identification for the performance analysis Example IC-INT-VPX3a board modeling Conclusion

6 Resource identification Multi-processing implementations and task scheduling Processors, cores or physical threads may be seen as standard processing resources by the scheduler. 6 Task Task Task Multi-Processor Multi-Core Processor Core Core Multi-Threaded Core But the shared resources are the difference Private Caches Interconnect Network Optional Shared Caches Memory Private caches Interconnect Network Shared Caches Shared / Private Resources Shared Private Caches caches Physical Thread

7 7 Resource identification Processing units Processing unit Processing system (10 processing units)

8 Resource identification Task allocations 8 Global scheduling Partitioned scheduling app is a process, thrs an array of threads, and dedicatedthr a thread Scheduling domain

9 9 Outline Modeling of Programmable Heterogonous Systems (PHM) to perform scheduling analysis. Processing units Identification for the allocation of tasks Shared resources Identification for the performance analysis Example IC-INT-VPX3a board modeling Conclusion

10 Shared resources Hierarchical models 10 The node s children can represent the entities that interact directly with this node (shared resource). Processing units Shared resources Pj Pk Pi My SSr Mx

11 11 Shared resources Node internals and private resources Composite M y implementation Pj Pk Pi My Private processor resource Mx

12 12 Outline Modeling of Programmable Heterogonous Systems (PHM) to perform scheduling analysis. Processing units Identification for the allocation of tasks Shared resources Identification for the performance analysis Example IC-INT-VPX3a board modeling Conclusion

13 Example Board InterfaceConcept IC-INT-VPX3a Board InterfaceConcept IC-INT-VPX3a Processor Intel Core i7 2566LE: Dual cores, 2.2 GHz, 3 levels of caches Technology «Hyper Threading» two physical threads /core 13 Thread state 1 Thread state 1 Thread state 2 Thread state 2 L1 Inst Cache L1 Data Cache L1 Inst Cache L1 Data Cache L2 Cache L2 Cache L3 Cache

14 Example IC-INT-VPX3a execution platform modeling core2 14 pth1 pth2 core1 mem mem

15 15 Example New processing unit arrivals! In mode Hyper-threading pth1 pth2 pth1 pth2 mem mem mem

16 16 Outline Modeling of Programmable Heterogonous Systems (PHM) to perform scheduling analysis. Processing units Identification for the allocation of tasks Shared resources Identification for the performance analysis Example IC-INT-VPX3a board modeling Conclusion

17 17 Conclusion Modeling for scheduling analysis: Processing unit enumeration and partitioning: processor bindings The presented AADL is interpreted by AADLinspector to define the allocation of tasks on processing units. Memory hierarchy effect The cheddar tool deals with cache related preemption delay for single shared instruction cache and uniprocessor platform. Extension to multiprocessor remains to be done. Cache analysis, WCET Modeling for code generation What are the specific requirements?

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19 Shared resources Hyper-threading configuration 19 Processing units activation following the user s configuration.

20 20 Other topics Memory hierarchies are complexes, but hardware entities interconnections too. Examples: SoCs contains a lot of buses with different performances Serial communications allow to multiple the numbers of connections, and their configuration IC VPX board (on 12 lanes PCIE) Need of properties to characterize processing units Capabilities (speed, operations) in Programmable Heterogeneous Multiprocessors (PHM) Implementation: operating systems don t manage similarly physical threads or cores/processors.

21 Allocation strategies System and software architecture Complete system 21 Software architecture Implicit assumption: A process represents an address space the execution platform implements the shared memory paradigm (native or rebuild through Distributed Shared Memory mechanisms)