Context. Giorgio Buttazzo. Scuola Superiore Sant Anna. Embedded systems are becoming more complex every day: more functions. higher performance

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1 Giorgio uttazzo Scuola Superiore Sant nna Context Embedded systems are becoming more complex every day: more functions higher performance higher efficiency new hardware platforms 2 1

2 Increasing complexity # functions in a cell phone year Hardware Performance 1 Instructions per second MD Phenom Intel i7 (6 cores) (6 cores) Xbox 36 (3 cores) MD thlon DEC lpha Intel Pentium Pro Intel 6 Intel 36 M 6 Intel 26 Intel year 2

3 1 Lines of code Software Complexity Windows Vista Windows Windows XP Windows 7 Windows 2 Linux 3.6 Windows NT. Linux Windows 9 Linux 2.6. Windows 3.1 Linux 2..2 Linux 2. Linux 1.1. Unix MS-DOS 3.1 MS-DOS year nd the Result is oot time (seconds) year 3

4 It increases with upgrades oot time (minutes) Windows 7 Windows 2K K 6K K 1M files upgraded ECU growth in a car #ECUs ECU = Electronic Control Unit 1 6 every function is encoded in a different ECU year

5 dvantages of separation Separating functions in dedicated ECUs allows: easier development easier testing easier certification easier maintenance Problems of separation With the increasing number of ECUs, there are problems of space, weight, energy.

6 How to add more functions? 1 Functions ECUs no more space Functions current situation: 7 ECUs ECUs group more functions in the same ECU year That's nice, but ECU 1 New platform ECU 2 How can we test and certify a function in the presence of other applications? How can we guarantee behavior and performance to get certification? 6

7 dditional problems single core platform multicore platform single core platform How do we partition the applications on the available cores? How does the Worst-Case Execution Time (WCET) scale on multicore architecture? The problem When multiple applications run on the same platform, they interfere with each other due to the use of shared resources. Interference: phenomenon for which the execution of a task affects the one of other tasks. In the following, we will identify the causes of interference present possible solutions 1 7

8 Interference mechanisms Tasks may interfere for different reasons: Time: concurrent access to shared resources, as processing units and communication channels. Space: due to sharing the same memory space (Cache, DRM, Hard Disk). Energy: sharing the energy source (battery). Temperature: eating up each other. 1 Why do we care? ecause interference has different negative effects: It decreases efficiency and schedulability It reduces predictability It jeopardizes safety It complicates the analysis 16

9 simple example pplication pplication P 1 P 2 P 3 P CPU 1: speed = 1 CPU 2: speed = 1 pplications + Priorities must be assigned P 1 P 2 Task interference can jeopardize predictability P 3 P Platform: speed = 2 17 Priority explosion! How many priority assignments satisfy both priority orders? P 1 P 2 P 3 P There are 6 priority assignments that satisfy both priority orders: 1 9

10 Non trivial questions How do computation times scale in the new platform? Which priority order do we choose? Do they all lead to a feasible schedule? re they different in terms of performance? How can we reduce the reciprocal interference? 19 Let s go into details C i T i C i T i P 1 2 P 3 2 P 2 P 6 (2,) (,) RM schedule (S = 1) RM schedule (S = 1) (2,) 1 (6,) 2 1

11 Now let s groups them How computation times scale in the new platform? C i T i speed = 2 2 ssume for simplicity P 1 C i 1 T i speed = 1 C i T i 2 6 speed = 1 C i = s C i P P 3 1 P 3 21 Now let s groups them If the new platform has a fixed priority scheduler, what is the best priority order? C i T i P 1 1 P 2 2 P 3 1 P 3 + RM ordering (optimal) 22 11

12 ll together are not feasible! (2,) (,) RM schedule (S = 1) RM schedule (S = 1) (2,) 1 (6,) + (1,) (1,) (2,) (3,) C i RM schedule (S = 2) assuming C i = s deadline miss 23 Example on 2 cores U = 1 U =.9 RM schedule (S = 1) RM schedule (S = 1) (2,) (2,) 1 (,) (6,) Rate Monotonic First Fit or est Fit U =.9 Core 1 (S = 1) U = 1 Core 2 (S = 1) miss 1 2

13 Course outline Motivation and examples 2. rief summary of uniprocessor analysis 3. Interference analysis and techniques to reduce it Temporal isolation Resource reservations servers Hierarchical component-based systems Schedulability analysis of single components Resource sharing protocols for hierarchical systems. Energy-aware scheduling Course outline - 2. Multiprocessor scheduling rchitecture issues and modeling Performance analysis Scheduling paradigms Task allocation and feasibility bounds 6. Processor abstraction and interface Efficient algorithms for the interface design. Multiprocessor abstractions. pplications models. pplication partitioning and resource allocation 13

14 Course outline Standards for component-based development RINC: a standard for avionic systems. UTOSR a standard for automotive systems. Component-oriented programming and models introduction to C++ patterns UML models of components code generation using patterns under Eclipse-EMF 9. Hypervisors The Xen project Guaranteeing real-time constraints on hypervisorbased systems 1