SPIRAL DSP Transform Compiler:

Transcription

1 SPIRAL DSP Trasform Compiler: Applicatio Specific Hardware Sythesis Peter A. Milder Fraz Frachetti, James C. Hoe, ad Marus Pueschel Departmet of ECE Caregie Mello Uiversity ow with SUNY Stoybroo ad ETH CMU/ECE/Hoe, February 03, slide

2 The SPIRAL Project High performace implemetatios of liear DSP trasforms (DFT, DCT, DWT, filters, etc) are a importat class of desig problems Had ddesig ad tuig is tricy ti ad expesive eeds both math ad implemetatio owledge time cosumig i ad tedious eeds to repeat effort for every ew cotext SPIRAL research goal: A flexible push butto desig geerator that produces SW & HW implemetatios comparable with expert had desig CMU/ECE/Hoe, February 03, slide

3 Why we ca do better tha had desig SPIRAL is oly focused o liear DSP trasforms These trasforms are highly structured, highly regular ad very well uderstood mathematically atca Algorithmic implemetatios of a trasform ca be eumerated followig a ow set of rules For a give objective fuctio ad mappig target, a computer geerates a solutio at least as good as the best huma effortby tryig eough implemetatios CMU/ECE/Hoe, February 03, slide 3

4 SPIRAL Framewor I wat a DFT of size 04 o a {Xilix, P4, Cell...} SPIRAL automatio starts here where most tools begi automatig the problem Priciple : Domai owledge i the system Priciple : Optimizatio at a high level of abstractio CMU/ECE/Hoe, February 03, slide 4

5 CMU/ECE/Hoe, February 03, slide 5

6 High Level, Quality, ad Specializatio High level: tools ow better tha you RTL Sythesis: geeral purpose but special hadlig of structures lie FSM, arith, etc. Place ad Route: ad wors the same o matter what desig CMU/ECE/Hoe, February 03, slide 6

7 Outlie SPIRAL Formula Framewor SPIRAL for HW FFT cores SPIRAL for HW FFT u core CMU/ECE/Hoe, February 03, slide 7

8 Liear Trasforms Liear trasform is a matrix vector multiplicatio computig by defiitio taes O(N ) operatios the matrix has structure E.g. discrete Fourier trasform: y = DFT N x y 0 y. y j j 0.. N- 0.. N- x 0 x. = e i j N x.... y N-. x N- CMU/ECE/Hoe, February 03, slide 8

9 Fast Algorithms Fast Algorithms a fast algorithm factors the matrix ito a sequece of structured sparsematrices structured, sparse matrices cheaper sparse multiplies O(N log(n)) operatios E g Cooley Tuey Factorizatio of DFT E.g. Cooley Tuey Factorizatio of DFT 4 i i i i i i i Matrix formula represetatio 4 4 CMU/ECE/Hoe, February 03, slide L DFT I D I DFT DFT

10 E.g. Cooley Tuey y DFT m Factorizatio Rules m m DFT I D I DFT L DFT is D is a diagoal matrix of twiddle factors L is a stride permutatio matrix AB=[a j, B] is the tesor (or roecer) product m m eg e.g., I B B BB 0 B A I a 0,0a0,0a0,0 0 a,0a a,0a,0 0 a 0, a0,a0, 0 0 a, 0 0 a,a, 0 CMU/ECE/Hoe, February 03, slide 0

11 Fast Fourier Trasform Algorithms Recursively factorize by the Cooley Tuey rule util oly leafcases remai (e.g. DFT r for radix r) r) DFT 8 DFT 8 I4 D I DFT4 8 4 DFT I D I DFT I D I DFT 8 L Expoetial umber of alteratives 4 8 L 4 L DFT 8 DFT 4 DFT DFT DFT DFT 8 DFT DFT 4 DFT DFT Each ruletree correspods a differet algorithm All cost O(N log(n)) CMU/ECE/Hoe, February 03, slide

12 A System of Trasforms ad Rules, / F ( ) DCT II diag ( II ) DCT P / / / DCT DCT DFT DFT ( IV ) ( IV ) m S ( II ) ( IV ) DCT DCT I F Q DCT ( II ) D M M r ( I ) ( I ) B ( DCT DST ) C / / DFT I D I DFT P F ( h) ( I / d I d ) ( I / d Fd ( h)) F ( h ) Circ ( h ) E DWT m ( W ) ( DWT / ( W ) I / ) P ( I / WHT ( I WHT I ) W ) E i m i i i t 50+ trasforms 50+ rules CMU/ECE/Hoe, February 03, slide

13 Algorithmic Desig Space size # of DFT # of DCT IV ~ ~ ~ ~ ~ ~ Differet characteristics: data flow, umerical stability, operatio orderig, worig set size, datapath regularity CMU/ECE/Hoe, February 03, slide 3

14 Desig Space: SW DCT 3 o P4 Histogram of 0,000 radomly selected algorithms histogram by rutime (P4, 3. GHz) histogram by um. accuracy CMU/ECE/Hoe, February 03, slide 4

15 Outlie SPIRAL Formula Framewor SPIRAL for HW FFT cores SPIRAL for HW FFT u core CMU/ECE/Hoe, February 03, slide 5

16 Formula to HW (Combiatioal) Give where is: apply, the is a permutatio permute apply, times i parallel is a diagoal scale B A A A CMU/ECE/Hoe, February 03, slide 6

17 DFT 8 Datapath Example x x x x x DFT x 8 4 DFT I D I DFT I D I DFT x x 4 8 L 8 4 L (formula is applied from right to left) CMU/ECE/Hoe, February 03, slide 7

18 Pease DFT Example 8 x x x x x x x x x x x x stage stage stage 3 CMU/ECE/Hoe, February 03, slide 8

19 How about good HW? Matrix formulas have a atural mappig to dataflow ad hece combiatioal datapath However, real hardware desigs must fit a give resource costrait sequetial datapath that reuse available HW idetify repeated erels istatiate erels uder resource costraits schedule hdl computatio tti to reuse istatiated ti t erels We wat to do the aalysis ad mappig at formula level, with high level algorithm owledge CMU/ECE/Hoe, February 03, slide 9

20 Tesor as Streamig Parallelism fully parallel fully streamed partially streamed CMU/ECE/Hoe, February 03, slide 0

21 Pease DFT Example: DFT 8 x x x x x x x x x x x x stage stage stage 3 CMU/ECE/Hoe, February 03, slide

22 Pease DFT Example: DFT 8 Streamig x x x f(l 8 ) f(l 8 ) f(l 8 ) f(r f(l 8 ) ) x x x f(l 8 ) f(l 8 ) f(l 8 ) f(r f(l 8 ) ) x x x stage stage stage 3 CMU/ECE/Hoe, February 03, slide

23 Regular Structure for HW Simple regular structure embodied i Pease FFT Example: CMU/ECE/Hoe, February 03, slide 3

24 Formally represetig horizotal reuse hr hr ot horizotally horizotally partially horizotally reused reused reused CMU/ECE/Hoe, February 03, slide 4

25 Iterative Reuse of Logic cost latecy Fie-graied cotrol over cost/latecy tradeoff CMU/ECE/Hoe, February 03, slide 5

26 Example: rewritig rules for streamig reuse 6 CMU/ECE/Hoe, February 03, slide 6

27 Applicability to other trasforms? pp y DFT radix 0 i i L DFT I T R DFT radix r 0 i / 0 r i r r r L DFT I T R D DFT x DFT I L i0 x WHT i0 / r L WHT I WHT DCT (type II) H P L L L A DP 0 i r r r L WHT I CMU/ECE/Hoe, February 03, slide 7 DCT (type II) H i i P L L L A DP 0

28 FPGA: Area vs vs. Throughput Pareto optimal 49x slices 3x throughput 8 CMU/ECE/Hoe, February 03, slide 8

29 Outlie SPIRAL Formula Framewor SPIRAL for HW FFT cores SPIRAL for HW FFT u core CMU/ECE/Hoe, February 03, slide 9

30 A D FFT Algorithm Row colum algorithm: D- Colum Stage Row Stage Dataset: (Logical abstractio of the D dataset) CMU/ECE/Hoe, February 03, slide 30

31 Off chip Data Sets off chip DRAM o chip SRAM DFT erel Need to balace erel processig badwidth off chip memory badwidth o chip storage capacity CMU/ECE/Hoe, February 03, slide 3

32 Iefficiet DRAM Access Patters Row wise traversal > Sequetial accesses Colum wise traversal > Large strided accesses row major D array 0 li ear mem m space Row buffer size CMU/ECE/Hoe, February 03, slide 3

33 How to Optimize the Access Patters row major bloced 0 liear mem spa ace Row buffer size i row buffer sized chus [Ai, et al., FCCM 0] CMU/ECE/Hoe, February 03, slide 33

34 Desig Geerator w/ Tesor Formalism colum stage row stage D- row colum algorithm symmetric algorithm symmetric algorithm with tilig write tiles colum wise traspose ad re tile o chip FFT processig liearize read tiles o chip row wise [Ai, et al., FCCM 0] CMU/ECE/Hoe, February 03, slide 34

35 D FFT (double) Raw Performace Problem Size [Ai, et al., FCCM 0] CMU/ECE/Hoe, February 03, slide 35

36 D FFT (double) BW Efficiecy Problem Size [Ai, et al., FCCM 0] CMU/ECE/Hoe, February 03, slide 36

37 D FFT (double) Power Efficiecy Problem Size [Ai, et al., FCCM 0] CMU/ECE/Hoe, February 03, slide 37

38 Coclusios Ecapsulatig domai owledge i a domai specific tool for high level desig automatio SPIRAL mathematical approach to DSP trasform implemetatio (cores ad u core) geeralizable to other liear DSP trasforms as good as best expert desiger Tha you CMU/ECE/Hoe, February 03, slide 38