AN ENHANCED CONTEXT-ADAPTIVE VARIABLE LENGTH CODING FOR H.264.

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1 Volume 120 No , ISSN: (on-line version) url: AN ENHANCED CONTEXT-ADAPTIVE VARIABLE LENGTH CODING FOR H.264. M.BALASUBRAMANI 1, S.KOKILA 2, S.PRIYA 3, 1,2 Assistant professor: ECE, 3 ME-VLSI Design, Vivekanandha College of Engineering for Women Thiruchengode, Tamilnadu, India mskbalasubramani@gmail.com eniyapriya6@gmail.com July 4, 2018 Abstract Context-Adaptive Variable Length Coding technique is used in modern video coding standard such as H.264. In existing CAVLC implementation coding code both the Chroma and Luma block simultaneously lead to low throughput. In the proposed paper, an enhanced CAVLC pixel values of Luma and Chroma are processed simultaneously. In an enhanced three stage pipeline architecture and then generate output NAL stream output. This lead to reduces the time and power. The proposed three stage architecture is synthesized in VHDL using Quartus II-9.1 in family cyclone III. Keywords: Encoder, H.264, CAVLC, Enhanced pipeline architecture

2 1 INTRODUCTION In today scenario, world is emphasized with internet streaming.video compression technique plays an immense role in the video conference, messaging, storage and HDTV appliance. For efficient transmission and storage, Context Adaptive Variable Length Coding (CAVLC) is adopted as the standard entropy coding from existing method[7]. coding efficiency achieved better in CAVLC, but increase in the performance of sub-encoder lead to hardware utilization [9] [2]. The hardware implementation makes it more difficult. The block diagram of H.264 encoder is illustrate in Fig.1. Figure 1: H.264 standard entropy coding. In H.264 Encoder, the block of Luma and Chroma are processed simultaneously. It deals with component of Chroma and Luma that generate output codes. In the existing paper, it achieves encoding blocks of low throughput and consume time generation by 40%. In this proposed paper, the Luma and Chroma pixel value are simultaneously processed and output code is generated as a stream. It exploits the waste time and maximizes the throughput with reduced time analysis. The rest paper is organized as follow: The overview of H.264 DCT in section 2. CAVLC algorithm overview in section 3. Related

3 works discussed in section 4. The proposed architecture design illustrate in section 5. The result of simulation in power and time analysis in section 6. Then the conclusion in final section. 2 OVERVIEW OF H.264 DCT Discrete Cosine transform, finite sequence of data points by summing up the cosine function for different oscillating frequency. DCTs have its own reliability in the field of science and engineering, their application in lossless compression of images (where high-frequency at small level being discarded), to spectral methods for partial differential equations in numerical solution. The function of cosine rather than sine is used. As the compression is of critical, since fewer cosine functions turns out are needed to approximate into a typical signal, whereas for differential equations the cosines are particular choice, express the boundary conditions. As it performs an orthogonal, symmetric, linear operations on 2m real number in the Fig.2. Figure 2: 2x2 multidimensional sub-block of DCT. Multidimensional 2x2 DCT is normalized to unitary. The image of two-dimensional Fourier transform is transmitted as the image itself over a channel rather than values. For high-speed computational,dcts rather than that of the fast Fourier transform algorithm, which performs the Hadamard transformation. In Hadamard transform only real number additions and subtractions are required with the, an order of magnitude speed advantage is possible compared to the complex number Fourier transform. an arbitrary input vector decomposes

4 into a superposition of Walsh function by the Hadamard transform. Where kj and nj are the binary digits(0 or 1) of k and n respectively. 3 OVERVIEW OF CAVLC ALGORITHM An enhanced three stage pipelined architecture of our proposed encoder design scans the coefficients and then analyzes the statistical characteristic of the input blocks. In this stage, the coefficient token table selector is integrated and the parameter nc to select the coding table being calculated for coefficient token encoding. Various encoders operate in parallel to encode syntax elements of the present block simultaneously. The encoding level takes places in five following steps. 1) Coefficient token coding. 2) Trial one sign coding. 3) Level coding. 4) Total zeros coding. 5) Run before coding. Step 1: Coefficient Token encoding:

5 The coefficient token encoding is syntax element presenting a pair of token: the number of trailing ones(±1) and the number of non-zero coefficients in a block. Depends on the number of nonzero coefficients in the upper and the left blocks,the VLC table selection taking place. If the number of non-zero coefficients in nu represents the upper block and the number of non-zero coefficients in nl represent the left block then, the VLC table of which will be selected be decided by parameter nc is calculated as follows: The coefficient token of a 4 4 Luma block nc is less than 2 is encoded using the table as VLC. If nc is greater than 1 then the table VLC1 is selected if and less than 4. The VLC2 is selected if nc is greater than 3 and less than 8. the Fixed Length Coding (FLC) table is used if nc is greater than 7. We also having a special table for encode the coefficient token of 2 2 Chroma block. Step 2: Trailing 1 sign coding: Each trailing one encoded with one bit in reverse order starts from the high frequency trailing one. If the trail one coefficient is 1 then the respective sign bit is zero ( 0 ). If the trail one coefficient is -1 then the sign bit is one ( 1 ). Step 3: Level encoding: Levels are encode in inversed zigzag order. In the level encoding, 7 VLC tables are used. The next VLC table is selected depending on the current VLC table and the magnitude of level. Encoding the first level using VLC0. Then there is increased in the VLC number, if the magnitude of the current level is larger than the current VLC correlate threshold. One exception is that if there are greater than 10 non zero coefficients and less than three trailing ones, by using table VLC1 the first level will be coded. Another exception is that if there are lower than three trailing ones, the first level coded with the magnitude is decremented by

6 Step 4: Total Zero encoding: In the zig-zag order, Total Zero defines the number of zero coefficients standing before the last non-zero coefficient. Total zero is encoded using 15 VLC tables selected by the number of non-zero coefficients in the Luma block. For encoding Chroma DC block three other tables are used. Step 5: Run Before coding: Run-before is sequence of number of zero coefficients standing before levels in zig-zag order. However, Run Before are encoded in reverse zig-zag order. The VLC table selection based on zero left information, that is, each Run Before is encoded after the number of zero left. Current zero left is equal to next zero left minus current run-before value. There are 7 VLC tables used in Run Before encoding. Finally, the structural output bitstream flow for one block data is in the following order: coefficient token, Trailing One signs, Levels, Total Zero, and Run-before. 4 RELATED WORK SURVEY In [1] FPGA based pipeline architecture along with dual stage architecture, achieve the low-cost memory requirement. The CAVLC entropy of efficient coding coefficient [8] which involves the redundancy of coefficient get reduced and removed. The features included in the 2 stage architecture are zero skipping technique, carried out for reducing 90% of cycles at low bitrates, exponential-golomb coding used for the general symbols and for the network abstraction layer bitstream encapsulation which are the following features get integrated in CAVLC engine to form complete entropy coder with baseline profile, the profile which achieves the least complex compare with other profile [11] [14].One block was handled by scanning engine for collecting the required symbol and in the meantime the previous block handled by the coding engine for symbol translation [2]. The translated symbol into bit stream is achieved in coding engine [4]. The arithmetic table eliminates technique, further reduces the area. The architecture capable of processing common/quarter intermediate format frame sequences [5]. An efficient internal

7 memory design and execution time reduced [10].Synchronization of variable length code words and error concealment [13]. Poor in the power performance due to their large consumption in residual SRAM and registered based symbol buffer[15]. This paper deals with the increase throughput with the waste time consumed. 5 PROPOSED ARCHITECTURE The three-stage enhanced pipelined architecture can encode three blocks (one 4x4 Luma and two 2x2 Chroma) in parallel and with a little increase of hardware utilization. It can almost half the processing cycles of CAVLC when the quantized residue energy is large in high-bit-rate situations. Figure 3: The proposed pipeline architecture. Input pixel value comes at top and is usually written to RAM and buffer it temporarily. When needed it is read in the prediction components such as inter4x4 and intra8x8. The transformed coefficients symbol count decreases with the

8 increasing of quantization parameter due to the large percent of zero coefficients. In this situation, the coefficient within 8x8 intra is zero and 4x4 inter are coded unnecessary. This process includes the memory access towards the buffer. Outputs from the prediction block fed to the transformed loop: core transform, DCT, quantize, dequantize, inverse transform, reconstruction block. For inter-frame encoding, these reconstructed pixels are required immediately to predict the flow of neighboring block, in addition, they are also written to RAM for the use of next inter-frame coding. In feedback section, for intra encoding the transformed loop is timing-critical, since the latency is important as that of the throughput. Transform modules need all data in before they output the first output pixel, but the delay between the last pixel in and the first pixel out is minimal. For blocks we can use DC as well as AC components in hardware utilization, a 2x2 DCT (Hadamard transform) is also provided as part of the feedback loop. In order to speed up the process and filter the noise in the respective core transform block. The intra 8x8 (which encodes Chroma for intra encoding) outputs, to the sums of each block as a separate DC data stream which is fed into the first DCT. The output from quantizing is fed to the buffer which delays and reorders the blocks for output to the CAVLC module which encodes the data. Header data fed from the header to CAVLC and the stream is turned into byte stream by the to bytes block, which also stuffs 03 bytes to prevent start code emulation. The output from to bytes is a NAL, and the done signal is asserted at the end. Multiple streams can be encoded simultaneously by the H.264 encoder; these may be of different resolutions. There is no design limit to the video resolution. 6 SIMULATION AND ANALYSIS An enhanced pipeline architecture for inter-frame encoding is used. Foreman with medium motion gives the general sequence. The mobile calendar gives high texture and has complex motion in this intra-frame coding plays a vital role. The weather has static background with a fast moving background in this inter-frame coding plays an important role. Comparing with the existing

9 method, the proposed method play both the inter and intra-frame coding with high throughput. It can almost half the processing cycle when the quantized energy and prediction are low bit rate situations most residues are zero, the processing phase must be high the simulated waveform and the time generation taken by the enhanced architecture of I and P prediction, CAVLC is analyzed. Figure 4: Simulation Waveform( I-prediction) Figure 5: Time Analysis (I-prediction) 7 CONCLUSION The proposed enhanced entropy gives high throughput simulation in CAVLC encoder. This paper focused on high-performance architecture applicable for real-time application of H.264 CAVLC encoder. It acquires low memory and time consumption

10 Figure 6: Simulation Waveform(P- prediction) Figure 7: Time Analysis (P- prediction) Figure 8: Simulation Waveform (CAVLC)

11 Figure 9: Time Analysis(CAVLC) In this paper, we presented high throughput with reduced time and consumes low power applicable to all real-time application. The proposed architecture is implemented in VHDL using Quartus II-9.1 in family cyclone III. The VHDL RTL code verified to work within 170 MHz. References [1] Arun Kumar Pradhan, Lalit Kumar Kanoje, and Biswa Ranjan Swain, FPGA based High-Performance CAVLC Implementation for H.264 Video Coding, International Journal of Computer Applications,vol.69, No.10, PP , May [2] Asma Ben Hmida, Salah Dhahri, and Abdelkrim Zitouni, A High-Performance Architecture Design of CAVLC Coding Suitable for Real-Time Applications, World Cong. on Multimedia and Computer Science, [3] Chang Su Han, and Jae Hun Lee, Area-Efficient And High Throughput CAVLC Encoder For 1920x1080@30p H.264/AVC, SAMSUNG ELECTRONICS CO., LTD., South Korea;ICCE.org,p-1-7,2009. [4] Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, and Jiun-In Guo, A High-Performance CAVLC Encoder Design for MPEG-4 AVC/H.264 Video Coding Applications, IEEE International Symposium on Circuits and Systems, PP ,

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