sfpdp core Specification

Transcription

1 sfpdp core Specification Abaco Systems Support Portal This document is the property of Abaco Systems and may not be copied nor communicated to a third party without the written permission of Abaco Systems. Abaco Systems 2014 UM

2 Revision History Date Revision Version First release Updated the document Added files description updated for Virtex Added support for CRC to Virtex-5 and Virtex Added support for Virtex Added support for Kintex7 1.5 UM

3 Table of Contents 1 Introduction Core usage and performance sfpdp transceiver sfpfp wrapper Supported sfpdp Configurations sfpdp installation overview Evaluation and Netlist Source Simulating the sfpdp core Implementing the sfpdp core UM

4 1 Introduction Serial front panel data port (sfpdp) is a serial communication protocol that is designed to have a low latency and a high transfer rate. Its application is in high-speed real-time applications. It is currently defined to be used with Gb, Gb, and 2.5 Gb data rates. The use of fiber optic cables allows sfpdp to operate over long distances (up to 10 KM). The Abaco sfpdp core is designed to implement the serial front panel data port protocol for use in FPGA devices. The core uses the FPGA specific high speed serialisers and deserialisers. A top level diagram, using the Xilinx Rocket IO, is depicted in Figure 1. sfpdp wrapper FIFO sfpfp tranceiver framer Xilinx Rocket IO MGT 2.5Gb/s FIFO Frame extract 2.5Gb/s Figure 1: sfpdp wrapper top level diagram UM

5 2 Core usage and performance Currently the core has been implemented and used in Xilinx FPGAs. These FPGAs include high speed serializers and de-serializers that can be used to drive the serial FPDP packets to an optical transceiver. The core typically uses the resources listed in the following table. Table 1: typical sfpdp core usage and performance Resource Usage Slices 406 Luts 471 Rocket IOs 1 Block RAM 2 max line rate 2.5 Gb/s 3 sfpdp transceiver The heart of the sfpfp core is the sfpdp_tranceiver module. This module takes care of encoding and decoding the sfpdp packets. The encoded data is available on the following signals. sfpdp_txcharisk sfpdp_txdata This port can connect directly to the transmit input of a Xilinx MGT or GTP. In the case of a Virtex-4 and Kintex-7 device the sfpdp_txdata port is 32 bits wide and the sfpdp_txcharisk port is 4 bits wide. In the case the core will be used in a Virtex-5 or Virtex-6the sfpdp_txdata_port will be 16 bits wide and the sfpdp_txcharisk port is 2 bits wide. Likewise the decoded data has to be made available on the following signals. sfpdp_rxcharisk sfpdp_rxdata This port can connect directly to the receive output of a Xilinx MGT or GTP. In the case of a Virtex-4 and Kintex-7device the sfpdp_rxdata port will be 32 bits wide and the sfpdp_rxcharisk port is 4 bits wide. In case the core will be used in a Virtex-5 or Virtex-6 the sfpdp_rxdata_port will be 16 bits wide and the sfpdp_rxcharisk port is 2 bits wide. Table 2: sfpdp tranceiver port description Port name Port direction Port width Description clk In 1 clock used to generate the core resets. rx_rst In 1 asynchronous reset of the rx part of the sfpdp transceiver rxclkout In 1 The sfpdp_rx signals will be synchronous to this clock. tx_rst In 1 asynchronous reset of the tx part of the sfpdp transceiver txclkin In 1 The sfpdp_tx signals will be synchronous to this clock. mgt0_rxlock_i In 1 input used for status reporting only, can be connected to GND. mgt0_txlock_i In 1 input used for status reporting only, can be connected to GND. flowcontrol_en In 1 enables the flow control for the sfpdp core. wait_for_nrdy In 1 When set the core waits until nrdy is asserted by the receiver copymode_en In 1 the core operates in copy mode. Make sure that the tx_clk and rx_clk are the same clock. UM

6 rx_en In 1 Enable the sfpdp core receiver tx_en In 1 Enable the sfpdp core transmitter rx_crc_en In 1 Enable CRC checking for received data tx_crc_en In 1 Enable generation of CRC for transmitted data rx_pio1 Out 1 Receiver PIO1 status received from the transmitter rx_pio2 Out 1 Receiver PIO2 status received from the transmitter rx_ndir Out 1 Receiver ndir status received from the transmitter rx_suspend Out 1 Receiver SUSPEND status received from the transmitter rx_nrdy Out 1 Receiver nrdy status received from the transmitter rx_fifo_ov Out 1 Receiver FIFO overflow rx_dvalid Out 1 Receiver Data valid. Valid every clock cycle after a valid data request. rx_sync Out 1 Receiver Sync. Valid every clock cycle after a valid data request. rx_data Out 32 Receiver data. Valid every clock cycle after a valid data request. rx_crc_error Out 1 Indicates a CRC error occurred on the last packet received rx_data_empty Out 1 The receive FIFO empty flag rx_data_overflow Out 1 The receiver FIFO overflow occurred rx_data_req In 1 Valid data will be output on the rx_sync, rx_dvalid and rx_data ports every clock cycle after the data_req is asserted and the rx_data_empty is de-asserted. tx_pio1 In Transmitter PIO1 whenever this signal changes its state is tx_pio2 In Transmitter PIO2 whenever this signal changes its state is tx_ndir In Transmitter ndir whenever this signal changes its state is tx_suspend In Transmitter SUSPEND whenever this signal changes its state is tx_nrdy In Transmitter nrdy whenever this signal changes its state is tx_dvalid In When asserted the tx_data will be serialised into the sfpdp link. tx_sync In When asserted when tx_dvalid is de-asserted a sync frame is transmitted. When asserted and when tx_dvalid is asserted, a sync with data packet is transmitted. tx_data In Data that will be serialised onto the sfpdp each time tx_dvalid is asserted. tx_data_full Out The transmit fifo is full. Stop sending data to prevent a fifo overflow. tx_data_overflow Out When asserted the transmit fifo has overflowed. sfpdp_txcharisk out 32/16 The coded data that can connect directly to an MGT or GTP transmit data port. sfpdp_txdata out 4/2 The control signals that can connect directly to an MGT or GTP char is K transmit port. sfpdp_rxcharisk in 32/16 The coded data input that can connect directly to an MGT or GTP receive data port. sfpdp_rxdata in 4/2 The control signals input that can connect directly to an MGT or GTP char is K receive port. UM

7 Figure 2: sfpfp transceiver data ports wave forms 4 sfpfp wrapper The sfpdp transceiver module needs to be combined with a serialiser-deserialiser component in order to produce the serial data stream. The sfpdp core comes with an example wrapper file that will make this combination. The wrapper instantiates an MGT or GTP core that was generated using the Xilinx core generator program. Table 3: sfpdp wrapper port description Port name Port direction Port width Description clk In 1 clock used to generate the core resets. rst In 1 asynchronous reset mgt_ref_clk_n In 1 negative reference clock for the MGT mgt_ref_clk_p In 1 positive reference clock for the MGT rxn In 1 negative receiver input pin rxp In 1 positive receiver input pin txn In 1 negative transmitter input pin txp In 1 positive transmitter input pin clkout out 1 recovered clock output tx_clk In 1 Clock used to synchronise the parallel transmit data input rx_clk In 1 Clock used to synchronise the parallel receive data output flowcontrol_en In 1 enables the flow control for the sfpdp core. wait_for_nrdy In 1 When set the core waits until nrdy is asserted by the receiver copymode_en In 1 the core operates in copy mode. Make sure that the tx_clk and rx_clk are the same clock. rx_en In 1 Enable the sfpdp core receiver tx_en In 1 Enable the sfpdp core transmitter UM

8 rx_crc_en In 1 Enable CRC checking for received data tx_crc_en In 1 Enable generation of CRC for transmitted data rx_pio1 Out 1 Receiver PIO1 status received from the transmitter rx_pio2 Out 1 Receiver PIO2 status received from the transmitter rx_ndir Out 1 Receiver ndir status received from the transmitter rx_suspend Out 1 Receiver SUSPEND status received from the transmitter rx_nrdy Out 1 Receiver nrdy status received from the transmitter rx_fifo_ov Out 1 Receiver FIFO overflow rx_dvalid Out 1 Receiver Data valid. Valid every clock cycle after a valid data request. rx_sync Out 1 Receiver Sync. Valid every clock cycle after a valid data request. rx_data Out 32 Receiver data. Valid every clock cycle after a valid data request. rx_crc_error Out 1 Indicates a CRC error occurred on the last packet received rx_data_empty Out 1 The receive FIFO empty flag rx_data_overflow Out 1 The receiver FIFO overflow occurred rx_data_req In 1 Valid data will be output on the rx_sync, rx_dvalid and rx_data ports every clock cycle after the data_req is asserted and the rx_data_empty is de-asserted. tx_pio1 In Transmitter PIO1 whenever this signal changes its state is tx_pio2 In Transmitter PIO2 whenever this signal changes its state is tx_ndir In Transmitter ndir whenever this signal changes its state is tx_suspend In Transmitter SUSPEND whenever this signal changes its state is tx_nrdy In Transmitter nrdy whenever this signal changes its state is tx_dvalid In When asserted the tx_data will be serialised into the sfpdp link. tx_sync In When asserted when tx_dvalid is de-asserted a sync frame is transmitted. When asserted and when tx_dvalid is asserted a sync with data packet is transmitted. tx_data In Data that will be serialised onto the sfpdp each time tx_dvalid is asserted. tx_data_full Out The transmit fifo is full. Stop sending data to prevent a fifo overflow. tx_data_overflow Out When asserted the transmit fifo has overflowed. 5 Supported sfpdp Configurations Serial FPDP is a data streaming protocol, rather than a network protocol. Therefore the protocol header does not provide for node identification or addressing. Instead, a Serial FPDP connection provides a link from the source interface to its destination(s). A return link can also optionally be provided. The most basic Serial FPDP system consists of a single transmitter, a single receiver, and an inter-connecting cable/link as shown below. This configuration does not provide for any feedback or flow control: UM

9 data The optional flow control signal is transmitted as part of the Serial FPDP frame structure. Flow control is set by the receiver and returned to the transmitter through a separate cable/link: Data flow control As flow control is sent across the return cable using standard Serial FPDP frames, this cable can also be used to transmit data to support bi-directional data flow: Data+flow control Data+flow control Bi-directional data flow without flow control is useful when transmit and receive channels do not go to the same end point: Data Data A Serial FPDP receiver using Copy Mode receives the data and control signals sent by the original Serial FPDP transmitter and re-transmits this information using the transmit section of the receiver. As this can be used to send the same bit stream to multiple end points and is very useful for data recording. Data Data Copy/loop mode is implemented with a return cable from the last receiver back to the transmitter. Any receiver node in a Copy/Loop mode system has the ability to set the flow control signal in the event of a pending Receive FIFO overflow condition. UM

10 Data+flow control Data+Flow control Data+flow control A Cyclic Redundancy Check (CRC) can be enabled for the transmitter, the receiver, or both. When CRC is enabled, the transmitter calculates the CRC on the outgoing data and appends the CRC word as an additional data word to each packet. When CRC is enabled for the receiver, the CRC is calculated on incoming data and then compared to the last data word in the packet. If a CRC error is detected, the rx_crc_error signal is asserted. The error signal is then cleared once a SOF is received by the core. UM

11 6 sfpdp installation overview After installation of the core you will find the following folder tree on the location that was chosen during the installation: <chosen directory> ----IP-core ----sfpdp Core ----Source ----V4 ----V5 ----V6 ----V7 ----K7 ----Evaluation ----V5 ----Netlist ----V4 ----V5 ----V6 ----V7 ----K7 Depending on the type of IP license that you have chosen you will be able to see the contents of the several directories. Three licensing levels have been defined: Evaluation: This does not require a license and gives the user a change to test the sfpdp core. The core is based on a netlist and is fully functional but it will time out after a specific amount of time ( between 3 and 8 minutes depending on the link speed). UM

12 Netlist: This license offers the usage of the core based on the netlist. The netlist is delivered for use during the place and route phase, as well as, a simulation file that can be used during simulation. Source: This license allows the user to also see the vhdl sources of the sfpdp core. 6.1 Evaluation and Netlist The evaluation and netlist directory structures are similar, only the sfpdp core netlist is different. For the evaluation license the netlist will stop functioning after 2 to 8 minutes. The netlist licenses will not time out. The following table describes the files and folders that are created. Table 4: Evaluation and netlist files and folders Folder File/folder Description VHDL xx_sfpdp_wrapper.vhd xx_sfpdp_test.vhd Xilinx This is the vhdl wrapper file that instantiates the sfpdp core plus the serial interface logic (MGT/GTP). This is a specific vhdl file that can be used to create a quick test. The file instantiates the wrapper and logic to transmit data. It expects the serial interface to have an external loop back and it will verify data that is received on the port. A few status LEDs report the status of the test. More detailed test can be done by using chipscope in combination with this test. This folder holds several Xilinx specific files that are required for simulation and synthesis. UCF xx_sfpdp_test.ucf This is an example UCF file that maps the signals and serial interfaces to match one of 4DSPs own hardware platforms. Testbench sfpdp_tranceiver_synthesis.vhd xx_sfpdp_wrapper_tb.vhd This is the netlist version of the sfpdp core that is required for synthesis. This file can be used to simulate the sfpdp core wrapper. It will provide clock and data to the wrapper and verify received data. Netlist xx_sfpdp_tranceiver.ngc This is the sfpdp core netlist that will be used during the place and route of your FPGA design. modelsim ISE xx_sfpdp_wrapper.do xx_wave.do xx_sfpdp_wrapper xx_sfpdp_test A compile script for modelsim to setup the simulation. Modelsim script to load signals to the wave form. Example ISE project that synthesises the sfpdp wrapper. Example ISE project that synthesises the sfpdp test. UM

13 6.2 Source The Source license allows the user to have access to the sfpdp vhdl sources. The following table describes the files and folders that are created. Table 5: Source license files and folders Folder File/folder Description xx_sfpdp_framer.vhd This the vhdl file that wraps the transmit data into the sfpdp packets. VHDL Testbench modelsim ISE xx_sfpdp_tranceiver.vhd xx_sfpdp_frame_extract.vhd Xilinx xx_sfpdp_framer_tb.vhd xx_sfpdp_core.do xx_wave.do sfpdp_core_xx The top level file of the sfpdp core that instantiates the framer and the frame extract modules as well as the transmit and receive fifos. This is the vhdl file that decodes incoming data packets and extracts the data. This folder holds several Xilinx specific files that are required for simulation and synthesis. This file can be used to simulate the sfpdp transceiver. It will provide clock and data to the transmit ports and it will verify received data. A compile script for modelsim to setup the simulation. Modelsim script to load signals to the wave form. Example ISE project that synthesises the sfpdp transceiver. 7 Simulating the sfpdp core The core is delivered with a vhdl file of the sfpdp_tranceiver specific FPGA family that you want to use. This file can be compiled for simulation in combination with the other test bench files. To set-up your simulator for simulating the sfpdp_tranceiver you must make sure you have followed the steps outlined in Chapter 3 of the RocketIO G Transceiver User Guide. In the sfpdp_core installation directory you will find the folder \modelsim\script\. In this folder there is a macro file that will set-up the simulation environment when you are using modelsim. Otherwise this macro file can be used as a guideline to set-up your simulation in another simulator. 8 Implementing the sfpdp core The core is delivered with a synthesizable netlist of the sfpdp_tranceiver for the device family that you want to use. This file can be used to implement the sfpdp_tranceiver in the FPGA using the Xilinx ISE tools. In the sfpdp_core installation folder you will find the folder \ISE\xx_sfpdp_wrapper\ (where xx is the device family V4 or V5). This folder holds the ISE project that will implement the example sfpdp wrapper into the FPGA. UM