Feasiblity of Radio over Ethernet -demonstration with time synch. Peter K. Cho, A. Kim, J. Choi Actus Networks/HFR, Inc

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1 Feasiblity of Radio over Ethernet -demonstration with time synch. Peter K. Cho, A. Kim, J. Choi Actus Networks/HFR, Inc

2 Compliance with IEEE Standards Policies and Procedures Subclause of the IEEE-SA Standards Board Bylaws states, "While participating in IEEE standards development activities, all participants...shall act in accordance with all applicable laws (nation-based and international), the IEEE Code of Ethics, and with IEEE Standards policies and procedures." The contributor acknowledges and accepts that this contribution is subject to The IEEE Standards copyright policy as stated in the IEEE-SA Standards Board Bylaws, section 7, and the IEEE- SA Standards Board Operations Manual, section 6.1, The IEEE Standards patent policy as stated in the IEEE-SA Standards Board Bylaws, section 6, and the IEEE-SA Standards Board Operations Manual, section 6.3, 2

3 IEEE 1914 Next Generation Fronthaul Interface Jingri Huang, Feasibility of RoE Date: : Author(s): Name Affiliation Phone [optional] [optional] A. Kim Sejong University akim@sejong.ac.kr Peter Cho Actus Networks/HFR Inc. choho@actusnetworks. com Jin Seek Choi Hanyang University jinseek@hanyang.ac.kr

4 Exp. Overview Demonstration of a RoE system for feasibility Structure agonistic RoE mappers interfacing with CPRI Timing issue (experiment with no buffer management) Clock distribution mechanism - 10MHz clock and 1PPS provided by 1588v2 - hybrid 1588 (clock from 10G synce and 1PPS from 1588v2) frequency accuracy, jitter 4

5 RoE Presentation Time = ingress time + Networking delay(transit time) + processing / buffering delay 5

6 Configuration Measurements with a CPRI TRx port1: RoE #1->#2 (downlink) port2: RoE #1<-#2 (uplink) ; down/uplinks are symmetric TX Clock Source : Received(slave) CPRI Link (2457.6Mbps) Pattern type :PRBS15 The same signals are fed to both ports 6

7 measurement on performance Check the CPRI alarm and CV (Code Violation) during the transmission of CPRI frames Measure the delay for various sizes of RoE payload paylord size = 48/64 CPRI Basic frames intrinsic delay = ns(16byte) x 48 frame = us (for 48 frames) = us (for 64 frames) exp. senario No. Test Case Clock distritution Remark Case #1 board loopback ( single RoE mapper board) 10MHz clock, 1PPS by 1588v2 single mapper board without TSN switches - with inputs of 10MHz clock & 1 PPS provided by 1588v2 Case #2 Mapper2mapper (w/o TSN Switch) 10MHz clock, 1PPS by 1588v2 Case #3 RoE2RoE (a mapper with a TSN switch) 10MHz clock, 1PPS by 1588v2 a mapper pair without TSN switches - with inputs of 10MHz clock & 1 PPS provided by 1588v2 RoE consisting of a mapper + a TSN switch - with inputs of 10MHz clock & 1 PPS provided by 1588v2 Case #4 Mapper2mapper with direct 1588v2 clock direct clock fed by 1588 master a mapper pair w/o TSN sw. - with direct clock feeding by 1588v2 grand master1588v2 Master accuracy issue 7

8 General Configuration : case #3. RoE to RoE - RoE consisting of a mapper + a TSN switch - with inputs of 10MHz clock & 1 PPS provided by 1588v2 BB U GPS Receiver SFP FMC- XM10 5 RoE Mapper SFP+ 1588v2 Grand Master 10MHz 1PPS SFP v 2 OC TSN Switch SFP + PTP Packet PSN SFP v 2 OC TSN Switch SFP + 10MHz 1PPS SFP+ FMC- XM10 5 RoE Mapper SF P RR H RoE #1(DP1) RoE#2(DP2) CPRI Tester (slave) Port#1 Port#2 CPRI Tester (slave) downlink uplink 8

9 Result Measure ingress/presentation time and delay after at least 300 counts (300sec) Check the CPRI alarm and LCV (Line Code Violation) during the transmission of CPRI signals ; no errors, LOS, LOF, LSS and alarms(rai) for RoE packets of both 48 and 64 CPRI BF frames <result for PDU size of 64 CPRI frames> Case (for 64 frame ) 1.Board loopback Max RoE #1(DP1) ->#2(DP2) #1(DP1)[for case1] Min Avg variation Max 16.80us 16.69us 16.75us 0.11us 16.96u s 2. Map2map us 16.61us 16.53us 0.05us 16.64u s 3.RoE2RoE 16.78us 16.73us 16.76us 0.05us 16.83u s 4.map2map. with direct master clock 16.53us 16.49us 16.51us 0.04us 16.50u s RoE #1(DP1)<- #2(DP2) #2(DP2) [for case1] Min Avg variation 16.88us 16.92us 0.08us 16.44us 16.53us 0.20us 16.77us 16.80us 0.06us 16.45us 16.47us 0.05us 9

10 result for PDUsize of 48 CPRI frames Case (for 48 frame ) 1.Board loopback Max RoE #1(DP1) ->#2(DP2) #1(DP1)[for case1] Min Avg variation Max RoE #1(DP1)<- #2(DP2) #2(DP2) [for cas Min Avg Dela variati 12.65us 12.61us 12.63us 0.04us 12.52us 12.34us 12.42us 0.18u 2. Map2map us 12.58us 12.61us 0.06us 12.77us 12.58us 12.68us 0.19u 3.RoE2RoE 12.66us 12.61us 12.63us 0.05us 12.72us 12.51us 12.61us 0.21u 4.map2map. with direct master clock 12.54us 12.50us 12.52us 0.04us

11 measurement on clock performance Measure the performance regarding clock recoverty, frequency accuracy under ITU-T G.8261/Y.1361 based profiles Layer 2 (BBU-RRH) : frequency accuracy budget Layer 1 (Fronthaul) : total jitter Fronthaul solution is applicable section of the Layer 1 CPRI link BBU (REC) and RRH (RRE). To measure the Service Access Point (SAPs) of Layer 2, BBU/RRH are needed. 11

12 Estimate jitter by measuring CPRI link. -> CPRI Option 3 ( Gbps) ± 0.002ppm => ± 5 bit ( < 2 ns) -> CPRI Option 7 ( Gbps) ± 0.002ppm => ± 1 bit ( < 0.5 ns) Measure MTIE with - Network Traffic model 1 80 / 5 / 15% of the load must be min./ medium/ max. size packets (64/576/1518 octets) Maximum size packets will occur in bursts lasting between 0.1s and 3s -Network Traffic model 2 30 / 10 / 60% of the load must be min./ medium/ max. size packets (64/576/1518 octets) Maximum size packets will occur in bursts lasting between 0.1s and 3s

13 Measure frequency drift with G.8261 test cases Test case 12 with traffic model 2 network disturbance load with 80% in the forward direction (Server-> Client) and 20% in the reverse direction (Client -> Server) for 1 hour Frequency output MTIE 1PPS output ; wander Test case 13 with traffic model 1 network disturbance load with 80% for 1hour and disturbance with 20% for the next 1hr in the forward direction and disturbance with 50% for 1hr and with 10% for the next 1hr in the reverse direction

14 Result PARAMETER SPECIFICATION E2E CPRI CONNECTIVITY / ETHERNET TRAFFIC TEST value NO CV ONE WAY DELAY 16.78US (64 FRAMES) 12.61US (48 FRAMES) JITTER 3.75PS/15.4PS (UP/DOWN LINK) 12.47PS (DOWN+UPLINK) BER <10-12 MAXIMUM DISTANCE 83.12US FOR 12.6KM

15 Conclusion and future plan for implementation Demonstration of a RoE system with RoE structure agonistic mapper interfacing with legacy radio systems variation controllable by buffering (<15ms) in-building deployment of RoE, however, is appropriate delaywise and size of BBU pools and fiber infrastructure in buildings are correlated. Other options for implementation - frequency accuracy<2ppm is challenging; analyze on performance vs. frequency accuracy - current experimental limits according to the clock distribution (10 MHz clock and 1PPS provided by 1588v2) => hybrid 1588 (clock from 10G synce and 1PPS from 1588v2) - timestamp for buffer management - Specification on timing parameters 15

16 Thanks 16