Fast Prototyping from Assertions: a Pragmatic Approach
|
|
|
- Winifred Robbins
- 5 years ago
- Views:
Transcription
1 Fast Prototyping from Assertions: a Pragmatic Approach K. Morin-Allory, N. Javaheri, D. Borrione TIMA Laboratory October 17, /20
2 SoC Design Flow: Protocols or Control Part 2/20
3 SoC Design Flow: Protocols or Control Part 2/20
4 SoC Design Flow: Protocols or Control Part 2/20
5 Outline PSL and the generalized Buffer Reactant synthesis Annotation and Directed Abstract Syntax Tree (DAST) Unsettled direction Experimental results 3/20
6 Generalized Buffer IBM: Homepage/tutorial3/index.html 4/20
7 Generalized Buffer IBM: Homepage/tutorial3/index.html 4/20
8 Generalized Buffer IBM: Homepage/tutorial3/index.html 4/20
9 GenBuf Specification The 4-phase handshake protocol: The sender side always ((BtoS ACK 0 and StoB REQ 0) next! (BtoS ACK 0)); 5/20
10 Complete specification of the 4-phase handshake protocol P1: always ((not BtoS ACK 0) and (not StoB REQ 0) next! (not BtoS ACK 0)); P2: always ((BtoS ACK 0 and StoB REQ 0) next! (BtoS ACK 0)); P3: always (rose(stob REQ 0) not BtoS ACK 0); P4: always ( not BtoS ACK 0 or not BtoS ACK 1 ); P5: always (ENQ BtoS ACK 0 or BtoS ACK 1); P6: always (not ENQ not BtoS ACK 0 and not BtoS ACK 1); 6/20
11 Complete specification of the 4-phase handshake protocol P1: always ((not BtoS ACK 0) and (not StoB REQ 0) next! (not BtoS ACK 0)); P2: always ((BtoS ACK 0 and StoB REQ 0) next! (BtoS ACK 0)); P3: always (rose(stob REQ 0) not BtoS ACK 0); P4: always ( not BtoS ACK 0 or not BtoS ACK 1 ); P5: always (ENQ BtoS ACK 0 or BtoS ACK 1); P6: always (not ENQ not BtoS ACK 0 and not BtoS ACK 1); 6/20
12 Design Synthesis 7/20
13 From PSL to reactants A library of primitive reactants: One primitive reactant for each PSL operator 8/20
14 From PSL to reactants A library of primitive reactants: One primitive reactant for each PSL operator A generic interface and a generic architecture Cond: monitored operand Trigger: start of the next module or generated operands 8/20
15 Property Synthesis Reactant always (( BtoS ACK 0 and StoB REQ 0) next! (BtoS ACK 0)); 9/20
16 Property Synthesis Reactant always (( BtoS ACK 0 and StoB REQ 0) next! (BtoS ACK 0)); 9/20
17 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
18 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) a down edge means generation always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
19 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) Operator always: always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
20 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) Operator imply: Propagation of a down edge to at least one child always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
21 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) Operator imply: An up edge means observation always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
22 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) Propagation of an up edge to both children always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
23 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) Operator next: always ((BtoS ACK 0 and StoB REQ 0 next! (BtoS ACK 0)) 10/20
24 Directed Abstract Syntax tree and annotation Formal definition in VLSI SOC (october 2013, Istanbul) always ((BtoS ACK 0 m and StoB REQ 0 m) next! (BtoS ACK 0 g)) 10/20
25 Unsettled Edges P5:Always ENQ BtoS ACK 0 or BtoS ACK 1 11/20
26 Unsettled Edges P5:Always ENQ BtoS ACK 0 or BtoS ACK 1 Signals BtoS ACK 0 and BtoS ACK 1 are not annotated. Impossible to generate them simultaneously because: P4: always ( not BtoS ACK 0 or not BtoS ACK 1 ) 11/20
27 Set of properties Restriction of the graphs to unsettled edge. 12/20
28 Set of properties Restriction of the graphs to unsettled edge. 12/20
29 Set of properties Restriction of the graphs to unsettled edge. 12/20
30 Set of properties Restriction of the graphs to unsettled edge. 12/20
31 Set of properties Restriction of the graphs to unsettled edge. 12/20
32 Computation of signals solved together Merge of graphs 13/20
33 Computation of signals solved together Merge of graphs 13/20
34 Computation of signals solved together Merge of graphs Computation of strongly connected components (BtoS ACK 0, BtoS ACK 1) 13/20
35 Computation of signals solved together Merge of graphs Computation of strongly connected components (BtoS ACK 0, BtoS ACK 1) Extraction of equations 13/20
36 Resolution 14/20
37 Resolution 14/20
38 Resolution ABC: alanmi/abc/ 14/20
39 The whole circuit 15/20
40 The construction flow 16/20
41 The construction flow 16/20
42 The construction flow 16/20
43 The construction flow 16/20
44 The construction flow 16/20
45 Results Ratsy: 17/20
46 Results Ratsy: 17/20
47 Results Ratsy: 17/20
48 Results Ratsy: 17/20
49 Conclusion: A new design flow? Is it Possible? Yes 18/20
50 Conclusion: A new design flow? Is it Possible? Yes Is it worth it? Well... 18/20
51 Fast prototyping from assertions: what good is it for? Defining and verifying the specifications: Generation of waveforms Generation of theorems to prove the consistency and the completeness of the specification Generation of a golden model (only if the specification was complete) Generation of a simplified environment for on line testing of a design simulation prototyping 19/20
52 Fast prototyping from assertions: what good is it for? Defining and verifying the specifications: Generation of waveforms Generation of theorems to prove the consistency and the completeness of the specification Generation of a golden model (only if the specification was complete) Generation of a simplified environment for on line testing of a design simulation prototyping 19/20
53 Fast prototyping from assertions: what good is it for? Defining and verifying the specifications: Generation of waveforms Generation of theorems to prove the consistency and the completeness of the specification Generation of a golden model (only if the specification was complete) Generation of a simplified environment for on line testing of a design simulation prototyping 19/20
54 Fast prototyping from assertions: what good is it for? Defining and verifying the specifications: Generation of waveforms Generation of theorems to prove the consistency and the completeness of the specification Generation of a golden model (only if the specification was complete) Generation of a simplified environment for on line testing of a design simulation prototyping 19/20
55 Future Works Combine with a model checker to very the specification coherency and consistency Apply optimizations on the design Work on bit vectors and integers Define guidelines for the PSL subset for synthesis 20/20
Property-based design with HORUS / SYNTHORUS
Property-based design with HORUS / SYNTHORUS Dominique Borrione, Negin Javaheri, Katell Morin-Allory, Yann Oddos, Alexandre Porcher Radboud University, Nijmegen 1 March 27, 2013 Functional specifications
ON THE EFFECTIVENESS OF ASSERTION-BASED VERIFICATION
ON THE EFFECTIVENESS OF ASSERTION-BASED VERIFICATION IN AN INDUSTRIAL CONTEXT L.Pierre, F.Pancher, R.Suescun, J.Quévremont TIMA Laboratory, Grenoble, France Dolphin Integration, Meylan, France Thales Communications
Is Power State Table Golden?
Is Power State Table Golden? Harsha Vardhan #1, Ankush Bagotra #2, Neha Bajaj #3 # Synopsys India Pvt. Ltd Bangalore, India 1 dhv@synopsys.com 2 ankushb@synopsys.com 3 nehab@synopsys.com Abstract: Independent
Mathematica for the symbolic. Combining ACL2 and. ACL2 Workshop 2003 Boulder,CO. TIMA Laboratory -VDS Group, Grenoble, France
Combining ACL2 and Mathematica for the symbolic simulation of digital systems AL SAMMANE Ghiath, BORRIONE Dominique, OSTIER Pierre, SCHMALTZ Julien, TOMA Diana TIMA Laboratory -VDS Group, Grenoble, France
Paths. Path is a sequence of edges that begins at a vertex of a graph and travels from vertex to vertex along edges of the graph.
Paths Path is a sequence of edges that begins at a vertex of a graph and travels from vertex to vertex along edges of the graph. Formal Definition of a Path (Undirected) Let n be a nonnegative integer
MODELING LANGUAGES AND ABSTRACT MODELS. Giovanni De Micheli Stanford University. Chapter 3 in book, please read it.
MODELING LANGUAGES AND ABSTRACT MODELS Giovanni De Micheli Stanford University Chapter 3 in book, please read it. Outline Hardware modeling issues: Representations and models. Issues in hardware languages.
Assertions: Too good to be reserved for verification only.
Assertions: Too good to be reserved for verification only. Written by Brian Bailey Abstract There has been a lot of talk in the industry about the usefulness of assertions as part of a complete verification
ELEMENTARY NUMBER THEORY AND METHODS OF PROOF
CHAPTER 4 ELEMENTARY NUMBER THEORY AND METHODS OF PROOF Copyright Cengage Learning. All rights reserved. SECTION 4.6 Indirect Argument: Contradiction and Contraposition Copyright Cengage Learning. All
SEQUENCES, MATHEMATICAL INDUCTION, AND RECURSION
CHAPTER 5 SEQUENCES, MATHEMATICAL INDUCTION, AND RECURSION Alessandro Artale UniBZ - http://www.inf.unibz.it/ artale/ SECTION 5.5 Application: Correctness of Algorithms Copyright Cengage Learning. All
ECEU530. Schedule. ECE U530 Digital Hardware Synthesis. Datapath for the Calculator (HW 5) HW 5 Datapath Entity
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 6, 2006 Classes November 6 and 8 are in 429 Dana! Lecture 15: Homework 5: Datapath How to write a testbench for synchronous
Specifying circuit properties in PSL
Specifying circuit properties in PSL Formal methods Mathematical and logical methods used in system development Aim to increase confidence in riktighet of system Apply to both hardware and software 1 Formal
Assertion Checker Synthesis for FPGA Emulation
Assertion Checker Synthesis for FPGA Emulation Chengjie Zang, Qixin Wei and Shinji Kimura Graduate School of Information, Production and Systems, Waseda University, 2-7 Hibikino, Kitakyushu, 808-0135,
MYGEN : Automata-Based On-line Test Generator for Assertion-Based Verification
MYGEN : Automata-Based On-line Test Generator for Assertion-Based Verification Yann Oddos, Katell Morin-Allory, Dominique Borrione TIMA Laboratory, Université Joseph Fourier Grenoble, France name.surname@imag.fr
Logic Verification 13-1
Logic Verification 13-1 Verification The goal of verification To ensure 100% correct in functionality and timing Spend 50 ~ 70% of time to verify a design Functional verification Simulation Formal proof
Diagnostic Information for Control-Flow Analysis of Workflow Graphs (aka Free-Choice Workflow Nets)
Diagnostic Information for Control-Flow Analysis of Workflow Graphs (aka Free-Choice Workflow Nets) Cédric Favre(1,2), Hagen Völzer(1), Peter Müller(2) (1) IBM Research - Zurich (2) ETH Zurich 1 Outline
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols Martin Straka, Jiri Tobola, Zdenek Kotasek Faculty of Information Technology Brno University of Technology Bozetechova 2, Brno,
TIMA Lab. Research Reports
ISSN 1292-862 TIMA Lab. Research Reports A Model for Assertion-Based Verification of TLM Designs Laurence PIERRE ISRN: TIMA-RR--07/09-01--FR TIMA Laboratory 46 Av. Félix Viallet, 38031 Grenoble cedex,
Using macros to mimic VHDL in ACL2
Using macros to mimic VHDL in ACL2 Dominique Borrione & Philippe Georgelin TIMA, Grenoble, France ACL2 Workshop Austin, Texas, March 1999 VDS Dominique Borrione & Philippe Georgelin 1 Contents Context
SEMANTIC ANALYSIS TYPES AND DECLARATIONS
SEMANTIC ANALYSIS CS 403: Type Checking Stefan D. Bruda Winter 2015 Parsing only verifies that the program consists of tokens arranged in a syntactically valid combination now we move to check whether
SEQUENCES, MATHEMATICAL INDUCTION, AND RECURSION
CHAPTER 5 SEQUENCES, MATHEMATICAL INDUCTION, AND RECURSION Copyright Cengage Learning. All rights reserved. SECTION 5.5 Application: Correctness of Algorithms Copyright Cengage Learning. All rights reserved.
Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC
Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1 Agenda Integrated Hardware / Software Top
ECE 587 Hardware/Software Co-Design Lecture 11 Verification I
ECE 587 Hardware/Software Co-Design Spring 2018 1/23 ECE 587 Hardware/Software Co-Design Lecture 11 Verification I Professor Jia Wang Department of Electrical and Computer Engineering Illinois Institute
Lesson 19: The Graph of a Linear Equation in Two Variables is a Line
Lesson 19: The Graph of a Linear Equation in Two Variables is a Line Classwork Exercises Theorem: The graph of a linear equation y = mx + b is a non-vertical line with slope m and passing through (0, b),
1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2
Synthesis The Y-diagram Revisited Structural Behavioral More abstract designs Physical CAD for VLSI 2 1 Structural Synthesis Behavioral Physical CAD for VLSI 3 Structural Processor Memory Bus Behavioral
THE USE of assertions in hardware [1] has increased
![THE USE of assertions in hardware [1] has increased](/thumbs/87/96040064.jpg "THE USE of assertions in hardware [1] has increased")
1436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 9, SEPTEMBER 2010 Validating Assertion Language Rewrite Rules and Semantics with Automated Theorem Provers
Mesh-Based Content Routing Using XML
Outline Mesh-Based Content Routing Using XML Alex C. Snoeren, Kenneth Conley, and David K. Gifford MIT Laboratory for Computer Science Presented by: Jie Mao CS295-1 Fall 2005 2 Outline Motivation Motivation
P2VSIM: A SIMULATION AND VISUALIZATION TOOL FOR THE P2V COMPILER. A Thesis OSCAR MICHAEL ALMEIDA
P2VSIM: A SIMULATION AND VISUALIZATION TOOL FOR THE P2V COMPILER A Thesis by OSCAR MICHAEL ALMEIDA Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements
Theorem proving. PVS theorem prover. Hoare style verification PVS. More on embeddings. What if. Abhik Roychoudhury CS 6214
Theorem proving PVS theorem prover Abhik Roychoudhury National University of Singapore Both specification and implementation can be formalized in a suitable logic. Proof rules for proving statements in
Design Verification Lecture 01
M. Hsiao 1 Design Verification Lecture 01 Course Title: Verification of Digital Systems Professor: Michael Hsiao (355 Durham) Prerequisites: Digital Logic Design, C/C++ Programming, Data Structures, Computer
Introduction to Asynchronous Circuits and Systems
RCIM Presentation Introduction to Asynchronous Circuits and Systems Kristofer Perta April 02 / 2004 University of Windsor Computer and Electrical Engineering Dept. Presentation Outline Section - Introduction
System-On-Chip Architecture Modeling Style Guide
Center for Embedded Computer Systems University of California, Irvine System-On-Chip Architecture Modeling Style Guide Junyu Peng Andreas Gerstlauer Rainer Dömer Daniel D. Gajski Technical Report CECS-TR-04-22
0. Overview of this standard Design entities and configurations... 5
Contents 0. Overview of this standard... 1 0.1 Intent and scope of this standard... 1 0.2 Structure and terminology of this standard... 1 0.2.1 Syntactic description... 2 0.2.2 Semantic description...
SVA Advanced Topics: SVAUnit and Assertions for Formal
SVA Advanced Topics: SVAUnit and Assertions for Formal SystemVerilog Assertions Verification with SVAUnit Andra Radu Ionuț Ciocîrlan 2/29/2016 Andra Radu - AMIQ Consulting Ionuț Ciocîrlan - AMIQ Consulting
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties Marc Boulé and Zeljko Zilic McGill University, Montréal, Québec, Canada marc.boule@elf.mcgill.ca, zeljko.zilic@mcgill.ca Abstract
Lecture 2 Hardware Description Language (HDL): VHSIC HDL (VHDL)
Lecture 2 Hardware Description Language (HDL): VHSIC HDL (VHDL) Pinit Kumhom VLSI Laboratory Dept. of Electronic and Telecommunication Engineering (KMUTT) Faculty of Engineering King Mongkut s University
(2,4) Trees. 2/22/2006 (2,4) Trees 1
(2,4) Trees 9 2 5 7 10 14 2/22/2006 (2,4) Trees 1 Outline and Reading Multi-way search tree ( 10.4.1) Definition Search (2,4) tree ( 10.4.2) Definition Search Insertion Deletion Comparison of dictionary
A Functional Specification and Validation Model for Networks on Chip in the ACL2 Logic
A Functional Specification and Validation Model for Networks on Chip in the ACL2 Logic J. Schmaltz * and D. Borrione TIMA Laboratory - VDS Group Grenoble, France * Part of this work was done while visiting
Leveraging Formal Verification Throughout the Entire Design Cycle
Leveraging Formal Verification Throughout the Entire Design Cycle Verification Futures Page 1 2012, Jasper Design Automation Objectives for This Presentation Highlight several areas where formal verification
Formal Verification of Synchronizers in Multi-Clock Domain SoCs. Tsachy Kapschitz and Ran Ginosar Technion, Israel
Formal Verification of Synchronizers in Multi-Clock Domain SoCs Tsachy Kapschitz and Ran Ginosar Technion, Israel Outline The problem Structural verification 1CD control functional verification MCD control
A Synthesizable RTL Design of Asynchronous FIFO Interfaced with SRAM
A Synthesizable RTL Design of Asynchronous FIFO Interfaced with SRAM Mansi Jhamb, Sugam Kapoor USIT, GGSIPU Sector 16-C, Dwarka, New Delhi-110078, India Abstract This paper demonstrates an asynchronous
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
A Temporal Assertion Extension to Verilog
A Temporal Assertion Extension to Verilog Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, and Sy-Yen Kuo Graduate Institute of Electronics Engineering, National Taiwan University 1, Sec. 4, Roosevelt Rd., Taipei,
The Eval/Apply Cycle Eval. Evaluation and universal machines. Examining the role of Eval. Eval from perspective of language designer
Evaluation and universal machines What is the role of evaluation in defining a language? How can we use evaluation to design a language? The Eval/Apply Cycle Eval Exp & env Apply Proc & args Eval and Apply
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 2 Intro to Electrical and Computer Engineering Lecture 5 Boolean Algebra Overview Logic functions with s and s Building digital circuitry Truth tables Logic symbols and waveforms Boolean algebra
REQUIREMENTS AND CONCEPTS FOR TRANSACTION LEVEL ASSERTION REFINEMENT
REQUIREMENTS AND CONCEPTS FOR TRANSACTION LEVEL ASSERTION REFINEMENT Wolfgang Ecker Infineon Technologies AG IFAG COM BTS MT SD 81726 Munich, Germany Wolfgang.Ecker@infineon.com Volkan Esen, Thomas Steininger,
Sizing Router Buffers
Sizing Router Buffers Sachin Katti, CS244 Slides courtesy: Nick McKeown Routers need Packet Buffers It s well known that routers need packet buffers It s less clear why and how much Goal of this work is
Induction and Recursion. CMPS/MATH 2170: Discrete Mathematics
Induction and Recursion CMPS/MATH 2170: Discrete Mathematics Outline Mathematical induction (5.1) Sequences and Summations (2.4) Strong induction (5.2) Recursive definitions (5.3) Recurrence Relations
CS/ECE 5780/6780: Embedded System Design
CS/ECE 5780/6780: Embedded System Design John Regehr Lecture 18: Introduction to Verification What is verification? Verification: A process that determines if the design conforms to the specification.
Using SystemC to Implement Embedded Software
Using SystemC to Implement Embedded Software Brijesh Sirpatil James M. Baker, Jr. James R. Armstrong Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA Abstract This
Outline. Proof Carrying Code. Hardware Trojan Threat. Why Compromise HDL Code?
Outline Proof Carrying Code Mohammad Tehranipoor ECE6095: Hardware Security & Trust University of Connecticut ECE Department Hardware IP Verification Hardware PCC Background Software PCC Description Software
FLEXIBLE USB 2.0-BASED ADDRESS- EVENT REPRESENTATION ROUTER
FLEXIBLE USB 2.0-BASED ADDRESS- EVENT REPRESENTATION ROUTER Matthew Carlberg Department of Electrical Engineering Columbia University New York, NY 10027 mac2115@columbia.edu Marc Goldman Department of
Towards A Formal Theory of On Chip Communications in the ACL2 Logic
(c) Julien Schmaltz, ACL2 2006, San José August 15-16 p. 1/37 Towards A Formal Theory of On Chip Communications in the ACL2 Logic Julien Schmaltz Saarland University - Computer Science Department Saarbrücken,
Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)
1 Introduction............................................... 1 1.1 Functional Design Verification: Current State of Affair......... 2 1.2 Where Are the Bugs?.................................... 3 2 Functional
7.3.3 Same Inputs in Antecedent and Consequent
Formal Verification Using Assertions 249 There are some special scenarios in which the user may want to intentionally toggle the reset signal during a session. This may be needed to check conditions such
Design and Synthesis for Test
TDTS 80 Lecture 6 Design and Synthesis for Test Zebo Peng Embedded Systems Laboratory IDA, Linköping University Testing and its Current Practice To meet user s quality requirements. Testing aims at the
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Appear in th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 9 Chicago, Illinois, October, 9 Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Softwaretechnik. Lecture 03: Types and Type Soundness. Peter Thiemann. University of Freiburg, Germany SS 2008
Softwaretechnik Lecture 03: Types and Type Soundness Peter Thiemann University of Freiburg, Germany SS 2008 Peter Thiemann (Univ. Freiburg) Softwaretechnik SWT 1 / 35 Table of Contents Types and Type correctness
23-3 TCP. Topics discussed in this section: TCP Services TCP Features Segment A TCP Connection Flow Control Error Control 23.22
23-3 TCP 23.22 TCP is a connection-oriented protocol; it creates a virtual connection between two TCPs to send data. In addition, TCP uses flow and error control mechanisms at the transport level. Topics
Multi-way Search Trees. (Multi-way Search Trees) Data Structures and Programming Spring / 25
Multi-way Search Trees (Multi-way Search Trees) Data Structures and Programming Spring 2017 1 / 25 Multi-way Search Trees Each internal node of a multi-way search tree T: has at least two children contains
Part II. Hoare Logic and Program Verification. Why specify programs? Specification and Verification. Code Verification. Why verify programs?
Part II. Hoare Logic and Program Verification Part II. Hoare Logic and Program Verification Dilian Gurov Props: Models: Specs: Method: Tool: safety of data manipulation source code logic assertions Hoare
Assignment 01 Computer Architecture Lab ECSE
Assignment 01 Computer Architecture Lab ECSE 487-001 Date due: September 22, 2006, Trottier Assignment Box by 14:30 1 Introduction The purpose of this assignment is to re-familiarize the student with VHDL
Register Transfer Methodology II
Register Transfer Methodology II Chapter 12 1 Outline 1. Design example: One shot pulse generator 2. Design Example: GCD 3. Design Example: UART 4. Design Example: SRAM Interface Controller 5. Square root
Outline. Register Transfer Methodology II. 1. One shot pulse generator. Refined block diagram of FSMD
Outline Register Transfer Methodology II 1. Design example: One shot pulse generator 2. Design Example: GCD 3. Design Example: UART 4. Design Example: SRAM Interface Controller 5. Square root approximation
Program analysis parameterized by the semantics in Maude
Program analysis parameterized by the semantics in Maude A. Riesco (joint work with I. M. Asăvoae and M. Asăvoae) Universidad Complutense de Madrid, Madrid, Spain Workshop on Logic, Algebra and Category
FishTail: The Formal Generation, Verification and Management of Golden Timing Constraints
FishTail: The Formal Generation, Verification and Management of Golden Timing Constraints Chip design is not getting any easier. With increased gate counts, higher clock speeds, smaller chip sizes and
Sugar 2.0 An Introduction
Sugar 2.0 An Introduction Cindy Eisner 1 Dana Fisman 1,2 1 IBM Haifa Research Laboratory 2 Weizmann Institute of Science, Rehovot, Israel {eisner,danaf}@il.ibm.com 1 Introduction Sugar is a language for
Flexible and Executable Hardware/Software Interface Modeling For Multiprocessor SoC Design Using SystemC
Flexible and Executable / Interface Modeling For Multiprocessor SoC Design Using SystemC Patrice Gerin Hao Shen Alexandre Chureau Aimen Bouchhima Ahmed Amine Jerraya System-Level Synthesis Group TIMA Laboratory
Formal Verification. Lecture 10
Formal Verification Lecture 10 Formal Verification Formal verification relies on Descriptions of the properties or requirements of interest Descriptions of systems to be analyzed, and rely on underlying
Formal Methods in Describing Architectures
Presented at the 1995 Monterey Workshop on Formal Methods and Architecture Introduction Formal Methods in Describing Architectures Dr. Paul C. Clements Software Engineering Institute 1 Carnegie Mellon
High Level Synthesis Using Operation Properties
High Level Synthesis Using Operation Properties Jan Langer, Ulrich Heinkel Chemnitz University of Technology Chemnitz, Germany {laja,heinkel}@infotech.tu-chemnitz.de Abstract We propose a high level synthesis
10.1 REVIEW QUESTIONS
CHAPTER 10 Data Link Control 10.1 REVIEW QUESTIONS 1. Transmission means to put a signal on a line. Communication is a meaningful and orderly relationship between devices that send and receive data. 3.
Chapter 1 Overview of Digital Systems Design
Chapter 1 Overview of Digital Systems Design SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 8, 2017 Why Digital Design? Many times, microcontrollers
Design of Asynchronous Interconnect Network for SoC
Final Report for ECE 6770 Project Design of Asynchronous Interconnect Network for SoC Hosuk Han 1 han@ece.utah.edu Junbok You jyou@ece.utah.edu May 12, 2007 1 Team leader Contents 1 Introduction 1 2 Project
Propositional Calculus: Boolean Functions and Expressions. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson
Propositional Calculus: Boolean Functions and Expressions CS 270: Mathematical Foundations of Computer Science Jeremy Johnson Propositional Calculus Objective: To provide students with the concepts and
Interface: Ports. Microprocessor System Design EHB432E Lecture - 6. Interface: Bus. Timing Diagrams. Istanbul Technical University
Interface: Ports Microprocessor System Design EHB432E Lecture - 6 Prof. Dr. Müştak E. Yalçın Conducting device on periphery Single wire or set of wires with single function Connects bus to processor or
HIERARCHICAL DESIGN. RTL Hardware Design by P. Chu. Chapter 13 1
HIERARCHICAL DESIGN Chapter 13 1 Outline 1. Introduction 2. Components 3. Generics 4. Configuration 5. Other supporting constructs Chapter 13 2 1. Introduction How to deal with 1M gates or more? Hierarchical
Outline HIERARCHICAL DESIGN. 1. Introduction. Benefits of hierarchical design
Outline HIERARCHICAL DESIGN 1. Introduction 2. Components 3. Generics 4. Configuration 5. Other supporting constructs Chapter 13 1 Chapter 13 2 1. Introduction How to deal with 1M gates or more? Hierarchical
Design of Low Power Asynchronous Parallel Adder Benedicta Roseline. R 1 Kamatchi. S 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 04, 2015 ISSN (online): 2321-0613 Design of Low Power Asynchronous Parallel Adder Benedicta Roseline. R 1 Kamatchi. S 2
Assertion and Model Checking of SystemC
Assertion and Model Checking of SystemC Sofiène Tahar Hardware Verification Group Department of Electrical and Computer Engineering Concordia University Montreal, Quebec, CANADA First Annual North American
POWER consumption has become one of the most important
704 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 Brief Papers High-Throughput Asynchronous Datapath With Software-Controlled Voltage Scaling Yee William Li, Student Member, IEEE, George
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay Lecture 40 VLSI Design Verification: An Introduction Hello. Welcome to the advance
Employing Multi-FPGA Debug Techniques
Employing Multi-FPGA Debug Techniques White Paper Traditional FPGA Debugging Methods Debugging in FPGAs has been difficult since day one. Unlike simulation where designers can see any signal at any time,
CHAPTER 10 GRAPHS AND TREES. Alessandro Artale UniBZ - artale/
CHAPTER 10 GRAPHS AND TREES Alessandro Artale UniBZ - http://www.inf.unibz.it/ artale/ SECTION 10.5 Trees Copyright Cengage Learning. All rights reserved. Trees In mathematics, a tree is a connected graph
A Simple Syntax-Directed Translator
Chapter 2 A Simple Syntax-Directed Translator 1-1 Introduction The analysis phase of a compiler breaks up a source program into constituent pieces and produces an internal representation for it, called
Modeling Asynchronous Communication at Different Levels of Abstraction Using SystemC
Modeling Asynchronous Communication at Different Levels of Abstraction Using SystemC Shankar Mahadevan Inst. for Informatics and Mathematical Modeling Tech. Univ. of Denmark (DTU) Lyngby, Denmark sm@imm.dtu.dk
Speed up Emulation Debugging using Whitebox Assertions
Speed up Emulation Debugging using Whitebox Assertions Ricky Wang ricky@atrenta.com This presentation may contain forward-looking statements regarding product development. Information or statements contained
The Formalization of a Simple Hardware Description Language
The Formalization of a Simple Hardware Description Language Bishop C. Brock Warren A. Hunt, Jr. Technical Report 52 November 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703
Lecture 11 Lecture 11 Nov 5, 2014
Formal Verification/Methods Lecture 11 Lecture 11 Nov 5, 2014 Formal Verification Formal verification relies on Descriptions of the properties or requirements Descriptions of systems to be analyzed, and
A Versatile Instrument for Analyzing and Testing the Interfaces of Peripheral Devices
Reprint A Versatile Instrument for Analyzing and Testing the Interfaces of Peripheral Devices P. Savvopoulos, M. Varsamou and Th. Antonakopoulos The 3rd International Conference on Systems, Signals & Devices
CP EDI 997 Guidelines (Version 7010)
CP EDI 997 Guidelines (Version 7010) CP EDI 997 Guidelines 1 October, 2018 997 Functional Acknowledgment Introduction: Functional Group ID=FA This X12 Transaction Set contains the format and establishes
Propositional Logic. Andreas Klappenecker
Propositional Logic Andreas Klappenecker Propositions A proposition is a declarative sentence that is either true or false (but not both). Examples: College Station is the capital of the USA. There are
Lecture 15: System Modeling and Verilog
Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading
Towards A Formally Verified Network-on-Chip
Towards A Formally Verified Network-on-Chip Tom van den Broek 1 Julien Schmaltz 12 1 Institute for Computing and Information Sciences Radboud University Nijmegen The Netherlands 2 School of Computer Science
Distributed Systems Programming (F21DS1) Formal Verification
Distributed Systems Programming (F21DS1) Formal Verification Andrew Ireland Department of Computer Science School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Overview Focus on
Specifying circuit properties in PSL. (Some of this material is due to Cindy Eisner and Dana Fisman, with thanks) See also the Jasper PSL Quick Ref.
Specifying circuit properties in PSL (Some of this material is due to Cindy Eisner and Dana Fisman, with thanks) See also the Jasper PSL Quick Ref. Background: Model Checking property G(p -> F q) yes MC
Semantic Web. Ontology Engineering and Evaluation. Morteza Amini. Sharif University of Technology Fall 93-94
ه عا ی Semantic Web Ontology Engineering and Evaluation Morteza Amini Sharif University of Technology Fall 93-94 Outline Ontology Engineering Class and Class Hierarchy Ontology Evaluation 2 Outline Ontology
Principles of Program Analysis. Lecture 1 Harry Xu Spring 2013
Principles of Program Analysis Lecture 1 Harry Xu Spring 2013 An Imperfect World Software has bugs The northeast blackout of 2003, affected 10 million people in Ontario and 45 million in eight U.S. states
The design of a programming language for provably correct programs: success and failure
The design of a programming language for provably correct programs: success and failure Don Sannella Laboratory for Foundations of Computer Science School of Informatics, University of Edinburgh http://homepages.inf.ed.ac.uk/dts
DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: OUTLINE APPLICATIONS OF DIGITAL SIGNAL PROCESSING
1 DSP applications DSP platforms The synthesis problem Models of computation OUTLINE 2 DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: Time-discrete representation
Carry Checking/Parity Prediction Adders and ALUs
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 1, FEBRUARY 2003 121 Carry Checking/Parity Prediction Adders and ALUs Michael Nicolaidis Abstract In this paper, we present