Towards A Formally Verified Network-on-Chip
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1 Towards A Formally Verified Network-on-Chip Tom van den Broek 1 Julien Schmaltz 12 1 Institute for Computing and Information Sciences Radboud University Nijmegen The Netherlands 2 School of Computer Science Open University The Netherlands t.vandenbroek@cs.ru.nl & julien.schmaltz@ou.nl FMCAD 09
2 Outline Networks-on-Chips: Hermes Implemented as model instance Characteristics: XY minimal deterministic routing Wormhole switching Frame structure: Header flit (Route Information) Data flits (Payload) Torn-down flit (Last flit) TD DATA HD
3 Outline Network-on-Chips Platform-Based Design and Networks-on-Chip Platform-Based Design: Re-use of parametric modules (Intellectual Properties) High-level of abstraction Communication-centric: from buses to networks Solves the communication issues The components are connected in a communication network Advantages Scalable Parallelism
4 Outline Network-on-Chips Formal Methods and Networks-on-Chips System Verification: Proof of each component Proof of their interconnection State-of-the-Art: Model checking or theorem proving of instances of systems Often at hardware level (RTL) The GeNoC Approach: A generic model for reasoning about NoCs Reduces amount of the user interaction needed to prove properties on NoC instances
5 GeNoC approach Outline Network-on-Chips Interfaces Routing Scheduling Proof Obligations Proof Obligations Proof Obligations (0 2) (1 2) (2 2) Y () () (2 1) (0 0) (1 0) (2 0) X THEOREM messages reach their expected destination Proof Obligations Instantiated for the given NoC Proof Obligations Proof Obligations To be discharged for the given NoC
6 Contribution Outline Contribution and Method Original GeNoC Model Highly abstract representation of the communications The model has access to the complete precomputed routes the messages will traverse in the network How does the specification level relates to the implementation level? Contribution A generic implementation model A (generic) specification model A refinement proof between two instances of these models
7 Outline Method - Specification model Contribution and Method
8 Method - Contribution Outline Contribution and Method
9 Models Structure of the two models Both models consist of two main parts: The NoC characteristics are defined in the Network model Topology Router components: Datalink Routing Scheduling The Network interpreter takes a network model and simulates the network Implemented in ACL2
10 Models The main interpreter structure Model Structure State Messages Depart delayed Updated state Stepnetwork Router UpdateNeighbours
11 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state Stepnetwork Router 0 0 UpdateNeighbours
12 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state M Stepnetwork Router 0 0 UpdateNeighbours
13 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state M Stepnetwork Router 0 0 UpdateNeighbours ProcessInputs
14 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state M Stepnetwork Router 0 0 UpdateNeighbours RouteControl
15 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state Stepnetwork Router M 0 0 UpdateNeighbours FlowControl
16 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state Stepnetwork Router 0 0 M 1 0 UpdateNeighbours ProcessOutputs
17 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state Stepnetwork Router M 0 0 UpdateNeighbours
18 Models Interpreter Network interpreter Implementation Level State Messages Depart delayed Updated state Stepnetwork Router 0 0 M 1 0 UpdateNeighbours
19 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state Stepnetwork Spec-Router 0 0 UpdateNeighbours
20 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state M ENL Stepnetwork Spec-Router 0 0 UpdateNeighbours
21 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state M ENL Stepnetwork Spec-Router 0 0 UpdateNeighbours
22 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state Stepnetwork Spec-Router M ENL 0 0 UpdateNeighbours
23 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state Stepnetwork Spec-Router 0 0 M NL 1 0 UpdateNeighbours
24 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state Stepnetwork Spec-Router M NL 0 0 UpdateNeighbours
25 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state Stepnetwork Spec-Router M NL 0 0 UpdateNeighbours
26 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed Updated state M L Stepnetwork Spec-Router 0 0 UpdateNeighbours
27 Models Interpreter Network interpreter Specification Level State Messages R-Depart delayed M L Updated state Stepnetwork Spec-Router 0 0 UpdateNeighbours
28 Models Interpreter Network interpreter Specification Level State Messages M L R-Depart delayed Updated state Stepnetwork Spec-Router 0 0 UpdateNeighbours
29 Proof concept Refinement proof The implementation model is a refinement of the specification model 1 Given the same input the models should produce the same output 2 The messages should traverse the same paths in the network
30 Proof concept Refinement proof The implementation model is a refinement of the specification model 1 Given the same input the models should produce the same output 2 The messages should traverse the same paths in the network spec spec Transform impl impl The Transform relation removes the routes from the network state
31 Refinement proof Refinement theorem (1) Correct-GeNoC state, transactions : transform(genoc S (state, transactions)) = GeNoC I (state, transactions) GeNoC I and GeNoC S return a tuple of (arrived, delayed, trace) so this theorem can be read as: 1 The transformed arrived messages are equal 2 Delayed messages are equal 3 The transformed simulation trace is the same
32 Proof - Structure Refinement proof Main theorem eq-genoc eq-genoc_t Pedicates delayed arrived ntkst ntkmem accup Valid-routes stepnetwork step-outputs step-flowcontrol step-routing step-inputs Correct-routing good-ntkst routinglogic-eq-next-hop good-switch Valid-routes
33 Proof - Structure Refinement proof Main theorem eq-genoc eq-genoc_t Pedicates delayed arrived ntkst ntkmem accup Valid-routes stepnetwork step-outputs step-flowcontrol step-routing step-inputs Correct-routing good-ntkst routinglogic-eq-next-hop good-switch Valid-routes
34 Refinement proof Example theorem - Routinglogic-eq-next-hop msg : validroute(msg) = computeroute(cur(msg))(dest(msg)) = getnexthop(msg) This theorem states: A message with a valid route implies that computing the next step in the route is equal to extracting it from the precomputed route.
35 Refinement proof Proof - Statistics Group number of Theorems Changed functions 72 Predicates 140 Not changed functions 88 Total 300 The source code of the proofs and models is available on the web julien/julien at Nijmegen/FMCAD09.html
36 Conclusion - overview Conclusion
37 Conclusion Conclusion - contributions The contributions are: First cross-layer verification attempt of a NoC A realistic generic implementation model Multiple implementation instances of real NoCs Packet, circuit, and wormhole switching XY and Spidergon routing Hermes NoC Octagon NoC Instance of a NoC at the specification level Refinement proof between two instances
38 Conclusion Conclusion - Future work Current and future research directions: A generic cross-layer verification method Proof between two generic models at two different levels More instances of different NoCs Integration of deadlock and liveness properties (Verbeek & Schmaltz ACL2 09 and DATE 10) Extending the number of layers Towards RTL Layer with Source and Distributed scheduling
39 Conclusion Thank you for listening!
40 Appendix Network Model Generic Router Port Address Id Port Name Direction N E S W L Data Data Input Input Stage Rx ackrx StatusField Buffer Routing Control Port Flow Control Data Address Id Data Output Port Name Direction Output Stage N E S W L Tx acktx StatusField Buffer
41 Appendix Wormhole switching and XY Routing 0 0
42 Appendix Wormhole switching and XY Routing H booked 0 0
43 Appendix Wormhole switching and XY Routing D booked H 0 0 booked 1 0
44 Appendix Wormhole switching and XY Routing D booked D H 0 0 booked booked 1 0
45 Appendix Wormhole switching and XY Routing T H booked booked D D 0 0 booked booked 1 0
46 Appendix Wormhole switching and XY Routing H booked D T booked D 0 0 booked booked 1 0
47 Appendix Wormhole switching and XY Routing H booked D booked D booked T 0 0 booked 1 0
48 Appendix Wormhole switching and XY Routing D booked D booked T booked 0 0
49 Appendix Wormhole switching and XY Routing D booked T booked 0 0
50 Appendix Wormhole switching and XY Routing T booked 0 0
51 Appendix Wormhole switching and XY Routing 0 0
52 Appendix Circuit Switching 0 0
53 Appendix Circuit Switching m req 0 0 req 1 0
54 Appendix Circuit Switching m req 0 0 req req 1 0
55 Appendix Circuit Switching m req req 0 0 req req 1 0
56 Appendix Circuit Switching req m req req 0 0 req req 1 0
57 Appendix Circuit Switching booked ack req m req req 0 0 req req 1 0
58 Appendix Circuit Switching booked ack booked m req req 0 0 req req 1 0
59 Appendix Circuit Switching booked ack booked m req booked 0 0 req req 1 0
60 Appendix Circuit Switching booked ack booked m req booked 0 0 req booked1 0
61 Appendix Circuit Switching booked ack booked m req booked 0 0booked booked1 0
62 Appendix Circuit Switching booked ack booked m booked booked 0 0booked booked1 0
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