LogiCORE IP Ten-Gigabit Ethernet PCS/PMA v2.2

Transcription

1 LogiCORE P Ten-Gigabit Ethernet PCS/PMA v2.2 User Guide

2 Notice of isclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS S" and with all faults, Xilinx hereby SCLAMS ALL WARRANTES AN CONTONS, EXPRESS, MPLE, OR STATUTORY, NCLUNG BUT NOT LMTE TO WARRANTES OF MERCHANTABLTY, NON-NFRNGEMENT, OR FTNESS FOR ANY PARTCULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at P cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: Copyright Xilinx, nc. Xilinx, the Xilinx logo, Artix, SE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PC, PC Express, PCe, and PC-X are trademarks of PC-SG. All other trademarks are the property of their respective owners. Revision History The table shows the revision history for this document. ate Version Revision 12/02/ nitial Xilinx release 4/19/ Updated to core version 1.2; updated Xilinx tools to /01/ Updated to core version 2.1; updated Xilinx tools to Added Virtex -7 and Kintex -7 FPGAs support. 10/19/ Updated to core version 2.2 updated Xilinx tools to n Table 3-2 and Table 6-3, changed transmit and receive data widths to 32 bits for Virtex-7 and Kintex-7 devices, and redefined gt_rxc[3]. n Table 3-7, removed rxreset and rxclk156, and renamed rxreset322 and txreset322. n Chapter 10, etailed Example esign, removed simulation/timing section. LogiCORE P Ten-Gigabit Ethernet PCS/PMA

3 Table of Contents Chapter 1: ntroduction Supported Tools and System Requirements About the Core Recommended esign Experience Additional Core Resources Technical Support Feedback List of Acronyms Chapter 2: Licensing the Core Chapter 3: Core Architecture System Overview Functional escription Core nterfaces and Modules Miscellaneous Signals - Virtex-7/Kintex-7 FPGAs Chapter 4: Customizing and Generating the Core GU nterface Parameter Values in the XCO File Output Generation Chapter 5: esigning with the Core General esign Guidelines Chapter 6: nterfacing to the Core ata nterface: nternal nterfaces nterfacing to the Transmit Client nterface nterfacing to the Receive Client nterface nterfacing to the Transceivers Configuration and Status nterfaces MO nterface Configuration and Status Vectors Chapter 7: Constraining the Core evice, Package, and Speed Grade Selection Clock Frequencies, Clock Management, and Placement Other Constraints LogiCORE P Ten-Gigabit Ethernet PCS/PMA 3

4 Transceiver Placement MO Chapter 8: esign Considerations Virtex-7/Kintex-7 FPGAs Virtex-6 FPGAs Connecting Multiple Core nstances in Virtex-6 HXT FPGAs Using the RP in Virtex-6 HXT FPGAs Reset Circuits Receiver Termination: Virtex-7/Kintex-7 FPGAs Receiver Termination: Virtex-6 FPGAs Chapter 9: mplementing the Core Pre-implementation Simulation Synthesis mplementation Post-mplementation Simulation Other mplementation nformation Chapter 10: etailed Example esign irectory and File Contents mplementation and Test Scripts GBASE-R Core Chapter 11: Quick Start Example esign ntroduction Generating the Core mplementing the 10GBASE-R Example esign Simulating the 10GBASE-R Example esign Additional nformation Appendix A: Additional Resources Xilinx Resources Solution Centers Appendix B: Verification and nteroperability Appendix C: Core Latency Virtex-7/Kintex-7 FPGAs Virtex-6 HXT FPGAs LogiCORE P Ten-Gigabit Ethernet PCS/PMA

5 Chapter 1 ntroduction The Ten Gigabit Ethernet PCS/PMA v2.2 User Guide provides information about generating a LogiCORE P Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core, utilizing the provided example design, and running the design files through implementation using the Xilinx tools. The 10GBASE-R LogiCORE P core has been verified in S 13.3 software with the pre-production Virtex -6 HXT FPGA and Virtex-7/Kintex -7 FPGA speed files. Pre-production means that the speed files are still subject to change. The 10GBASE-R LogiCORE P core and example design are provided in Verilog and VHL. This chapter introduces the 10GBASE-R core and provides related information, including recommended design experience, additional resources, technical support, and submitting feedback to Xilinx. Supported Tools and System Requirements Operating System Requirements For a list of system requirements, see the SE esign Suite 13: Release Notes Guide. Tools For the supported versions of these tools, see the SE esign Suite 13: Release Notes Guide. SE v13.3 software About the Core The 10GBASE-R core is a Xilinx CORE Generator software P core, included in the latest SE Update on the Xilinx P Center. For detailed information about the core, see the 10GBASE-R product page. For information about licensing options, see Chapter 2, Licensing the Core. Recommended esign Experience Although the 10GBASE-R core is a fully verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high performance, pipelined FPGA designs using Xilinx implementation software and UCF is recommended. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 5

6 Chapter 1: ntroduction Additional Core Resources ocumentation Contact your local Xilinx representative for a closer review and estimation for your specific requirements. For detailed information about 10GBASE-R technology and updates to the 10GBASE-R core, see the following: From the 10GBASE-R product page: 10GBASE-R Release Notes 10GBASE-R ata Sheet From the document directory after generating the core: 10GBASE-R Release Notes 10GBASE-R ata Sheet 10GBASE-R Technology For information about 10GBASE-R technology basics, including features, FAQs, the 10GBASE-R chip interface, typical applications, specifications, and other important information, see Ethernet Specifications Other nformation Technical Support The relevant 10GBASE-R standards are EEE Std The 10-Gigabit Ethernet Consortium at the University of New Hampshire nteroperability Lab is an excellent source of information on 10-Gigabit Ethernet technology: For technical support, visit Questions are routed to a team of engineers with expertise using the 10GBASE-R core. Xilinx provides technical support for use of this product as described in the LogiCORE P 10GBASE-R User Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines. 6 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

7 Feedback Feedback Xilinx welcomes comments and suggestions about the 10GBASE-R core and the documentation supplied with the core. Core For comments or suggestions about the 10GBASE-R core, submit a webcase from Be sure to include the following information: Product name Core version number Explanation of your comments ocument List of Acronyms For comments or suggestions about this document, submit a webcase from Be sure to include the following information: ocument title ocument number Page number(s) to which your comments refer Explanation of your comments This table describes acronyms used in this manual. Acronym CLB CML R RP FPGA Gb/s GU HL ES O OB P SE MAC Mb/s Spelled Out Configurable Logic Block Current Mode Logic ouble ata Rate ynamic Reconfiguration Port Field Programmable Gate Array. Gigabits per second Graphical User nterface Hardware escription Language ncisive Enterprise Simulator nput/output nput/output Block ntellectual Property ntegrated Software Environment Media Access Controller Megabits per second LogiCORE P Ten-Gigabit Ethernet PCS/PMA 7

8 Chapter 1: ntroduction Acronym MM MO MGMT MHz MMCM ms NC NG ns PAR PCS PHY PLL PMA PM ps SR STA TWR UCF VCS VHL XAU XCO XGM XST Spelled Out MO Managed evice Management ata nput/output Management Mega Hertz Mixed-Mode Clock Manager milliseconds Native Circuit escription Native Generic atabase nanoseconds Place and Route Physical Coding Sublayer physical-side interface Phase-Locked Loop Physical Medium Attachment Physical Medium ependent picoseconds Single ata Rate Station Management Entity Timing Wizard Report User Constraints File Verilog Compiled Simulator (Synopsys) VHSC Hardware escription Language (VHSC an acronym for Very High-Speed ntegrated Circuits). extended Attachment Unit nterface Xilinx CORE Generator core source file 10-Gigabit Media ndependent nterface Xilinx Synthesis Technology 8 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

9 Chapter 2 Licensing the Core This core is provided under the End User License Agreement and can be generated using the Xilinx CORE Generator system v13.3 or higher. The CORE Generator system is shipped with Xilinx SE esign Suite Series evelopment software. n SE v13.3 software and later, a license key is not required to access the 10GBASE-R P. To access the wrapper in SE v12.4 software and older, a no-cost full license must be obtained from Xilinx. See the version of the user guide for the version of the core you are using for information. Contact your local Xilinx sales representative for pricing and availability of other Xilinx LogiCORE P modules and software. nformation on additional LogiCORE P modules is available at the Xilinx P Center. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 9

10 Chapter 2: Licensing the Core 10 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

11 Chapter 3 Core Architecture System Overview Functional escription This chapter describes the overall architecture of the 10GBASE-R core and also describes the major interfaces to the core. 10GBASE-R is a 10 Gb/s serial interface. t provides the PCS and PMA functionality between the XGM interface on a 10-Gigabit Ethernet MAC and a 10-Gigabit Ethernet network PHY. Figure 3-1 shows a block diagram of the implementation of the Virtex -7/Kintex -7 FPGA 10GBASE-R core. The major functional blocks of the core include the following: Virtex-7/Kintex-7 FPGA GTX Transceiver. Provides high-speed transceiver and partial gearbox functionality. PCS Block. Provides encode/decode, scramble/descramble, block-lock, transmit and receive state machines, test-pattern blocks, and BER monitor in the same configuration as in Figure 3-2. Optional MO nterface. A two-wire low-speed serial interface used to manage the core. An alternative vector-based interface might be provided instead. Elastic Buffer. dentical to that described in the next section. See page 12. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 11

12 Chapter 3: Core Architecture X-Ref Target - Figure 3-1 Fabric GTXE2 Elastic Buffer rxn,p User Logic P C S SERES txn,p XGM (SR) MO Control + Status Management Arbiter PCS/PMA Registers Figure 3-1: Virtex-7/Kintex-7 FPGA mplementation of the 10-Gigabit Ethernet PCS/PMA (BASE-R) Core Figure 3-2 shows a block diagram of the implementation of the Virtex-6 FPGA 10GBASE-R core. The major functional blocks of the core include the following: Virtex-6 FPGA GTH transceiver. Provides high-speed transceiver as well as 64B/66B encode and decode, Block Lock, TX and RX state machines and BER monitor. Management interface. Provides a simple interface to the management registers in the transceiver. Optional MO interface. A two-wire low-speed serial interface used to manage the core. An alternative vector-based interface might be provided instead. Elastic Buffer in the receive datapath. The Elastic Buffer is 32 words deep (1 word = 32 bits data + 4 control). f the buffer empties, Local Fault codes are inserted instead of data. This allows you to collect up to 32 clock correction (CC) sequences before the buffer overflows (and words are dropped). The buffer normally fills up to one quarter and only drop CC sequences when over half full, and only insert CC sequences when under one quarter full. So from a half-full state, you can (conservatively) accept an extra 14, 32-bit sequences (that is, receiving at +200 ppm) without dropping any and from a quarter-full state you can cope with half that number of missing bits without inserting Local faults (for -200 ppm) LogiCORE P Ten-Gigabit Ethernet PCS/PMA

13 Functional escription X-Ref Target - Figure 3-2 Fabric GTH Transceiver Elastic Buffer 64B/66B ecode escramble Block Sync rxn,p User Logic Test Pattern Check BER Monitor SERES 64B/66B Encode Test Pattern Generate Scramble Gearbox txn,p XGM (SR) MO Control + Status Management Arbiter PCS/PMA Registers Figure 3-2: Virtex-6 FPGA mplementation of the 10-Gigabit Ethernet PCS/PMA (BASE-R) Core Applications Figure 3-3 shows a typical Ethernet system architecture and the 10-Gigabit Ethernet PCS/PMA core within it. The MAC and all the blocks to the right are defined in Ethernet EEE specifications. X-Ref Target - Figure 3-3 TCP P FFO /F MAC PCS PMA PM Figure 3-3: Typical Ethernet System Architecture Figure 3-4 shows the 10-Gigabit Ethernet PCS/PMA core connected on one side to a 10-Gigabit MAC and on the other to an optical module using a serial interface. The 10-Gigabit Ethernet PCS/PMA core is designed to be easily attached to the Xilinx P 10-Gigabit Ethernet MAC core over XGM. More details are provided in Chapter 8, esign Considerations. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 13

14 Chapter 3: Core Architecture X-Ref Target - Figure 3-4 FPGA User Logic (Ten Gigabit Ethernet MAC) XGM 10G PCS/PMA Core Serial nterface Core nterfaces and Modules Client-Side nterface Figure 3-4: 10-Gigabit Ethernet PCS/PMA Core Connected to MAC Core Using XGM nterface The signals of the client-side interface are shown in Table 3-1. See Chapter 6, nterfacing to the Core for details on connecting to the client-side interface. Table 3-1: Client-Side nterface Ports Signal Name irection escription xgmii_txd[63:0] n Transmit data, eight bytes wide xgmii_txc[7:0] n Transmit control bits, one bit per transmit data byte xgmii_rxd[63:0] Out Received data, eight bytes wide xgmii_rxc[7:0] Out Receive control bits, one bit per received data byte 14 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

15 Core nterfaces and Modules Transceiver ata nterface - Virtex-7/Kintex-7 FPGA GTX Transceiver The interface to the device-specific transceivers is not a simple one-to-one interface on those pins that need to be connected. The signals are described in Table 3-2. See Chapter 6, nterfacing to the Core for details on connecting the device-specific transceivers to the 10GBASE-R core. Note that gt_txc[7:2] on the core should be connected to txsequence[5:0] on the GTX transceiver and that gt_rxc[2] on the core should be connected to rxdatavalid on the GTX transceiver. Table 3-2: Transceiver nterface Ports - Virtex-7/Kintex-7 FPGA GTX Transceiver Signal Name irection escription gt_txd[31:0] Out 32-bit transmit data word gt_txc[1:0] Out 2-bit transmit sync header gt_txc[7:2] Out 6-bit TXSEQUENCE count (0..32) gt_rxd[31:0] n 32-bit receive data word gt_rxc[1:0] n 2-bit receive sync header gt_rxc[2] n RXATAVAL (High for 64 in 66 rxusrclk2 cycles) gt_rxc[3] n RXHEAERVAL (High for 32 in 66 rxusrclk2 cycles) gt_rxc[7:4] n Not Used gt_slip Out RXGEARBOXSLP Transceiver ata nterface - Virtex-6 FPGA GTH Transceiver The interface to the device-specific transceivers is a simple pin-to-pin interface on those pins that need to be connected. The signals are described in Table 3-3. See Chapter 6, nterfacing to the Core for details on connecting the device-specific transceivers to the 10GBASE-R core. Table 3-3: Transceiver nterface Ports - Virtex-6 FPGA GTH Transceiver Signal Name irection escription gt_txd[63:0] Out Transceiver transmit data gt_txc[7:0] Out Transceiver transmit control flag gt_rxd[63:0] n Transceiver receive data gt_rxc[7:0] n Transceiver receive control signals LogiCORE P Ten-Gigabit Ethernet PCS/PMA 15

16 Chapter 3: Core Architecture Optical Module nterface The status and control interface to an attached optical module is a simple pin-to-pin interface on those pins that need to be connected. The signals are described in Table 3-3. See Chapter 6, nterfacing to the Core for details on connecting an optical module to the 10GBASE-R core. Table 3-4: Optical Module nterface Ports Signal Name irection escription signal_detect n Status signal from attached optical module a tx_fault n Status signal from attached optical module ab tx_disable Out Control signal to attached optical module a. These signals are not connected inside this version of the core. t is left to users to handle these inputs and reset their design as they see fit. b. Connect to SFP+ tx_fault signal, or XFP MO_NR signal, depending on which is present. MO nterface The MO nterface signals are shown in Table 3-5. More information on using this interface can be found in Chapter 6, nterfacing to the Core. Table 3-5: MO Management nterface Ports Signal Name irection escription mdc n Management clock mdio_in n MO input mdio_out Out MO output mdio_tri Out MO 3-state; 1 disconnects the output driver from the MO bus. prtad[4:0] n MO port address; this should be set by you to provide a unique on the MO bus. Configuration and Status Signals The Configuration and Status Signals are shown in Table 3-6. See Configuration and Status Vectors, page 61 for details on these signals, including a breakdown of the configuration and status vectors. Table 3-6: Configuration and Status Ports Signal Name irection escription configuration_ vector[535:0] n Configuration information for the core. status_vector[447:0] Out Status information from the core LogiCORE P Ten-Gigabit Ethernet PCS/PMA

17 Core nterfaces and Modules Clocking and Reset Signals - Virtex-7/Kintex-7 FPGAs ncluded in the example design top-level sources are circuits for clock and reset management. These can include clock generators, reset synchronizers, or other useful utility circuits that can be useful in your particular application. Table 3-7 shows the ports on the netlist that are associated with system clocks and resets. Table 3-7: Clock and Reset Ports- Virtex-7/Kintex-7 FPGAs Signal Name irection escription clk156 n System clock for core rxusrclk2 n Receive path clock, derived from recovered clock on the GTX transceiver txusrclk2 n Transmit path clock, derived from TXCLKOUT on the GTX transceiver dclk n Management/RP clock, at half the rate of clk156 reset n Synchronous reset in clk156 domain rxreset322 n Synchronous reset in rxusrclk2 domain txreset322 n Synchronous reset in txusrclk2 domain dclk_reset n Synchronous reset in dclk domain Clocking and Reset Signals - Virtex-6 FPGAs ncluded in the example design top-level sources are circuits for clock and reset management. These can include clock generators, reset synchronizers, or other useful utility circuits that can be useful in your particular application. Table 3-8 shows the ports on the netlist that are associated with system clocks and resets. Table 3-8: Clock and Reset Ports - Virtex-6 FPGAs Signal Name irection escription clk156 n System clock for core. rxclk156 n Receiver clock to transceiver side of elastic buffer. dclk n Management clock used to access transceiver registers. reset n Reset port synchronous to clk156. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 17

18 Chapter 3: Core Architecture Transceiver Management nterface As shown in the example design block-level sources, the core communicates with the transceiver via a fixed management interface. Table 3-9 shows the ports on the netlist that are associated with the transceiver management interface. Table 3-9: Transceiver Management nterface Ports - Virtex-6 FPGAs Signal Name irection escription mgmt_req Out Request access to management interface arbiter mgmt_gnt n Access granted to management interface arbiter mgmt_rd_out Out Read pulse to management interface mgmt_wr_out Out Write pulse to management interface mgmt_addr_out [20:0] Out Address for management interface, with the 5-bit EVA (evice Address) at bits mgmt_rdack_in n Read Acknowledge/ata Valid signal from the transceiver management interface mgmt_rddata_in [15:0] n Read data from management interface mgmt_wrdata_out [15:0] Out Write data to management interface Miscellaneous Signals - Virtex-7/Kintex-7 FPGAs Table 3-10: Miscellaneous Signals Signal Name irection escription core_status[7:0] Out Bit 0 = PCS Block Lock, Bits [7:1] are reserved 18 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

19 Chapter 4 Customizing and Generating the Core The 10GBASE-R core is generated using the Xilinx CORE Generator system. This chapter describes how to customize the 10GBASE-R core to your requirements and then generate the core netlist. GU nterface Figure 4-1 displays the main screen for customizing the 10GBASE-R core. X-Ref Target - Figure 4-1 Component Name Figure 4-1: 10GBASE-R Main Screen For general help with starting and using the CORE Generator software on your development system, see the documentation supplied with the SE software. The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and _ (underscore). LogiCORE P Ten-Gigabit Ethernet PCS/PMA 19

20 Chapter 4: Customizing and Generating the Core MO Management Select this option to implement the MO interface for managing the core. eselect the option to remove the MO interface and expose a simple bit vector to manage the core. The default is to implement the MO interface. Parameter Values in the XCO File XCO files contain parameterization information for an instance of a core; an XCO file is created when a core is generated and can be used to recreate a core. The text in an XCO file is case-insensitive. Table 4-1 shows the XCO file parameters and values, and summarizes the GU defaults. The following is an example extract from an XCO file: SELECT Ten_Gigabit_Ethernet_PCS/PMA_(10GBASE-R/KR) family Xilinx,_nc. 2.2 CSET component_name = the_core CSET mdio_management = true GENERATE Table 4-1: XCO File Values and efaults Parameter XCO File Values efaults component_name ASC text starting with a letter and based upon the following character set: a...z, and _ ten_gig_eth_pcs_pma_v2_2 mdio_management True, false True Output Generation The output files generated from the CORE Generator software are placed in the project directory. The list of output files includes: The netlist files for the core XCO files Release notes and documentation An HL example design Scripts to synthesize, implement and simulate the example design. See Chapter 10, etailed Example esign, for a complete description of the CORE Generator software output files and for details of the HL example design LogiCORE P Ten-Gigabit Ethernet PCS/PMA

21 Chapter 5 esigning with the Core General esign Guidelines This chapter provides a general description of how to use the 10GBASE-R core in your designs and should be used in conjunction with Chapter 6, nterfacing to the Core, which describes specific core interfaces. This section describes the steps required to turn a 10GBASE-R core into a fully-functioning design with user-application logic. t is important to realize that not all implementations require all of the design steps listed in this chapter. Follow the logic design guidelines in this manual carefully. Use the Example esign as a Starting Point Each instance of the 10GBASE-R core created by the CORE Generator software is delivered with an example design that can be implemented in an FPGA and simulated. This design can be used as a starting point for your own design or can be used to sanitycheck your application in the event of difficulty. See the Chapter 10, etailed Example esign, for information about using and customizing the example designs for the 10GBASE-R core. Know the egree of ifficulty Keep t Registered 10GBASE-R designs are challenging to implement in any technology, and the degree of difficulty is further influenced by: Maximum system clock frequency Targeted device architecture Nature of your application All 10GBASE-R implementations need careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance. To simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered between your application and the core. This means that all inputs and outputs from your application should come from, or connect to a flip-flop. While registering signals cannot be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place and route the design. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 21

22 Chapter 5: esigning with the Core Recognize Timing Critical Signals The UCF provided with the example design for the core identifies the critical signals and the timing constraints that should be applied. See Chapter 7, Constraining the Core for further information. Use Supported esign Flows The core is synthesized in the CORE Generator software and is delivered to you as an NGC netlist. The example implementation scripts provided currently use XST as the synthesis tool for the HL example design that is delivered with the core. Other synthesis tools can be used for your application logic; the core is always unknown to the synthesis tool and appears as a black box. Post synthesis, only Xilinx SE v13.3 software tools are supported. Make Only Allowed Modifications The 10GBASE-R core is not user-modifiable. o not make modifications as they can have adverse effects on system timing and protocol compliance. Supported user configurations of the 10GBASE-R core can only be made by selecting the options from within the CORE Generator software when the core is generated. See Chapter 4, Customizing and Generating the Core LogiCORE P Ten-Gigabit Ethernet PCS/PMA

23 Chapter 6 nterfacing to the Core This chapter describes how to connect to the data interfaces of the core and configuration and status interfaces of the 10GBASE-R core. ata nterface: nternal nterfaces nternal 64-bit SR Client-side nterface The 64-bit single-data rate (SR) client-side interface is based upon the 32-bit XGM interface. The bus is demultiplexed from 32 bits wide to 64 bits wide on a single rising clock edge. This demultiplexing is done by extending the bus upwards so that there are now eight lanes of data numbered 0-7; the lanes are organized such that data appearing on lanes 4 7 is transmitted or received later in time than that in lanes 0-3. The mapping of lanes to data bits is shown in Table 6-1. The lane number is also the index of the control bit for that particular lane; for example, xgmii_txc[2] and xgmii_txd[23:16] are the control and data bits respectively for lane 2. Table 6-1: XGM_TX, XGM_RX Lanes for nternal 64-bit Client-Side nterface Lane XGM_TX, XGM_RX Bits 0 7:0 1 15:8 2 23: : : : : :56 LogiCORE P Ten-Gigabit Ethernet PCS/PMA 23

24 Chapter 6: nterfacing to the Core efinitions of Control Characters Reference is regularly made to certain XGM control characters signifying Start, Terminate, Error, etc. These control characters all have in common that the control line for that lane is 1 for the character and a certain data byte value. The relevant characters are defined in the EEE Std and are reproduced in Table 6-2 for reference. Table 6-2: Partial List of XGM Characters ata (Hex) Control Name, Abbreviation 00 to FF 0 ata () 07 1 dle () FB 1 Start (S) F 1 Terminate (T) FE 1 Error (E) 24 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

25 nterfacing to the Transmit Client nterface nterfacing to the Transmit Client nterface nternal 64-bit Client-Side nterface The timing of a data frame transmission via the internal 64-bit client-side interface is shown in Figure 6-1. The beginning of the data frame is shown by the presence of the Start character (the /S/ codegroup in lane 4 of Figure 6-1) followed by data characters in lanes 5, 6, and 7. Alternatively the start of the data frame can be marked by the occurrence of a Start character in lane 0, with the data characters in lanes 1 to 7. When the frame is complete, it is completed by a Terminate character (the T in lane 1 of Figure 6-1). The Terminate character can occur in any lane; the remaining lanes are padded by XGM idle characters. X-Ref Target - Figure 6-1 clk156 xgmii_txd[7:0] xgmii_txd[15:8] T xgmii_txd[23:16] xgmii_txd[31:24] xgmii_txd[39:32] S xgmii_txd[47:40] xgmii_txd[55:48] xgmii_txd[63:56] xgmii_txc[7:0] FF 1F FE FF Figure 6-1: Normal Frame Transmission Across the nternal 64-bit Client-Side /F LogiCORE P Ten-Gigabit Ethernet PCS/PMA 25

26 Chapter 6: nterfacing to the Core Figure 6-2 depicts a similar frame to that in Figure 6-1, with the exception that this frame is propagating an error. The error code is denoted by the letter E, with the relevant control bits set. X-Ref Target - Figure 6-2 clk156 xgmii_txd[7:0] E xgmii_txd[15:8] E xgmii_txd[23:16] E xgmii_txd[31:24] E xgmii_txd[39:32] S xgmii_txd[47:40] T xgmii_txd[55:48] xgmii_txd[63:56] xgmii_txd[7:0] FF 1F 00 0F E0 FF Figure 6-2: Frame Transmission with Error Across nternal 64-bit Client-Side /F 26 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

27 nterfacing to the Receive Client nterface nterfacing to the Receive Client nterface nternal 64-bit Client-Side nterface The timing of a normal inbound frame transfer is shown in Figure 6-3. As in the transmit case, the frame is delimited by a Start character (S) and by a Terminate character (T). The Start character in this implementation can occur in either lane 0 or in lane 4. The Terminate character, T, can occur in any lane. X-Ref Target - Figure 6-3 clk156 xgmii_rxd[7:0] S xgmii_rxd[15:8] xgmii_rxd[23:16] xgmii_rxd[31:24] xgmii_rxd[39:32] xgmii_rxd[47:40] T xgmii_rxd[55:48] xgmii_rxd[63:56] xgmii_rxc[7:0] FF E0 FF Figure 6-3: Frame Reception Across the nternal 64-bit Client nterface LogiCORE P Ten-Gigabit Ethernet PCS/PMA 27

28 Chapter 6: nterfacing to the Core Figure 6-4 shows an inbound frame of data propagating an error. n this instance, the error is propagated in lanes 4 to 7, shown by the letter E. X-Ref Target - Figure 6-4 clk156 xgmii_rxd[7:0] S xgmii_rxd[15:8] xgmii_rxd[23:16] xgmii_rxd[31:24] T xgmii_rxd[39:32] E xgmii_rxd[47:40] E xgmii_rxd[55:48] E xgmii_rxd[63:56] E xgmii_rxc[7:0] FF F0 00 F8 FF Figure 6-4: Frame Reception with Error Across the nternal 64-bit Client nterface 28 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

29 nterfacing to the Transceivers nterfacing to the Transceivers Virtex-7/Kintex-7 FPGAs Table 6-3: Transceiver nterface Ports for Virtex-7/Kintex-7 FPGA GTX Transceivers The remainder of the device-specific transceiver ports are not connected to the netlist, but are connected in the core source code (block-level and transceiver wrapper files) or are wired to static values. No timing diagrams are presented here for the device-specific transceiver signals. You should treat this interface as a black box. f customization of this interface is required, see the 7 Series FPGAs GTX Transceivers User Guide (UG476) for detailed descriptions of the transceiver ports. Virtex-6 HXT FPGAs Signal Name irection escription gt_txd[31:0] Out 32-bit transmit data word gt_txc[1:0] Out 2-bit transmit sync header gt_txc[7:2] Out 6-bit TXSEQUENCE count (0..32) gt_rxd[31:0] n 32-bit receive data word gt_rxc[1:0] n 2-bit receive sync header gt_rxc[2] n RXATAVAL (High for 64 in 66 rxusrclk2 cycles) gt_rxc[3] n RXHEAERVAL (High for 32 in 66 rxusrclk2 cycles) gt_rxc[7:4] n Not used gt_slip n RXGEARBOXSLP on GTX transceiver Table 6-4: Transceiver nterface Ports for Virtex-6 FPGA GTH Transceivers Signal Name irection escription gt_txd[63:0] Out Transceiver transmit data gt_txc[7:0] Out Transceiver transmit control signals gt_rxd[63:0] n Transceiver receive data gt_rxc[7:0] n Transceiver receive control signals The remainder of the device-specific transceiver ports are not connected to the netlist, but are connected in the core source code (block-level and transceiver wrapper files) or are wired to static values. No timing diagrams are presented here for the device-specific transceiver signals. You should treat this interface as a black box. f customization of this interface is required, see the Virtex-6 FPGA GTH Transceivers User Guide for detailed descriptions of the transceiver ports. The following sections describe the interfaces available for dynamically setting the configuration and obtaining the status of the 10GBASE-R core. There are two interfaces for configuration; depending on the core customization, only one is available in a particular core instance. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 29

30 Chapter 6: nterfacing to the Core Configuration and Status nterfaces MO nterface This section describes the interfaces available for dynamically setting the configuration and obtaining the status of the 10GBASE-R core. There are two interfaces for configuration; depending on the core customization, only one is available in a particular core instance. The interfaces are: MO nterface, page 30 Configuration and Status Vectors, page 61 The Management ata nput/output (MO) interface is a simple, low-speed 2-wire interface for management of the 10GBASE-R core consisting of a clock signal and a bidirectional data signal. t is defined in clause 45 of EEE Standard An MO bus in a system consists of a single Station Management (STA) master management entity and a number of MO Managed evice (MM) slave entities. Figure 6-5 illustrates a typical system. All transactions are initiated by the STA entity. The 10GBASE-R core implements an MM. X-Ref Target - Figure 6-5 MAC 1 MAC 2 STA mdio mdc MM MM MM MM MM MM Figure 6-5: A Typical MO-Managed System 30 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

31 MO nterface MO Ports The core ports associated with MO are shown in Table 6-5. f implemented, the MO interface is implemented as four unidirectional signals. These can be used to drive a 3-state buffer either in the FPGA SelectO interface buffer or in a separate device. The prtad[4:0] port sets the port address of the core instance. Multiple instances of the same core can be supported on the same MO bus by setting the prtad[4:0] to a unique value for each instance; the 10GBASE-R core ignores transactions with the PRTA field set to a value other than that on its prtad[4:0] port. MO Transactions EVA Table 6-5: MO Management nterface Port escription Signal Name irection escription mdc n Management clock mdio_in n MO input mdio_out Out MO output mdio_tri Out MO 3-state. 1 disconnects the output driver from the MO bus. prtad[4:0] n MO port address The MO interface should be driven from a STA master according to the protocol defined in EEE Std An outline of each transaction type is described in the following sections. n these sections, these abbreviations apply: PRE: preamble ST: start OP: operation code PRTA: port address EVA: device address TA: turnaround The device address in this case will be either for the PMA device or for the PCS device, both of which are implemented in the GTH Transceiver. MO transactions with a EVA other than those two values are ignored. Set Address Transaction Figure 6-6 shows an Address transaction defined by OP= 00. Set Address is used to set the internal 16-bit address register which is particular to the given EVA, for subsequent data transactions (called the current address in the following sections). The core contains two such address registers, one for PCS and one for PMA. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 31

32 Chapter 6: nterfacing to the Core X-Ref Target - Figure 6-6 STA drives MO mdc mdio Z Z LE P4 P3 P2 P1 P0 V4 V3 V2 V1 V Z bits PRE ST OP PRTA EVA TA 16-bit ARESS Z LE Write Transaction Figure 6-6: MO Set Address Transaction Figure 6-7 shows a Write transaction defined by OP= 01. The 10GBASE-R core takes the 16-bit word in the data field and writes it to the register at the current address. X-Ref Target - Figure 6-7 STA drives MO mdc mdio Z Z LE P4 P3 P2 P1 P0 V4 V3 V2 V1 V Z bits PRE ST OP PRTA EVA TA 16-bit WRTE ATA Z LE Read Transaction Figure 6-7: MO Write Transaction Figure 6-8 shows a Read transaction defined by OP= 11. The 10GBASE-R core returns the 16-bit word from the register at the current address. X-Ref Target - Figure 6-8 STA drives MO MM drives MO mdc mdio Z Z LE P4P3 P2 P1 P0 V4 V3 V2 V1 V0 Z Z bits PRE ST OP PRTA EVA TA 16-bit REA ATA Z LE Figure 6-8: MO Read Transaction 32 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

33 MO nterface Post-Read-increment-address Transaction Figure 6-9 shows a Post-read-increment-address transaction, defined by OP= 10. The 10GBASE-R core returns the 16-bit word from the register at the current address for the given EVA then increments that current address. This allows sequential reading or writing by a STA master of a block of contiguous register addresses. X-Ref Target - Figure 6-9 STA drives MO MM drives MO mdc mdio Z Z LE P4 P3 P2 P1 P0 V4 V3 V2 V1 V0 Z Z bits PRE ST OP PRTA EVA TA 16-bit REA ATA Z LE Figure 6-9: MO Read-and-increment Transaction LogiCORE P Ten-Gigabit Ethernet PCS/PMA 33

34 Chapter 6: nterfacing to the Core 10GBASE-R PCS/PMA Register Map Because the core is configured as a 10GBASE-R PCS/PMA, it occupies MO evice Addresses 1 and 3 in the MO register address map, as shown in Table 6-6. Table 6-6: 10GBASE-R PCS/PMA MO Registers Register Address 1.0 PMA/PM Control PMA/PM Status PMA/PM Speed Ability 1.5, 1.6 PMA/PM evices in Package G PMA/PM Control G PMA/PM Status G PM Transmit isable G PM Receive Signal OK 1.11 to Reserved Register Name PMA Vendor Specific Loopback (Virtex-6 FPGAs only) to Reserved Core Version nfo (Virtex-7/Kintex-7 FPGAs only) 3.0 PCS Control PCS Status PCS Speed Ability (Virtex-7/Kintex-7 FPGAs only) 3.5, 3.6 PCS evices in Package G PCS Control G PCS Status to 3.31 Reserved GBASE-R PCS Status GBASE-R PCS Status GBASE-R Test Pattern Seed A GBASE-R Test Pattern Seed B GBASE-R Test Pattern Control GBASE-R Test Pattern Error Counter 3.44 to Reserved PCS Vendor Specific Loopback (Virtex-6 FPGAs only) to Reserved PCS 125 μs timer control (Virtex-7/Kintex-7 FPGAs only) 34 LogiCORE P Ten-Gigabit Ethernet PCS/PMA

35 MO nterface MO Register 1.0: PMA/PM Control 1 Figure 6-10 shows the MO Register 1.0: PMA/PM Control 1. X-Ref Target - Figure 6-10 Reg LOOPBACK RSV SPEE SPEE RSV POWER OWN RSV SPEE RSV RESET Figure 6-10: PMA/PM Control 1 Register Table 6-7 shows the PMA Control 1 register bit definitions. Table 6-7: PMA/PM Control 1 Register Bit efinitions Bit(s) Name escription Attributes efault Value Reset 1 = Block reset 0 = Normal operation The 10GBASE-R block is reset when this bit is set to 1. t returns to 0 when the reset is complete. R/W Self-clearing Reserved The block always returns 0 for this bit and ignores writes. R/O Speed Selection The block always returns 1 for this bit and ignores writes. R/O Reserved The block always returns 0 for this bit and ignores writes. R/O Power down This bit has no effect. R/W :7 Reserved The block always returns 0 for these bits and ignores writes. R/O All 0s Speed Selection The block always returns 1 for this bit and ignores writes. R/O :2 Speed Selection The block always returns 0s for these bits and ignores writes. R/O All 0s Reserved The block always returns 0 for this bit and ignores writes. R/O All 0s Loopback 1 = Enable PMA loopback mode 0 = isable PMA loopback mode Virtex-6 FPGAs: The 10GBASE-R block will loop the transmit signal inside the GTH transceiver back into the receiver. Note: The vendor-specific register bits :0 take precedence over this bit. R/W 0 LogiCORE P Ten-Gigabit Ethernet PCS/PMA 35

36 Chapter 6: nterfacing to the Core MO Register 1.1: PMA/PM Status 1 Figure 6-11 shows the MO Register 1.1: PMA/PM Status 1. X-Ref Target - Figure 6-11 Reg RSV POWEROWN ABLTY RX LNK STATUS RSV LOCAL FAULT RSV Figure 6-11: PMA/PM Status 1 Register Table 6-8 shows the PMA/PM Status 1 register bit definitions. Table 6-8: PMA/PM Status 1 Register Bit efinitions Bit(s) Name escription Attributes efault Value :8 Reserved The block always returns 0 for this bit. R/O Local Fault The block always returns '0' for this bit. R/O :3 Reserved The block always returns 0 for this bit. R/O Receive Link Status Power own Ability The block always returns '1' for this bit R/O 1 The block always returns 1 for this bit. R/O Reserved The block always returns 0 for this bit. R/O LogiCORE P Ten-Gigabit Ethernet PCS/PMA

37 MO nterface MO Register 1.4: PMA/PM Speed Ability Figure 6-12 shows the MO Register 1.4: PMA/PM Speed Ability. X-Ref Target - Figure 6-12 Reg G CAPABLE RSV Figure 6-12: PMA/PM Speed Ability Register Table 6-9 shows the PMA/PM Speed Ability register bit definitions. Table 6-9: PMA/PM Speed Ability Register Bit efinitions Bit(s) Name escription Attribute efault Value :1 Reserved The block always returns 0 for these bits and ignores writes. R/O All 0s G Capable The block always returns 1 for this bit and ignores writes. R/O 1 MO Registers 1.5 and 1.6: PMA/PM evices in Package Figure 6-13 shows the MO Registers 1.5 and 1.6: PMA/PM evices in Package. X-Ref Target - Figure 6-13 Reg Reg 1.5 VENOR1 PRESENT VENOR2 PRESENT CLAUSE 22 EXT.N PRESENT RSV CLAUSE 22 PRESENT PM/PMA PRESENT WS PRESENT PCS PRESENT PHY XS PRESENT TE XS PRESENT TC PRESENT AN PRESENT RSV Figure 6-13: PMA/PM evices in Package Registers LogiCORE P Ten-Gigabit Ethernet PCS/PMA 37

38 Chapter 6: nterfacing to the Core Table 6-10 shows the PMA/PM evice in Package registers bit definitions. Table 6-10: PMA/PM evices in Package Registers Bit efinitions Bit(s) Name escription Attributes efault Value Vendor- specific evice 2 Present Vendor-specific evice 1 Present The block always returns 0 for this bit. The block always returns 0 for this bit. R/O 0 R/O Clause 22 Extension Present Virtex-7/Kintex-7 FPGAs: The block always returns '0' for this bit. Virtex-6 FPGAs: The block always returns '1' for this bit. R/O Virtex-7/ Kintex-7 FPGAs: 0 Virtex-6 FPGAs: :0 Reserved The block always returns 0 for these bits :8 Reserved The block always returns 0 for these bits. R/O R/O All 0s All 0s Autonegotiation present Virtex-7/Kintex-7 FPGAs: The block always returns '0' for this bit. Virtex-6 FPGAs: The block always returns '1' for this bit. R/O Virtex-7/ Kintex-7 FPGAs: 0 Virtex-6 FPGAs: TC Present The block always returns '0' for this bit TE XS Present The block always returns 0 for this bit PHY XS Present The block always returns 0 for this bit PCS Present The block always returns 1 for this bit WS Present The block always returns 0 for this bit. R/O 0 R/O 0 R/O 0 R/O 1 R/O PMA/PM Present Clause 22 evice Present The block always returns 1 for this bit. The block always returns 0 for this bit. R/O 1 R/O LogiCORE P Ten-Gigabit Ethernet PCS/PMA

39 MO nterface MO Register 1.7: 10G PMA/PM Control 2 Figure 6-14 shows the MO Register 1.7: 10G PMA/PM Control 2. X-Ref Target - Figure 6-14 Reg PMA/PM TYPE SELECTON RSV Figure 6-14: 10G PMA/PM Control 2 Register Table 6-11 shows the PMA/PM Control 2 register bit definitions. Table 6-11: 10G PMA/PM Control 2 Register Bit efinitions Bit(s) Name escription Attributes efault Value :4 Reserved The block always returns 0 for these bits and ignores writes. R/O All 0s 1.7.3:0 PMA/PM Type Selection Virtex-7/Kintex-7 FPGAs: This returns the value '0xyz', where 'xyz' is set from the top level core port pma_pmd_type vector. Virtex-6 FPGAs: The block returns a code for the 10GBASE-*R PMA/PM and ignores written values which do not correspond to the PCS_ABLTY register settings (1.8.7:1) denotes 10GBASE-SR, 0110 denotes -LR and 0101 denotes -ER. R/W Virtex-7/Kintex-7 FPGAs: Set from pma_pmd_type port. Virtex-6 FPGAs: Set from GTH transceiver attribute. LogiCORE P Ten-Gigabit Ethernet PCS/PMA 39

40 Chapter 6: nterfacing to the Core MO Register 1.8: 10G PMA/PM Status 2 Figure 6-15 shows the MO Register 1.8: 10G PMA/PM Status 2. X-Ref Target - Figure 6-15 Reg PMA LOOPBACK ABLTY 10GBASE-EW ABLTY 10GBASE-LW ABLTY 10GBASE-SW ABLTY 10GBASE-LX4 ABLTY 10GBASE-ER ABLTY 10GBASE-LR ABLTY 10GBASE-SR ABLTY PM TX SABLE ABLTY RSV RX FAULT TX FAULT RX FAULT ABLTY TX FAULT ABLTY EVCE PRESENT Figure 6-15: 10G PMA/PM Status 2 Register Table 6-12 shows the PMA/PM Status 2 register bit definitions. Table 6-12: 10G PMA/PM Status 2 Register Bit efinitions Bit(s) Name escription Attributes efault Value :14 evice Present The block always returns 10 for these bits. R/O Transmit Local Fault Ability Receive Local Fault Ability The block always returns '0' for this bit. R/O 0 The block always returns '0' for this bit R/O Transmit Fault The block always returns '0' for this bit. R/O Receive Fault The block always returns '0' for this bit. R/O Extended abilities The block always returns '1' for this bit. R/O PM Transmit isable Ability The block always returns '1' for this bit. R/O GBASE-SR Ability Virtex-7/Kintex-7 FPGAs: Returns a '1' if pma_pmd_type port is set to '111' Virtex-6 FPGAs: The block always returns 1 for this bit. R/O Virtex-7/Kintex-7 FPGAs: epends on pma_pmd_type port Virtex-6 FPGAs: GBASE-LR Ability Virtex-7/Kintex-7 FPGAs: Returns a '1' if pma_pld_type port is set to '110' Virtex-6 FPGAs: The block always returns 1 for this bit. R/O Virtex-7/Kintex-7 FPGAs: Returns a '1' if pma_pld_type port is set to '110' Virtex-6 FPGAs: GBASE-ER Ability Virtex-7/Kintex-7 FPGAs: Returns a '1' if the pma_pmd_type port is set to '101' Virtex-6 FPGAs: The block always returns 1 for this bit. R/O Virtex-7/Kintex-7 FPGAs: epends on pma_pmd_type port Virtex-6 FPGAs: GBASE-LX4 Ability The block always returns 0 for this bit. R/O LogiCORE P Ten-Gigabit Ethernet PCS/PMA