CS3330 Spring 2015 Exam 2 Page 1 of 6 ID:

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1 S3330 Spring 2015 xam 2 Page 1 of 6 mail I: S3330 xam 2 Spring 2015 Name: irections: Put the letter of your selection or the short answer requested in the box. Write clearly: if we are unsure what you wrote you will get a zero on that problem. Test proctors will not provide clarification during the exam. If you find something ambiguous or unclear, explain that clearly on your exam and add a * to the top right corner of your answer box so we know to look for your note when grading. If you do not sign the pledge on the last page you will get a zero on the entire exam Question 1: In the FMW five-stage pipeline we analyzed in class, if we want to stall writeback which many pipeline register(s) should be given the bubble signal? Select all that apply F the register before fetch the register before decode the register before memory the register before writeback the register before execute Question 2: If we cut power for one millisecond, which of the following is true? SRM would keep its data, RM would keep its data SRM would keep its data, RM would lose its data SRM would lose its data, RM would lose its data SRM would lose its data, RM would keep its data Question 3: To implement data forwarding, we had to check if each source of one instruction was either destination of any earlier instruction still in the pipeline somewhere. Without data forwarding, which of the following is true? the check for stalling decode doesn t involve sources and destinations we need to compare sources and destinations to decide if we stall decode, but it is a much simpler check we need the same check to decide if we stall decode the above answers are misleading: removing data forwarding doesn t result in stalling decode

2 S3330 Spring 2015 xam 2 Page 2 of 6 mail I: Question 4: If you organize current storage technologies from fastest to slowest, you have also organized them from most expensive to least expensive. This is because slow-and-expensive technologies don t survive in the market so they don t make the list it s cause-and-effect: running quickly consumes money it s cause-and-effect: spending money makes things faster it s just a coincidence; new technologies could change that Question 5: In the FMW five-stage pipeline we analyzed in class, if we want to stall memory how many pipeline registers should be given the stall signal? F 1 Question 6: In the FMW five-stage pipeline we analyzed in class, if we want to stall decode how many pipeline registers should be given the normal operation signal? F 1 Question 7: apacity misses are typically discussed in connection with direct-mapped caches fully-associative caches set-associative caches all of the above Question 8: In the simulators we worked with the register file had two write ports, dst/wval and dstm/wvalm. However, only the popl operations used them both. Which two registers are written by popl %eax? Write two letters in the box (e.g., if you think it is the first two options, write ) F G H ebp esp edx ebx eax ecx esi edi

3 S3330 Spring 2015 xam 2 Page 3 of 6 mail I: Question 9: In the FMW five-stage pipeline we analyzed in class, if we want to bubble decode how many pipeline registers should be given the normal operation signal? F 5 Question 10: onsider the 10-bit address FGH I J, where each letter represents one bit. With 8-byte blocks, 4 lines per set, and 16 sets, what is the tag? Write your answer in the box; e.g., if you think the answer is the first two bits write. Question 11: Suppose one stage of a pipeline depends on data forwarded from another, later stage. This describes a dependency hazard a hazard for some pipelines (depending on how many stages there are and/or how many stages are in between the two) a dependency for some pipelines (depending on how many stages there are and/or how many stages are in between the two) Question 12: onflict misses are typically discussed in connection with set-associative caches fully-associative caches direct-mapped caches all of the above Question 13: Set-associative cache X breaks a 32-bit address into a 20-bit tag and a 4-bit block offset. How many sets are there in X? it depends on how many lines there are per set = 256 log 2 (8) = 3

4 S3330 Spring 2015 xam 2 Page 4 of 6 mail I: Question 14: If we cut power for one minute, which of the following is true? SRM would lose its data, RM would lose its data SRM would lose its data, RM would keep its data SRM would keep its data, RM would keep its data SRM would keep its data, RM would lose its data Question 15: irty bits are associated with (pick the best answer): write-through caches set-associative caches write-back caches direct-mapped caches fully-associative caches F all of the above have dirty bits G have dirty bits Question 16: In the simulators we worked with the register file had two write ports, dst/wval and dstm/wvalm. However, only the popl operations used them both. onsider a design where we have only one write port (i.e., the register file can only write one value per cycle) and we implement popl to write one value in writeback one cycle, then to stay in writeback and write the other value the next cycle. This design an t work an work, but will stall sometimes, depending on what instruction precedes popl an work, but will stall sometimes, depending on what instruction follows popl an work, but will always stall for every popl instruction Question 17: When reading from a direct-mapped cache, which of the following will result in a cache miss? Select all that apply by writing one or more letters in the box. Note: some answers are nonsensical, misusing terminology; do not select those answers. F G address s tag does not match cache line s tag address s valid bit does not match cache line s valid bit address s dirty bit does not match cache line s dirty bit the cache line s tag is set the cache line s dirty bit is set the cache line s valid bit is set apply

5 S3330 Spring 2015 xam 2 Page 5 of 6 mail I: Question 18: Fully-associative cache X has 8-byte lines with 32 lines in the cache. If addresses are 12 bits long, how long is the tag? 4 it depends on how many lines there are per set 2 4 = 16 log 2 (4) = 2 Question 19: Magnetic disk seek time is made up of time needed to get to the right track and time needed to get to the right sector. Which of these involves physical motion? both finding the sector neither finding the track Question 20: In a set-associative cache, which of the following does not need to be a power of two? lines per set bytes per block number of sets all of the above must be powers of two Question 21: Supposed a set-associative cache has a fixed total capacity of 128K. To prioritize the performance of code that exhibits high temporal locality but low spatial locality, the cache should (pick the most correct answer): have small sets have large sets have small blocks have large blocks prioritizes temporal over spatial locality Question 22: ddresses,, and all have the same set index; and have the same tag but s tag is different; and have the same block offset but s block offset is different. Starting from a cold direct-mapped cache, how many hits are there when executing the following five reads in order:,,,,? F 4

6 S3330 Spring 2015 xam 2 Page 6 of 6 mail I: Question 23: In the simulators we worked with the register file had two write ports, dst/wval and dstm/wvalm. However, only the popl operations used them both. onsider a design where we have only one write port (i.e., the register file can only write one value per cycle) and we implement popl to write use that write port twice, once during its memory phase and once during its writeback phase. This design an t work an work, but will stall sometimes, depending on what instruction follows popl an work, but will always stall for every popl instruction an work, but will stall sometimes, depending on what instruction precedes popl Question 24: old misses are typically discussed in connection with fully-associative caches set-associative caches direct-mapped caches all of the above Question 25: Given two caches and in a cache hierarchy, where is closer to the PU and is closer to main memory. For every cache hierarchy size() > size() and speed() > speed() size() < size() and speed() < speed() size() > size() and speed() < speed() size() < size() and speed() > speed() None of the above are true of every cache hierarchy Pledge: On my honor as a student, I have neither given nor received aid on this exam. Your signature here