Electronics WorkbenchTM

Transcription

1 Electronics WorkbenchTM MultiVHDL 8 Programmable Logic User Guide TitleShort-Hidden (cross reference text) February A-01

2 Support Worldwide Technical Support and Product Information ni.com National Instruments Corporate Headquarters North Mopac Expressway Austin, Texas USA Tel: Worldwide Offices Australia , Austria , Belgium , Brazil , Canada , China , Czech Republic , Denmark , Finland , France , Germany , India , Israel , Italy , Japan , Korea , Lebanon , Malaysia , Mexico , Netherlands , New Zealand , Norway , Poland , Portugal , Russia , Singapore , Slovenia , South Africa , Spain , Sweden , Switzerland , Taiwan , Thailand , United Kingdom For further support information, refer to the Technical Support Resources and Professional Services page. To comment on National Instruments documentation, refer to the National Instruments Web site at ni.com/info and enter the info code feedback National Instruments Corporation. All rights reserved.

3 Important Information Warranty The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free. A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty. National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it. EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner s failure to follow the National Instruments installation, operation, or maintenance instructions; owner s modification of the product; owner s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control. Copyright Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation. National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction. Portions of this product are provided under license from Green Mountain Computing Systems. Trademarks National Instruments, NI, ni.com, and LabVIEW are trademarks of National Instruments Corporation. Refer to the Terms of Use section on ni.com/legal for more information about National Instruments trademarks. Other product and company names mentioned herein are trademarks or trade names of their respective companies. Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no agency, partnership, or joint-venture relationship with National Instruments. Patents For patents covering National Instruments products, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your CD, or ni.com/patents. WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS (1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN. (2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY, COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS. BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS' TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE

4 Preface Congratulations on choosing MultiVHDL 8 from Electronics Workbench. We are confident that it will deliver years of increased productivity and superior designs. Electronics Workbench is the world s leading supplier of circuit design tools. Our products are used by more customers than those of any other EDA vendor, so we are sure you will be pleased with the value delivered by MultiVHDL 8, and by any other Electronics Workbench products you may select. Documentation Conventions This manual uses the convention Menu/Item to indicate menu commands. For example, File/Open means choose the Open command from the File menu. An arrow ( ) is used to indicate the start of procedural information. This manual also uses the construction CTRL-KEY and ALT-KEY to indicate when you need to hold down the Ctrl or Alt key on your keyboard and press another key. The MultiVHDL 8 Documentation Set MultiVHDL 8 documentation consists of this User Guide, and on-line help. This manual assumes that you are familiar with Windows applications and know how, for example, to choose a menu from a command, use the mouse to select an item, and enable/disable an option. If you are new to Windows, see your Windows documentation for help.

5 Table of Contents 1. Software Installation 1.1 Installation Requirements Installation Overview Installing MultiVHDL Single User Edition Installing the Single User Edition Requesting a Release Code for the Single User Version Multi-Station Standalone Edition Network Version Installing the Network Edition Entering the Release Code for the Network Edition Workstation Setup Setting User Permissions Changing Server Name and/or Port Number After Client Installation Initial Launch Installing Hardware Key Editions Network License Server Administering the Network License Server Administering Fixed Seat Licenses Reviewing License Server Events Troubleshooting Support and Upgrade Checking for Updates Installing Updates Viewing Messages Changing Settings Uninstalling MultiVHDL Uninstalling the Single User Version Uninstalling SUU MultiVHDL 8 User Guide i

6 1.10 Uninstalling a Site Version Uninstalling Standalone Multi-Station Installation Uninstalling Network Installation Uninstalling Combination Standalone Multi-Station and Network Installations Uninstalling NLS License Agreement VHDL Simulation 2.1 What is MultiVHDL? Design Management Features Simulation Features Feature Summary Creating a Project and Using the Hierarchy Browser Creating a Project File Setting Project Options Adding a VHDL Module Creating a VHDL Module Adding an Existing VHDL Module Examining the Project Hierarchy Using the Entity Wizard Invoking the Entity Wizard Specifying the Port List Adding Functionality to a Module Compiling a Module Error Message Dialog Updating (Rebuilding) Your Project Hierarchy Using the Test Bench Wizard Invoking the Test Bench Wizard Verifying the Port List Modifying the Test Bench Using Simulation Understanding Simulation Loading the Project Compiling Modules for Simulation Linking Modules for Simulation Setting Simulation Options ii Electronics Workbench

7 2.5.6 System Options Loading the Simulation Executable Transcript Dialog Starting a Simulation Run Working with the Simulator Interface Using the Debug Window Understanding Source-Level Debugging A Sample Project Using the Command Entry dialog box VITAL Simulation Models Using MultiVHDL LIB MultiVHDL s LIB Overview Examining the Contents of a Library File Adding a.an File to a Library Deleting a.an File Reference from a Library MultiVHDL Menu Items Simulator Interface Menu Items Graphical Waveform Editor 3.1 Creating a New Waveform Testbench Creating Clock Waveforms Creating Derived Clock Waveforms Editing Waveforms Adding and Removing Timing Checks Adding and Removing Data Checks One-time Data Checks Exhaustive data checks Setting Graphical Testbench Properties Timing Parameters Limitations Running a Graphical Testbench MultiVHDL 8 User Guide iii

8 3.11 Streams Creating Streams Using a stream for stimulus Using a stream for expected output data Using a stream to save simulation results Multi-field streams Placing Data Paths Between Streams File Stream Reference Setting Up Input File Streams Setting Up Output File Streams Random Stream Reference Setting Up Random Streams Random number generation Floating point numbers State Machine Editor 4.1 Introduction Creating a New State Machine Defining Ports Setting State Machine Properties Adding and Editing States Adding and Editing State Transitions Using local signals Debugging State Machines State Machine Example VHDL Primer 5.1 HDLs Using HDL Models Without the Need to Write HDL Code Using MultiVHDL to Write/Debug HDL Code Using MultiVHDL with Programmable Logic Using MultiVHDL to Model Complex Digital ICs iv Electronics Workbench

9 5.4 VHDL Standards History IEEE Standard IEEE Standard IEEE Standard (Numeric Standard) IEEE Standard (VITAL) Learning VHDL A Simple Example Entity Declarations Architecture Declarations Data Types Design Units Levels of Abstraction Sample Circuit Comparator (Dataflow) Barrel Shifter (Entity) Signals and Variables Using a Procedure Structural VHDL Design Hierarchy Test Benches Sample Test Bench Conclusion Examples Gallery Using Type Version Functions Design Description Test Bench Describing a State Machine Design Description Test Bench Reading and Writing from Files Design Description Test Bench MultiVHDL 8 User Guide v

10 Chapter 1 Software Installation This chapter contains MultiVHDL installation instructions. The following are described in this chapter. Subject Page No. Installation Requirements 1-2 Installation Overview 1-3 Installing MultiVHDL 8 Single User Edition Multi-Station Standalone Edition Network Version Changing Server Name and/or Port Number After Client Installation Initial Launch 1-12 Installing Hardware Key Editions 1-13 Network License Server Administering the Network License Server Administering Fixed Seat Licenses Reviewing License Server Events Troubleshooting Support and Upgrade Checking for Updates Installing Updates Viewing Messages Changing Settings Uninstalling MultiVHDL 8 Uninstalling the Single User Version Uninstalling SUU 1-26 MultiVHDL 8 User Guide 1-1

11 Software Installation Subject Uninstalling a Site Version Uninstalling Standalone Multi-Station Installation Uninstalling Network Installation Uninstalling Combination Standalone Multi-Station and Network Installations Page No Uninstalling NLS 1-27 License Agreement Installation Requirements To successfully install MultiVHDL 8, you may need up to 150 MB of hard disk space, depending on which edition you have purchased. You also need the following system requirements: Minimum System Requirements Windows NT4 SP6/2000/XP Pentium III Processor Recommended System Requirements Windows XP Professional Pentium 4 Processor 128 MB RAM 256 MB RAM CD-ROM CD-ROM 800 x 600 screen resolution 1024 x Electronics Workbench

12 Installation Overview 1.2 Installation Overview MultiVHDL 8 has three types of installation: Single User Edition, Network Edition, and Multi-Station Standalone Edition. Single User Edition If you are installing MultiVHDL 8 on a single computer that is not part of a network, then you are installing a Single User Edition. Note The Single User Edition is only licensed on the computer on which you install it. If for any reason you wish to move the software to a different computer, you must first uninstall it from the initial computer, and then re-install it onto the new computer. In this case, you must contact Electronics Workbench to receive a new Release Code. For details on the installation process see Installing the Single User Edition on page 1-4. Network Edition If you are installing MultiVHDL 8 in a networked environment, you are installing a Network Edition. For details, see Network Version on page 1-7. Either fixed or floating licenses are available from Electronics Workbench. A floating license allows any computer to run MultiVHDL 8 on a first-come, first-served basis. Maximum concurrent uses are limited to the number of seats you have purchased. A fixed license allows only a set number of specific computers to run the software. You may select and change the specific computers allowed access using the NLS Utility, up to the number of fixed licenses you have purchased (see Administering Fixed Seat Licenses on page 1-17). Multi-Station Standalone Edition If you are installing MultiVHDL 8 on various computers in a non-networked environment, then you are installing a Multi-Station Standalone Edition. This type of installation is identical to that of the Single User Edition, except that you may only install a single copy of MultiVHDL 8 per computer on as many computers as specified by the License Agreement. For details on the installation process see Installing the Single User Edition on page 1-4. Hardware Key Edition For any of the above types of installations, Electronics Workbench can provide you with a hardware key, at an extra cost, which can be used instead of a hardware signature. Use of the hardware key (which plugs into the parallel port on your computer) allows you to move the software from computer to computer without having to contact Electronics Workbench. Use of the hardware key requires an additional installation step. For details, see 1.5 Installing Hardware Key Editions on page MultiVHDL 8 User Guide 1-3

13 Software Installation 1.3 Installing MultiVHDL Single User Edition If you purchased the Single User Edition, you have been provided with an 18-digit Serial Number that you will be required to enter at the time of installation. After installation, and upon running the software for the first time, you will be provided with a hardware signature that uniquely identifies the computer you are installing the software onto. Following the instructions on the MultiVHDL splash screen, you must send your Serial Number and your hardware signature to Electronics Workbench. You will receive a Release Code that enables the software on that hardware. Without the Release Code, after a grace period, your software will not function. Note The Single User Edition is only licensed on the computer on which you install it. If for any reason you wish to move the software to a different computer, you must first uninstall it from the initial computer, and then re-install it onto the new computer. In this case, you must contact Electronics Workbench to receive a new Release Code Installing the Single User Edition The MultiVHDL 8 CD you received will autostart when inserted in the CD-ROM drive. Follow the instructions below and on the screen during the installation process. To install MultiVHDL 8: 1. Copy the Serial Number you have received with your MultiVHDL 8 package in the space below. Serial Number 2. Exit all Windows applications prior to continuing with the installation. 3. Insert the MultiVHDL 8 CD into your CD-ROM drive. When the splashscreen appears, click on MultiVHDL 8 to begin the installation. 4. When the Welcome dialog appears click Next to continue. 5. Read the License Agreement. Click on the Next button if you agree with the terms of the License Agreement and want to continue with the installation. If you do not agree with the terms of the License Agreement, select I do not accept the terms of the license agreement and click on the Next button. The installation will be terminated and MultiVHDL 8 will not be installed in your computer. 6. Enter your name, company and serial number (as recorded above). Click Next to continue. 1-4 Electronics Workbench

14 Installing MultiVHDL 8 7. When the Support and Upgrade Utility Settings (SUU) dialog appears, select the desired level of service in order to be notified of any updates. Click on Next to continue. 8. You will find a link to Electronics Workbench s privacy policy in this dialog. You may read it and then click Next to continue. Note If you do not wish to provide Electronics Workbench with information through SUU then uncheck the box selection and click Next to continue. 9. Select the location in which you wish to install MultiVHDL 8. Click on the Browse button to select a different location or click on the Next button to accept the default location. 10.When prompted, enter the country where you are located and your language of preference for SUU to send you information about your product and any updates that may be available to you. Click Next to continue. 11. Click on the Finish button to complete your MultiVHDL 8 installation. If enabled, SUU will check for any program updates available for your product. We strongly recommend that you keep SUU enabled to receive the latest patches to the software. MultiVHDL 8 User Guide 1-5

15 Software Installation Requesting a Release Code for the Single User Version MultiVHDL 8 requires you to enter a Release Code within five days of the date of installation. After the five day grace period has expired, MultiVHDL 8 will not run until a Release Code is entered. To obtain your Release Code, you must provide us with your Serial Number and Signature number, as displayed on the splash screen. Contact Electronics Workbench via our website (preferred method) at and select the Product Registration link, or call Customer Service at Customers outside North America should contact their local distributor. Electronics Workbench recommends that you obtain your Release Code as soon as possible after you have installed MultiVHDL 8. Note The Release Code that you will be provided with is composed of 60-alphanumeric characters. Electronics Workbench recommends that you use one of the recommended methods below to enter the Release Code. To enter the Release Code: 1. Click on the Enter Release Code button at the start-up splash screen. 2. If you have received your Release Code via there are a few ways to easily enter it without the need to type each number or character one at a time. Select one of the following methods: Highlight the Release Code. Drag and drop it on one of the text boxes. Highlight the Release Code, right-click on it and select Copy. Click on the Paste Release Code button. Highlight the Release Code, right-click on it and select Copy. Right-click on one of the text boxes and click on Paste from the pop-up menu. 3. If you have received your Release Code over the phone, you must type it in the Release Code fields 5 characters at a time. 4. Click Accept to continue. 1-6 Electronics Workbench

16 Installing MultiVHDL Multi-Station Standalone Edition If you purchased the Multi-Station Standalone edition, you have been provided with one 18- digit Serial Number that you will use for each computer. You must then go to each computer on which MultiVHDL is installed, and separately request a Release Code for each, which enables the software on that computer. Because of this inconvenience, and because of the fact that the software is tied to particular computers, the Network Edition is the preferred alternative in networked settings. The installations are identical except that you will re-use the same Serial Number multiple times Network Version For network versions, the client software (MultiVHDL 8) may be installed: 1. On a central file server that serves the software to other networked computers (called "workstations"). 2. Locally on each workstation computer. This option gives the best performance, as the software need not be accessed across a network. However, it takes up the most disk space on the workstation computers, and requires updates to be installed separately on each workstation. This option can be combined with option 1, where some workstations may have the client software installed locally, and other workstations may have the software served from a shared file system. 3. On several file servers, each one of which serves the software to a subset of the networked computers, and, optionally, also on selected workstation computers. This option is intermediate between options 1 and 2. If options 1 or 3 are selected, the network must be set up to allow access from the workstations to the shared file systems on which the client software is installed. For all of the options above (1, 2 or 3), you must also install the Electronics Workbench Network License Server (NLS) on any one computer on the network. This computer does not need to share a file system with the client software. However, it requires TCP/IP access from the workstation computers. This computer will run a Windows service that keeps track of and limits the number of licenses currently in use. From that computer, administrators may run the NLS utility that shows information on licenses available, the users currently utilizing the licenses, and enables users to be remotely logged off. As with the single user edition, you have been provided with an 18-digit Serial Number that you will require during each installation of MultiVHDL 8 and for the lone installation of NLS. The Serial Number identifies the product as being a Network Edition. Using NLS, you may access the hardware signature of the NLS server computer. You must send the NLS server's MultiVHDL 8 User Guide 1-7

17 Software Installation hardware signature and your Serial Number to Electronics Workbench. You will receive a Release Code that you will need to enter into NLS to enable the network edition to function. The Release Code encodes the number of seats and any term limits on your license. A MultiVHDL workstation will access either a fixed or a floating license depending upon the Serial Number entered at the time of install of the MultiVHDL 8 client software that the workstation uses. In either the fixed or the floating case, the MultiVHDL 8 client software may be installed either directly on the workstation computer, or onto a shared file server. Different Serial Numbers are provided to you for each of these cases. Note NLS is only licensed on the computer on which you install it. If for any reason you wish to move the NLS service to a different computer, you must first uninstall it from the initial computer, and then re-install it onto the new computer. In this case, you must contact Electronics Workbench to receive a new Release Code Installing the Network Edition The MultiVHDL 8 CD you received will autostart when inserted in the CD-ROM drive. Follow the instructions below and on the screen during the installation process. To install MultiVHDL 8: 1. Copy the Serial Number you have received with your MultiVHDL 8 package in the space below. Serial Number 2. Exit all Windows applications prior to continuing with the installation. 3. Insert the MultiVHDL 8 CD into your CD-ROM drive. When the splashscreen appears, click on MultiVHDL 8 to begin the installation. 4. When the Welcome dialog appears click Next to continue. 5. Read the License Agreement. Click on the Next button if you agree with the terms of the License Agreement and want to continue with the installation. 6. If you do not agree with the terms of the License Agreement, select I do not accept the terms of the license agreement and click on the Next button. The installation will be terminated and MultiVHDL 8 will not be installed in your computer. 7. Enter your name, company and serial number. Click Next to continue. 1-8 Electronics Workbench

18 Installing MultiVHDL 8 8. Select your preferred type of network installation: Option 1 Choose MultiVHDL 8 and Network License Server if you wish to install both The Network License Server (NLS) and MultiVHDL 8 on the same computer. You will select this option if your central file server is the same computer as your license server, or if you wish to install the license server on this machine and also wish to install a local client copy of the software. NLS will be installed into the same folder as MultiVHDL 8. If you wish these to be installed into different folders, then install the two components separately as described below. Option 2 Choose Network License Server Only if you wish to only install NLS and not MultiVHDL 8. Option 3 Choose MultiVHDL 8 Only if you wish to only install the client software MultiVHDL 8 on either a shared file system for serving out to other workstation computers, or if you wish to install MultiVHDL 8 on each workstation computer directly. Note You will need to install NLS prior to installing MultiVHDL Click Next to continue. 10.Select the location in which you wish to install MultiVHDL 8 and/or NLS. Click on the Browse button to select a different location or click on the Next button to accept the default location. 11. The EWB Network License Information dialog will prompt you for the Server on which NLS is installed and the TCP Port Number that it uses. If installing MultiVHDL 8, the client software will be configured to use the port number shown here. If you have changed the port number when installing NLS or subsequently using the NLS Utility, be sure that the port numbers match. If installing NLS, typing a different number for the port will force NLS to use this port rather than its default. This may also be changed using the NLS Utility at a later time. MultiVHDL 8 User Guide 1-9

19 Software Installation When installing MultiVHDL 8, the EWB Network License Information dialog will prompt you for the Server name by which the NLS server is to be known to the workstations running MultiVHDL 8. You may provide the name of the server, the IP number of the server, or a network alias for the server name. In order to facilitate moving NLS to a different computer, we recommend that you use a name, such as ewbnls, that you set up to be an alias for the machine name of the license server. If you later choose to move the license server to a different machine, you need only change the network alias and the workstations will continue to find the license server without modification. For help in setting up a machine name alias, consult your network administrator. 12.Click on the Test button to test the connection to the server. If you fail to connect, doublecheck that the Server and Port settings correspond to your NLS installation and try again. If you still fail to connect, check your firewall settings. Click Next to continue. Note See also, Troubleshooting on page Click on the Finish button to complete the installation Entering the Release Code for the Network Edition After installing NLS, you will be required to enter a Release Code to enable the workstations to run MultiVHDL 8. To perform this step, you will need to use the NLS Utility that you have previously installed on your license server. See 1.6 Network License Server on page 1-14 for further information Workstation Setup If for your Network Installation you choose to serve MultiVHDL 8 from a file server to the workstation computers, you will need to perform an extra setup step on each workstation computer as follows. 1. Logon to each workstation with administrator privileges. 2. Using Windows Explorer, navigate to the <install-root>\multivhdl8\setup folder on the computer drive where MultiVHDL 8 was installed on the network. 3. Double-click on setup.exe to install the shortcuts to the software on the computer. The setup routine will configure the workstation. Access to MultiVHDL 8 directories should be restricted by placing certain user permissions on various directories. Follow the instructions below to place the appropriate permissions Electronics Workbench

20 Installing MultiVHDL Setting User Permissions If you are installing the MultiVHDL 8 Network Edition, you will need to set certain restrictions on the folder where MultiVHDL is installed in order to prevent nonadministrative users from modifying, writing or deleting program files that otherwise would make the software unusable. Note that there are many different ways to set permissions in a networked environment. The following settings are one way of configuring a Windows XP Professional-based computer that is not part of a network domain (i.e., using workgroup sharing). It is recommended that you have advanced knowledge of NTFS and share permissions. Contact your administrator for help. MultiVHDL 8 Permissions on a Windows XP Professional-based Computer 1. Browse to <install-root>\multivhdl8, where the MultiVHDL 8 Network Edition is installed on the server. 2. Right-click on the \MultiVHDL8 folder and click on Sharing and Security from the pop-up menu. 3. Click on the Sharing tab on the MultiVHDL8 Properties dialog and select Share this folder. 4. Click on the Permissions button. The Permissions for MultiVHDL8 dialog will popup. 5. Under Groups or user names, select the security group that requires access to MultiVHDL 8. (If everybody on the network is allowed access, select Everyone ). 6. Set the following permissions: Permission Allow Deny Full Control Change Read X X X All other options shown on the dialog should be unchecked unless specified on the above table. Click OK to accept the permissions. 7. Click on the Security tab and select the appropriate group under Group or user names. 8. Click on the Advanced button. The Advanced Security Settings for EWB8 dialog will pop-up. 9. On the Permissions tab, click on the Edit button. The Permissions Entry for EWB8 dialog will pop-up. MultiVHDL 8 User Guide 1-11

21 Software Installation 10.Set the following permissions: Permission Allow Deny Read & Execute List Folder Contents Read X X X All other options shown on the dialog should be unchecked unless specified on the above table. Under the Advanced tab, make sure that the option Inherit from parent the permission entries that apply to child objects. Include these with entries explicitly defined here is unchecked. Place a check mark on Replace permission entries on all child objects with entries shown here that apply to child objects. Click OK to accept the permissions. 11. Click OK on the MultiVHDL8 Properties dialog. You have now set up the MultiVHDL8 folder directory and all sub-directories and files with Read & Execute permissions Changing Server Name and/or Port Number After Client Installation If for some reason, after having installed MultiVHDL 8 on workstations and/or file servers it becomes necessary to change the server name or port number, it is possible to do this without re-installing the client software. On each MultiVHDL 8 installation, navigate to the Settings sub-directory (by default located in 'C:\Program Files\Electronics Workbench\MultiVHDL8\Settings') and use a text editor (such as Notepad) to edit the file MultiVHDL.ini. Change the entries next to Port and Server. 1.4 Initial Launch The first time you launch MultiVHDL: 1. Select Start - All Programs - Electronics Workbench - MultiVHDL 8 - MultiVHDL Electronics Workbench

22 Installing Hardware Key Editions 2. If the following dialog appears, click Yes to build the libraries indicated in the dialog. A dialog box displays and is updated as the libraries are built. When the process is complete, MultiVHDL launches. Note The library build process may take some time. Tip If you launch MultiVHDL from Multisim (using Simulate/VHDL Simulation) and you receive an error message, launch MultiVHDL from the Start button on the lower left of your screen as indicated above, to display more detailed error messages. 1.5 Installing Hardware Key Editions If you chose to install MultiVHDL 8 or NLS using a Hardware Key as opposed to a Hardware Signature, then you have been provided with one or more parallel port keys. Other than the one extra step described below, the installations are identical to those described in their respective sections. The extra installation step may be performed at any time prior to requesting your Release Code from Electronics Workbench. On each computer on which you plan to use the hardware key you must install the hardware key driver software prior to using it. The install script is located on your MultiVHDL 8 installation CD at <CD Drive>:\FSCOMMAND\VHDLINST\HARDWARE KEY\SETUP.EXE. Use Explorer to navigate to this file on your installation CD, or from the Windows Start Menu, select "Run..." and type <CD Drive>:\FSCOMMAND\VHDLINST\HARDWARE KEY\SETUP.EXE. Prior to running the software for the first time (either MultiVHDL 8 or NLS in the case of a Network Installation) you must insert the hardware key into the computer. Instead of using the computer's unique hardware signature, the software will use a hardware signature uniquely associated with the installed hardware key. Request a Release Code in the usual manner, as described above. The Release Code will be suitable for use on any computer into which the hardware key is installed. MultiVHDL 8 User Guide 1-13

23 Software Installation 1.6 Network License Server The Network License Server (NLS) is used to administer network installations. If you have installed a network version of any Electronics Workbench software, the Network License Server will automatically run in the background whenever the computer on which it is installed is operating Administering the Network License Server To administer the Network License Server: 1. Click Start > All Programs > Electronics Workbench > Network License Server > Network License Server. Or Double-click on the short-cut icon that was placed during installation. The first time you open the dialog after installing MultiVHDL, it will appear similar to the following: If desired, you can right-click here to change the Port setting. Note Network seats will also be showing if they were added during the installation process. 2. Click New to add a product. The Add Product dialog box appears. 3. Enter a valid serial number and click OK. Tip If you have the serial number recorded electronically (for instance, in an ), you can drag-and-drop it into the field in the Add Product dialog box Electronics Workbench

24 Network License Server The product is added as shown below. Right-click here and select Edit Release Code from the pop-up. 4. Right-click on the Release Code line as shown above and select Edit Release Code from the pop-up. 5. You can either copy the release code and click Paste Release Code, drag-and-drop the release code into any of the Release Code fields, or type it in manually. MultiVHDL 8 User Guide 1-15

25 Software Installation 6. Click Save to return to the main dialog box. 7. When network seats are being used, the dialog will appear similar to the following: Right-click to edit release codes, edit serial numbers or remove the product Right-click to edit serial number Right-click to edit release code Right-click to logoff all users Right-click on individual users to log them off Click to restart the Network License Server software. Click to add a new product Electronics Workbench

26 Network License Server Administering Fixed Seat Licenses This section gives additional information needed for the administration of Fixed Seat Licenses. To add (authorize) a seat signature: 1. Go the computer that contains the client software that you wish to add (for example, Multisim 8) and launch the software. As this software is not yet authorized, a message similar to the following displays. Record the signature. 2. Copy down the signature as shown above. MultiVHDL 8 User Guide 1-17

27 Software Installation 3. Right-click on Authorized Seat Signatures and select Authorize a new computer from the pop-up that displays. The following dialog displays. 4. Click OK to continue. The following dialog displays. 5. Enter the signature that you copied down from the client computer and click OK. Authorized and Available Seats Number of seats logged in Number of Authorized Seats Maximum Seats Available 1-18 Electronics Workbench

28 Network License Server Reviewing License Server Events The Network License Server records all client connections or attempted connections in the system event log. To access the event log, go to the Windows Control Panel, select Administrative Tools, and then select Event Viewer. In the left-hand pane of the Event Viewer, choose Application Log. All events with the source EWBNLSS are from the Network License Server. Double-click on any event to see more detail Troubleshooting The following contains solutions to situations that may be encountered with the Network License Server. Network License Server gives Permission Denied message. For security reasons, the Network License Server may only be run from an account with administrator privileges. Attempting to control the license server from a user or power user account will cause a permission denied error. Client application gives Connection to the license server failed message. Make sure that the server address and port number on the client Network License Server dialog have been set correctly. If you have entered a machine name as the server address, try using the numeric IP address instead. In some networks, this IP address may change dynamically. Please contact your network administrator for assistance if this occurs frequently. If either the server machine or client machine has a firewall installed (including the Windows XP service pack 2 internal firewall), make sure that either: a) the required port is allowed to be open (in TCP protocol) or b) the server program (EWBNLSS) or client application is granted an exception. Please see your firewall s documentation for more information. Client application gives This product is not registered on the license server message. Make sure that you have used the same product serial number on both the client and the server. Make sure that the registration code has been accepted by the license server. No client application will be licensed until the product has been successfully registered. MultiVHDL 8 User Guide 1-19

29 Software Installation Client application gives No more instances of the program can be run on the network message. This message is returned when all available license seats have been used up. When a user shuts down the client application normally, their seat should be released immediately; however, when a client application terminates unexpectedly (the computer is turned off while running or there is a fatal error), the license server may take up to five minutes to relinquish this license for reuse. If you believe that there should be seats available and clients are being denied licenses, waiting for five minutes to log on is usually sufficient to allow these seats to be freed. The administrator may also wish to check the Network License Server control screen and try to identify unused but unreleased licenses by their computer name or IP address subdomain. If the administrator logs off these users, their licenses will be immediately available for new clients. The administrator may also check for users running multiple clients on a single machine. In extreme cases, the administrator may click the Restart button on the Network License Server. This will immediately release all licenses, and then reissue them silently to active authorized users only. For most client users, this will be an invisible process. This option should however be used with caution: if the number of clients requesting licenses is indeed over the seat limit, the license server cannot guarantee that exactly the same set of clients will be granted licenses as had them before the reset operation. Therefore, some authorized clients may be given the no more instances of the program can be run on the network message in the middle of their active session and be prohibited from continuing their work (however, they will be given the opportunity to save their work). 1.7 Support and Upgrade The Support and Upgrade program lets you call Electronics Workbench with your technical questions. The program also entitles you to no-charge upgrades to the software as new versions are released. Between major upgrade releases, Electronics Workbench puts out a series of patches that may add incremental functionality, add new parts to the database, or quickly address any issues found in the field. If you allow it to (a choice you initially make upon install and can later change), MultiVHDL will quickly and silently check the Electronics Workbench website for the availability of new patches and upgrades when you start the application. If any are available, it will pop-up the Support and Upgrade Utility (SUU) program that will allow you to download and install all the necessary patches to get you to the most current version of your product Electronics Workbench

30 Support and Upgrade Checking for Updates Unless you selected I will check for updates and messages manually during the installation of MultiVHDL, SUU checks for updates when you launch MultiVHDL. You can also check for updates at any time by following the procedure below. To check for updates: 1. From the Start button in the lower-left side of your screen, select: Start - All Programs - Electronics Workbench - MultiVHDL 8 - Check for Updates. SUU launches and checks for updates. 2. If updates are available, the dialog appears as shown below: Click to view release notes associated with available upgrades. Note A message advising that your software is up-to-date appears if there are no updates available. 3. Proceed to Installing Updates on page Installing Updates Use the procedure below to install updates. To determine if updates are available, see Checking for Updates on page Most users will install all available upgrades. You can also upgrade to a specific version. This option should only be used to ensure parallel versions of software are being run within an organization or institution. MultiVHDL 8 User Guide 1-21

31 Software Installation Installing all Updates To install all available updates: 1. From the Support and Upgrade Utility, click on Upgrade to Latest Version. Patch information appears as download progresses When all downloads have been made the install process begins. 2. Follow the onscreen prompts (if available) to complete the upgrade. Note Some patches may be configured to install without user input Electronics Workbench

32 Support and Upgrade Upgrading to a Specific Version To upgrade to a specific version: 1. From the Support and Upgrade Utility, click on Advanced Options. Click to view a brief description of each upgrade 2. Click on a button in the Upgrade to Specific Version column, for example, Click Yes when prompted to confirm the upgrade. Patch information appears as download progresses MultiVHDL 8 User Guide 1-23

33 Software Installation When all downloads have been made the install process begins. 4. Follow the onscreen prompts to complete the upgrade Viewing Messages To view messages: 1. From the Start button in the lower-left side of your screen, select: Start - All Programs - Electronics Workbench - MultiVHDL 8 - Check for Updates. SUU launches and checks for updates. (For instructions on what to do if there are available updates, see Installing Updates on page 1-21). 2. Click on more info... in the Messages area, beside the message of interest. The full message appears. 3. You can also click on Message History to display a history of received messages Changing Settings The initial settings for SUU are done during MultiVHDL s installation procedure. For details, see 1.3 Installing MultiVHDL 8 on page 1-4. If you would like to change these settings, please follow the procedure outlined below. To change the Support and Upgrade Utility s settings: 1. From the Start button in the lower-left side of your screen, select: 1-24 Electronics Workbench

34 Uninstalling MultiVHDL 8 Start - All Programs - Electronics Workbench - MultiVHDL 8 - Check for Updates. SUU launches and checks for updates. (For instructions on what to do if there are available updates, see Checking for Updates on page 1-21). 2. Click on the Settings button. Displayed text changes depending on where you hover the cursor Note The Language field applies to messages only. The sofware s language is not affected by this setting. 3. Select the desired options and click OK. 1.8 Uninstalling MultiVHDL Uninstalling the Single User Version 1. Ensure you have recorded the serial number in Installing the Single User Edition on page Click the Windows Start button. 3. Click Control Panel. 4. Click Add or Remove Programs. The Add or Remove Programs dialog appears. 5. From the list, select MultiVHDL 8 and select Remove. MultiVHDL 8 will be removed from your computer. MultiVHDL 8 User Guide 1-25

35 Software Installation 1.9 Uninstalling SUU To uninstall SUU: 1. Click the Windows Start button. 2. Click Control Panel. 3. Click Add or Remove Programs. The Add or Remove Programs dialog appears. 4. From the list, select EWB Support and Upgrade Utility and select Remove. SUU will be removed from the standalone workstation Uninstalling a Site Version Uninstalling Standalone Multi-Station Installation At each standalone workstation, perform the following procedure: 1. Ensure you have recorded the serial number. 2. Click the Windows Start button. 3. Click Control Panel. 4. Click Add or Remove Programs. The Add or Remove Programs dialog appears. 5. From the list, select MultiVHDL 8 and select Remove. MultiVHDL 8 will be removed from the standalone workstation Uninstalling Network Installation Only the workstation that was used to install MultiVHDL 8 to the network directory (host computer) can be used to remove it. Performing the steps below on other workstations (client computer) will only remove the MultiVHDL 8 folder. To uninstall MultiVHDL 8 from the network directory or the MultiVHDL 8 folder: 1. Ensure you have the serial number and any Feature Codes written down prior to uninstalling MultiVHDL Click the Windows Start button. 3. Click Control Panel. 4. Click Add or Remove Programs. The Add or Remove Programs dialog appears Electronics Workbench

36 Uninstalling NLS 5. From the list, select MultiVHDL 8 and select Remove. If the workstation is the host computer, MultiVHDL 8 is removed from the network directory. If the workstation is only a client computer, the MultiVHDL 8 folder is removed Uninstalling Combination Standalone Multi- Station and Network Installations Follow the instructions in Uninstalling Standalone Multi-Station Installation on page 1-26 and Uninstalling Network Installation on page 1-26, as necessary Uninstalling NLS To uninstall NLS: 1. Click the Windows Start button. 2. Click Control Panel. 3. Click Add or Remove Programs. The Add or Remove Programs dialog appears. 4. From the list, select EWB Network License Server and select Remove. SUU will be removed from the standalone workstation License Agreement Please read this license carefully before installing and using the software contained in this package. By installing and using the software, you are agreeing to be bound by the terms of this license. If you do not agree to the terms of this license, simply return the unused software within thirty days to the place where you obtained it and your money will be refunded. This version of the License Agreement was current at the time of printing. However, Electronics Workbench reserves the right to update the License Agreement from time to time, and it is the version which is current at the time you install the software that you agree to be bound by. For the most up-to-date version of this License Agreement, please go to 1. Copyright. The software in this package is copyright Electronics Workbench Corporation (EWB). The software is licensed for use only on the terms set forth below, as applicable. The software is installed on a computer when it is loaded into the hard drive or any other storage device of that computer. The software is installed on a network when it is loaded into a hard drive or any other storage device accessible from stations on that network. You may not rent, sell, lease, sub-license, time-share or loan the software to others. You may not transfer this MultiVHDL 8 User Guide 1-27

37 Software Installation license without the written permission of EWB. Failure to comply will result in the automatic termination of this license. Single User Edition. This Agreement permits you to install one copy of the software, which is licensed as a single product. You must pay for additional copies if you wish to install the software on more than one computer at the same time or on a network. Certain exceptions to this policy exist in specific circumstances. Please contact Electronics Workbench for details. Floating Network Edition. This floating network license allows you to install this software on a network. Each station shall consist of only one computer with only one user at a time. The number of users restricted by this license is determined by the total number of stations running the software from the network at the same time. The total number of concurrent users your particular license is restricted to is. Named-Node Network Edition. This fixed network license allows you to install this software on a network. Each station shall consist of only one computer with only one user at a time. The number of users restricted by this license is determined by the total number of named stations that can access the software from the network. The total number of users your particular license is restricted to is. Multi-Station Standalone Edition. This multi-station license allows you to install this software on the number of stations specified below. Each station shall consist of only one computer with only one user at a time. The total number of stations your particular multistation license is restricted to is. Student Editions (Student Suite and Multisim Lite). This Agreement permits you to install and use one copy of the software on a home computer owned by you, a registered student at an accredited academic institution, for academic purposes only. Student Versions may not be used on-campus, in a lab environment or otherwise, nor may they be installed as part of an institution-sanctioned laptop program. The software is installed on a computer when it is loaded into the hard drive or any other storage device of that computer. You must pay for additional copies if you wish to install the software on more than one computer at the same time or on a network. 2. Limited Warranty. EWB warrants that under normal use for a period of thirty (30) days from the date of delivery that: (a) the media on which the software is furnished will be free from defects in the material and workmanship; and (b) the software will operate substantially as described in the User's Guide (documentation). In order to make a claim under this warranty you must call EWB for authorization to return any defective item during the warranty period. If you return merchandise to EWB, you must insure the defective item being returned because EWB does not assume the risk of loss or damage while in transit. Upon return of a defective item, EWB shall, upon verification of the defect or error, at EWB's option, either repair or replace the defective copy or refund the amount paid for the license. If EWB elects to provide a refund, upon the date you receive notice of such election, this license shall terminate and you must comply with the provisions set out below Electronics Workbench

38 License Agreement You must assume full responsibility for the selection of this software to achieve your intended purposes, for the proper installation and use of the software and for verifying the results obtained from use of the software. EWB does not warrant in any way that the functions contained in the software will meet your requirements, that the software is fit for any particular purpose or that the operations of the software will be uninterrupted and error-free. 3. Term. The License granted in this agreement is effective until termination. Your misuse shall automatically terminate this license if you breach any of its terms and conditions. Upon termination, you shall return all media containing the software and all documentation to EWB and destroy any copies of the software or any portions of it which have not been returned to EWB, including copies resident in computer memory. 4. Copies, Modification or Merger. You shall not copy or modify all or any portion of the software or documentation or merge it into another software program. Copies shall include, without limitation, any complete or partial duplications on any media, adaptations, translations, compilations, partial copies within modifications, mergers with other material from whatever source, and updated works. You shall use your best efforts to prevent any unauthorized copying of the software. You shall not make any change or modification to any of the executable files, nor shall you reverse engineer, de-compile or disassemble the software or any portion of it, or otherwise attempt to determine the underlying source code of the software or permit any such actions. 5. Disclaimer/Limitation of Liability. EWB expressly disclaims all other warranties, whether oral or written, express or implied, including without limitation warranties of merchantability or fitness for a particular purpose. All warranties shall terminate thirty days from date of delivery of the software to you. Your exclusive remedy and EWB's entire liability arising from or in connection with the software, the software documentation, and/or this license (including without limitation for breach of warranty) shall be, at EWB's option, the repair or replacement of the media on which the software is supplied or refund of the license fee. In no event shall EWB's total liability for any damages, direct or indirect, in connection with the software, the software documentation, and/or this license exceed the license fees paid for your right to use this copy of the software, whether such liability arises from any claim based upon contract, warrants, tort or otherwise. In no event shall EWB or its partners be liable for any loss of profit or any other commercial damage, including but not limited to special, incidental, consequential or other damages, resulting from or in any way connected with the use of this software and including but not limited to any damages resulting from the use of the software for any special or high-risk applications such as those relating to or involving nuclear designs, medical devices and other critical or potentially dangerous applications. EWB specifically disclaims any other warranties, expressed or implied, including but not limited to the implied warranties of merchantability and fitness for a particular purpose. MultiVHDL 8 User Guide 1-29

39 Software Installation Some jurisdictions do not allow the exclusion of implied warranties, so the above exclusion may not apply to you. In that event, any implied warranties are limited in duration to thirty (30) days from the date of delivery of the software. This warranty gives you specific legal rights. You may have other rights, which vary from jurisdiction to jurisdiction. No action for any breach of warranty shall be commenced more than one year following the expiration of such warranty. 6. General. You acknowledge that you have read this agreement, understand it and agree to be bound by its terms and conditions. You further agree that it is the complete and exclusive statement of the agreement between you and EWB and supersedes any proposal or prior agreement or any other communications between EWB and you relating to the use of the software. If any provision of this Agreement is unenforceable, all others shall remain in effect. This Agreement shall be governed by the internal laws of the Province of Ontario and Canada, including Canadian copyright laws. The exclusive venue in the event of any suit, proceeding or claim brought by you, and at our option, any suit, proceeding or claim brought by EWB, shall be in the Courts located in Toronto, Ontario. If you have any questions regarding this Agreement, you may contact EWB by writing to us at the address set out below: ELECTRONICS WORKBENCH CORPORATION 111 Peter Street, Suite 801 Toronto, Ontario M5V 2H1 Tel: (416) Fax: (416) Internet: Electronics Workbench

40 Chapter 2 VHDL Simulation This chapter shows you how to set up projects in MultiVHDL, and how to create new modules and test benches. It also includes details on the simulator interface and a debugging example. The following topics are found in this chapter. Subject What is MultiVHDL? Creating a Project and Using the Hierarchy Browser Using the Entity Wizard Using the Test Bench Wizard Using Simulation Working with the Simulator Interface Using the Debug Window Using the Command Entry dialog box Using MultiVHDL LIB MultiVHDL Menu Items Simulator Interface Menu Items Page No What is MultiVHDL? MultiVHDL is a design entry and simulation system that is intended to help you use the VHDL language for advanced circuit design projects. It is also an excellent way to learn VHDL. The system includes a VHDL simulator, source code editor, hierarchy browser, source level debugging and design management features. You can use MultiVHDL to create and manage new or existing VHDL projects. Because VHDL is a standard language, you can use MultiVHDL in combination with other tools, including schematic editors, high-level design tools, and other tools available from third parties. MultiVHDL 8 User Guide 2-1

41 VHDL Simulation Design Management Features MultiVHDL includes many useful features that help you to create, modify and process your VHDL projects. Some of these features are as follows: The Hierarchy Browser shows you an up-to-date view of the structure of your design as you are entering it. This is particularly useful for projects that involve multiple VHDL source files (called modules ) and/or multiple levels of hierarchy. The Entity Wizard helps you create new VHDL design descriptions, by asking you a series of questions about your design requirements, and generating VHDL source file templates for you based on those requirements. The built-in dependency features help you streamline the processing of your design for simulation and synthesis. When you are ready to simulate your design, for example, you simply highlight the design unit (a source file module, entity, architecture, etc.) you wish to have processed and click a single button. There is no need to compile each VHDL source file in the design, or to keep track of your source file dependencies. MultiVHDL does it for you Simulation Features MultiVHDL s built-in simulator is a complete system for the compilation and execution of VHDL design descriptions. It includes a VHDL compiler, linker, and simulator. VHDL design descriptions are compiled into a 32-bit native Windows executable form. When run, these executable files interact with the MultiVHDL system to allow interactive debugging of your circuit. Simulation results (in the form of graphical waveforms and/or textual output) can be easily saved for later or printed on any Windows-compatible printer Feature Summary The following features are found in MultiVHDL: Source-Level Debugging Source-level debugging is provided via a window that allows you to follow the execution of your VHDL design at the level of VHDL source file statements. This is particularly useful for debugging complex sequential statements, determining the order in which statements are processed, and understanding the impact of scheduling, delta cycles and other complex aspects of model execution. For details, see 2.7 Using the Debug Window on page Electronics Workbench

42 Creating a Project and Using the Hierarchy Browser MultiVHDL LIB MultiVHDL s LIB program can be used to create and maintain VHDL library files from your previously-compiled VHDL object files. MultiVHDL s LIB is a DOS application, and is described in detail in 2.10 Using MultiVHDL LIB on page Creating a Project and Using the Hierarchy Browser MultiVHDL operates on one or more VHDL source files that are referenced in a project file. This section describes how to create and use projects, and how to create or import VHDL source files into a project. A project is composed of a project file and one or more VHDL source files, which are referred to as modules. The project file, in addition to containing references to the various VHDL modules in your project, also includes various option settings that you have specified for the project. Each module (VHDL source file) includes one or more VHDL design units that can be selected as needed when the design is processed. Project files (which are created with a.acc file name extension when you choose File/Save Project) include information about the VHDL modules used in the design, as well as the project-specific options that you have specified. Project files do not include the actual VHDL source statements for your design; instead, the VHDL source statements are maintained in separate VHDL source files, which normally have.vhd file name extensions. Note MultiVHDL allows you to use alternative file name extensions, such as.vhdl or.vho, but the built-in text editor will only recognize files with a.vhd file name extension for the purpose of VHDL syntax coloring Creating a Project File To create a project: 1. Launch the MultiVHDL application. 2. Choose File/New Project, or click the New Project button. MultiVHDL 8 User Guide 2-3

43 VHDL Simulation A blank project is created, and the Hierarchy Browser appears. Hierarchy Browser The Hierarchy Browser will contain references to each new VHDL module as it is added or created. Before continuing, it is a good idea to establish a working folder and project name by saving the project file. To save a project and give it a name, choose File/Save Project, or click the Save Project button. After saving your project with a name, you are ready to begin creating or importing VHDL source file modules. First, however, you may want to set a few project options Setting Project Options MultiVHDL includes a variety of program options that you can specify. Some options available in MultiVHDL (such as compile flags and library paths) are related to specific projects, while others (such as the text editor font and toolbar settings) are more general and system-wide. As you learn and use the many features of MultiVHDL, you will find it useful to customize the options settings for your own preferences, and for the requirements of your projects. 2-4 Electronics Workbench

44 Creating a Project and Using the Hierarchy Browser To set MultiVHDL options: 1. Open the Options dialog box, either by choosing any item from the Options menu, or by clicking the Options button in the MultiVHDL toolbar. 2. Click the desired tab, and make your setting. The Options dialog box allows you to set a variety of options related to compilation, linking, simulation and general program operation. 3. To exit the dialog box and save your new option settings, click OK. To exit the dialog box without saving the new settings, click Cancel. For details on each of the tabs in the Options dialog box, see: Compiling Modules for Simulation on page Linking Modules for Simulation on page Setting Simulation Options on page System Options on page Adding a VHDL Module There are two ways to add VHDL modules to your project, depending on whether you are building a project from existing VHDL source files or are creating a new project from scratch Creating a VHDL Module If you do not already have VHDL source files to work with, begin by creating a new, blank VHDL module. MultiVHDL 8 User Guide 2-5

45 VHDL Simulation To create a new VHDL module, choose File/New Module, or click the Create New Module button. The New Module dialog box appears. See Adding a VHDL Module on page 2-5. Note If you have not already saved your project, you will be prompted to save it before the New Module dialog box appears. To create a new, empty VHDL module, click the Create Blank Module button. Note By default, the new module will be added to your project so it is displayed in the Hierarchy Browser. If you do not wish to have the module added to the Hierarchy Browser, you should disable the Add new module to project field in the New Module dialog box. To remove the module, highlight the module name in the Hierarchy Browser and choosing File/Remove Module. Note Removing a module from the Hierarchy Browser does not remove the file from your hard disk. Remove Module only removes the reference to the specified file from the project file Adding an Existing VHDL Module See 2.4 Using the Test Bench Wizard on page See 3.1 Creating a New Waveform Testbench on page 3-1. See 4.2 Creating a New State Machine on page 4-3. See Creating a VHDL Module on page 2-5. To import existing VHDL source files (created outside of MultiVHDL) into your project, or to copy and use a module (such as a test bench) from one of MultiVHDL s standard examples, use the Add Module command to add one or more VHDL source file to the Hierarchy Browser display, and to the project. To add an existing module: 1. Choose File/Add Module, or click the Add Module button. 2. Navigate to MultiVHDL s samples folder and select one of the example directories (for example,...samples\cache). 2-6 Electronics Workbench

46 Creating a Project and Using the Hierarchy Browser 3. Highlight (press the SHIFT key and click) all.vhd files listed. 4. Click Open to add all selected.vhd files to your project. When you import modules using Add Module, if the selected VHDL source files are not in the current project folder, they will be copied to the current folder before being added to the project. Note It is not possible to create projects that directly reference VHDL files located in other folders. You can, however, use the library features of MultiVHDL to create precompiled modules in different folders on your system. For more details on the library features of MultiVHDL see 2.10 Using MultiVHDL LIB on page Examining the Project Hierarchy When you have created or imported one or more VHDL modules for your project, you can easily examine the hierarchy of each module and see the relationships between design units found within those modules. To examine the hierarchy of the project: 1. Make the Hierarchy Browser the active window (by clicking within it, or on its title bar). 2. Choose File/Rebuild Hierarchy, or click the Rebuild Hierarchy button on the Hierarchy Browser toolbar. When Rebuild Hierarchy is invoked, all modules in the project are analyzed and a hierarchy tree is created. After the tree is created, you see small + icons appearing next to each VHDL module: You can use these + icons to examine the contents of a module, or you can use the Show Hierarchy button to expand and view the entire project hierarchy. When you examine the complete hierarchy for a module (either by repeatedly clicking on the + icons or by clicking once on the Show Hierarchy button), you see listed not only the design units that exist in the current module, but those that exist in other modules referenced from the current module as well. If you wish to examine the VHDL source file associated with any design unit listed in a module s hierarchy tree, double-click on the design unit name and the source file is loaded into the built-in source file editor of MultiVHDL. This editor (shown MultiVHDL 8 User Guide 2-7

47 VHDL Simulation below) is a full-featured text editor, and includes features such as search and replace, and keyword coloring editing features. Note If you prefer to use your own text editor, you can specify an alternate source file editor in the System Options dialog box. Although you can edit and compile VHDL modules without first rebuilding the project hierarchy, you will not be able to link or load a module for simulation, without first bringing the project hierarchy up-to-date. In addition, you should keep in mind that the project hierarchy is not updated automatically as you modify your project. You should therefore be sure to rebuild the hierarchy any time you make a change to the project that might affect the hierarchy of the project. Changes that can affect the hierarchy include: adding or removing VHDL modules changing compile library names adding or removing component references changing entity, architecture or component names modifying references to external packages. 2-8 Electronics Workbench

48 Using the Entity Wizard 2.3 Using the Entity Wizard The Entity Wizard is a MultiVHDL feature that allows you to quickly and easily create new VHDL modules and test benches. If you are familiar with writing VHDL source code, you do not need to use this wizard. Instead, you may simply begin design entry by clicking Create Blank Module from the New Module dialog box, entering a file name and typing your code in the resulting dialog box. However, even some VHDL experts find the use of the Entity Wizard a time-saver. If you will not be using the wizard, you can skip directly to Compiling a Module on page The Entity Wizard prompts you to enter a list of ports (input and output signals) describing the interface to your new design module, and from that list of ports automatically generates a template module or test bench. After the template module or test bench has been created, you can modify it to add the desired functionality and/or test stimulus. This section is a step-by-step tutorial designed to show you how the Entity Wizard can make the creation of new design modules fast and easy. Before beginning this tutorial, you should create a new, empty project as in Creating a Project File on page Invoking the Entity Wizard To create a VHDL module using the Entity Wizard: 1. Choose File/New Module, or click the Create New Module button on the toolbar to display the New Module dialog box. MultiVHDL 8 User Guide 2-9

49 VHDL Simulation 2. Click Module Wizard to display the Entity Wizard dialog box. Note For details on the other buttons in the New Module dialog box, see 2.4 Using the Test Bench Wizard on page 2-17; 3.1 Creating a New Waveform Testbench on page 3-1; 4.2 Creating a New State Machine on page 4-3; Creating a VHDL Module on page Specifying the Port List The Entity Wizard generates a template VHDL source file based on the I/O specification (the port list) that you provide. Entering your I/O is easy: just enter the port names, one at a time, along with their direction (or mode, in VHDL jargon) and type. The Entity Wizard helps you by providing commonly-used modes and types in drop-down selection lists, and by checking to make sure the names that you enter are valid VHDL identifiers. If you are new to the VHDL programming language, see VHDL Primer on page 5-1. For this tutorial example, we will create a simple shift register that accepts 8-bit data, and shifts (rotates) this data one bit position on the next rising edge of the clock. To describe the top-level entity and interface to this sample design in the Entity Wizard: 1. Enter the name of the new module (its VHDL entity name) in the Entity Name field. 2. Enter the name of the new module s architecture in the Architecture Name field, or simply leave the field with its default value (behavior) Electronics Workbench

50 Using the Entity Wizard 3. Use the Port Name, Mode and Type fields to add port declarations for each of the inputs, as shown below. Be sure to select the correct mode ( in or out ) for each port as shown. Click Add Port to add each port (line) to the Port declarations list. As you enter the ports, you can make changes to them at any time by clicking in the Port declarations area. For example, you will probably want to edit ports that are array types to give them valid ranges as shown in the screen capture above. When modifying items within the Port declarations area, keep the following rules in mind: Each entry in the port list, with the exception of the last entry, must be terminated by a semicolon. There must be only one entry (port identifier) on each line; do not attempt to combine multiple port names on a single line. If you make use of IEEE standard logic data types (including std_logic, std_ulogic, std_logic_vector and std_ulogic_vector), you must make sure the Use IEEE 1164 standard logic option is selected. After you have entered all the ports for your design (and have verified that they have the desired modes and types), you are ready to create the new module and save it to a file. 4. Click Create in the Entity Wizard dialog box. You are prompted for a file name (typically a.vhd file). 5. Enter a name, or accept the default file name (in this case SHIFTER.VHD). MultiVHDL 8 User Guide 2-11

51 VHDL Simulation MultiVHDL saves your new module to the specified file and adds a reference to the file to your project, as shown below Adding Functionality to a Module After the Entity Wizard of MultiVHDL has created your module, you must edit the module to add the appropriate functionality. MultiVHDL makes the process easier by generating sample code, and by inserting comments to help guide you as you modify your VHDL code. Because most new VHDL modules you create will include at least one registered element, the Entity Wizard inserts sample VHDL code and comments showing you how to write a synthesizable register element, with a suggested (synthesizable) style for describing the clock and reset logic. For example, the following VHDL source code was generated by the Entity Wizard from the port specifications described in the previous section: Auto-generated module template: SHIFTER -- Note: comments beginning with WIZ should be left intact. Other comments are informational only. library ieee; use ieee.std_logic_1164.all; 2-12 Electronics Workbench

52 Using the Entity Wizard -- use ieee.numeric_std.all; use ieee.std_logic_arith.all; -- entity SHIFTER is port ( -- WIZ BEGINPORTS (Entity Wizard command) Clk: in std_logic; Reset: in std_logic; Data_in: in std_logic_vector(7 downto 0); Shift: in std_logic; Data_out: out std_logic_vector(7 downto 0) -- WIZ ENDPORTS (Entity Wizard command) ); end SHIFTER; architecture BEHAVIOR of SHIFTER is -- Note: signals, components and other objects may be declared here if needed. begin -- Sample clocked process (synthesizable) for use in registered designs. -- Note: replace _RESET_ and _CLOCK_ with your reset and clock names as appropriate.(delete this process if the design is not registered.) P1: process(_reset_, _CLOCK_ ) -- Note: variables may be declared here if needed. begin if _RESET_ = '1' then -- Registers are reset here. Be sure you include reset values for all signals that are assigned logic in the process. elsif rising_edge(_clock_) then -- Note: registered assignments go here. Remember that signal assignments do not take effect until the process completes. end if; end process P1; -- Note: concurrent statements (including concurrent assignments and component instantiations) go here. end BEHAVIOR; MultiVHDL 8 User Guide 2-13

53 VHDL Simulation This template source code can be quickly and easily modified to described the desired function (a shifter). The exact changes needed for this template source code are: The template s dummy clock and reset signals (_CLOCK_ and _RESET_) must be replaced with the actual clock and reset lines for the design (Clk and Reset, in this example). Reset assignments must be added (after the first "if" statement). The clocked operation of the design must be described, using whatever VHDL statements are appropriate. Concurrent statements (such as combinational assignments or component instantiations, if any) must be entered where indicated. Continuing with the shifter example, we now modify the template source code to describe our shifter as follows: Auto-generated module template: SHIFTER -- Note: comments beginning with WIZ should be left intact. Other comments are informational only. library ieee; use ieee.std_logic_1164.all; -- use ieee.numeric_std.all; -- use ieee.std_logic_arith.all; entity SHIFTER is port ( -- WIZ BEGINPORTS (Entity Wizard command) Clk: in std_logic; Reset: in std_logic; Data_in: in std_logic_vector(7 downto 0); Shift: in std_logic; Data_out: out std_logic_vector(7 downto 0) -- WIZ ENDPORTS (Entity Wizard command) ); end SHIFTER; architecture BEHAVIOR of SHIFTER is -- Note: signals, components and other objects may be declared here if needed. begin -- Sample clocked process (synthesizable) for use in registered designs Electronics Workbench

54 Using the Entity Wizard P1: process(reset, Clk ) begin if Reset = '1' then -- Registers are reset here. Data_out <= (others => 0 ); elsif rising_edge(clk) then -- Note: registered assignments go here. if Shift = 1 then Data_out <= Data_in(6 downto 0) & Data_in(7); else Data_out <= Data_in; end if; end if; end process P1; end BEHAVIOR; For more complex (and realistic) designs, you will need to make many such changes and additions to achieve the desired functionality Compiling a Module After you have modified your new module, you will need to compile it to verify that you have entered your VHDL statements correctly. To compile the file: 1. Select your new module by highlighting its entry in the Hierarchy Browser, as shown below. 2. Choose Simulate/Compile Selected, or click the Compile button on the toolbar. MultiVHDL 8 User Guide 2-15

55 VHDL Simulation Note The Transcript dialog appears, displaying any error messages: Note Depending on the number of syntax errors you have introduced during your editing session, you may need to compile the module more than once. Refer to 2.5 Using Simulation on page 2-22 for more details about finding and fixing syntax and other errors. See also Error Message Dialog on page Error Message Dialog To display the Error Message dialog box: 1. Select an error in the Transcript dialog box and click on the Error Summary button. Click to jump to the line in the module where the error is located 2-16 Electronics Workbench

56 Using the Test Bench Wizard Updating (Rebuilding) Your Project Hierarchy After you have successfully compiled your new module, and any time you make a change to it (or any other file) that might affect the hierarchy of your design, it is important to update the information in the Hierarchy Browser by rebuilding the project. To rebuild your project, click the Rebuild Hierarchy button on the Hierarchy Browser toolbar. After you have rebuilt the project hierarchy, you can view the hierarchy for your new module by clicking on the small plus sign icon to the left of the module name, or by clicking the Show Hierarchy button to expand the hierarchy for the entire project. 2.4 Using the Test Bench Wizard Before processing a module for simulation, you will need to provide MultiVHDL with a test bench. Test benches are VHDL modules that provide input stimulus (and, if desired, output value checking) for VHDL modules that are to be simulated. There are many ways to write test benches (and you can examine many different test bench styles by perusing MultiVHDL s samples folder), but nearly all VHDL test benches have the following in common: They have an entity declaration with no input or output ports. They have one or more component declarations describing the interface to the VHDL module being tested (called the unit under test, or UUT). They have a series of signal declarations defining local (top-level) signals onto which input values can be assigned, or from which output values can be observed. They have one or more component instantiations corresponding to the modules being tested. These component instantiations connect the local signals of the test bench to the corresponding ports of the unit under test (UUT). They have one or more process statements describing the sequence of inputs applied to the UUT, and the tests to be performed (if any) on the UUT outputs. Writing a test bench that includes all of these elements is not difficult, but it can be tedious if the module being tested has many input and output ports. MultiVHDL 8 User Guide 2-17

57 VHDL Simulation The Test Bench Wizard helps by automatically generating a basic framework of a test bench, and reduces typing errors by automatically filling in such things as port lists, component declarations and component instantiations. The Test Bench Wizard also generates a sample process for a background clock, and generates informative comments that guide you as you develop your test stimulus. Just as with the Entity Wizard, it is not required that you use the Testbench Wizard to generate a testbench for your VHDL module. However, even if you choose not to use the Testbench Wizard, you must generate a testbench if you want to simulate the VHDL module. As a result, if you do not use the wizard, you need to write the source code yourself, after clicking Create Blank Module on the New Module dialog box Invoking the Test Bench Wizard To create a new VHDL test bench using the Test Bench Wizard: 1. Select (by highlighting) the VHDL module that this test bench will be referencing. For example, select module SHIFTER.VHD. For a design with multiple VHDL modules, select the top-level module in your project s hierarchy, unless you are creating a test bench that is intended to test only one component of the design. 2. With the module to be tested highlighted in the Hierarchy Browser, choose File/New Module, or click the New Module button on the toolbar to display the New Module dialog box. 3. Click Test Bench Wizard (text) to display the Testbench Wizard (text) Electronics Workbench

58 Using the Test Bench Wizard Verifying the Port List When the Test Bench Wizard is invoked it examines the port list of the module that you have selected (in this case SHIFTER.VHD) and attempts to fill in the port declarations edit box for you, as shown below. All you need to do is verify that all of the ports have been listed along with their correct direction and type. To complete the test bench: 1. Examine the port declarations to ensure they match the declarations shown and click Create. Tip If you are generating a test bench for a module that was not created using the Entity Wizard, you may need to manually enter the port list. You can save time by pasting text copied from an editor window. 2. When prompted, enter a name for the new test bench module, or accept the default name (in this case TEST_SHIFTER.VHD). MultiVHDL 8 User Guide 2-19

59 VHDL Simulation Your new test bench module is now complete, and is displayed as shown below Modifying the Test Bench This test bench template source code must be modified to describe the desired test stimulus. The exact changes needed to this template will depend on how extensively you want to test the design. To create a simple test sequence for this shifter, make the following modifications to the source code: 1. In process Clock1, replace the template s dummy clock signal (_CLOCK_) with the actual system clock signal Clk. 2. In process Stimulus1, replace the assignments to _RESET_ so they instead refer to signal Reset. 3. Add some additional stimulus to this design as shown in the source file that follows. The sample stimulus assigns a value to signal data_in, then sets the shift input to 1. A subsequent wait statement will cause the simulation to move forward for some period of simulated time (in this case 100ns). Similar sequences of assignments and wait statements apply additional test inputs Electronics Workbench

60 Using the Test Bench Wizard CLOCK1: process variable clktmp: std_ulogic := 0 ; begin wait for PERIOD/2; clktmp := not clktmp; Clk <= clktmp; Attach your clock here if done = true then wait; end if; end process CLOCK1; STIMULUS1: process begin Sequential stimulus goes here... Sample stimulus... Reset <= 1 ; Reset the system wait for PERIOD; Wait one clock cycle Reset <= 0 ; de-assert reset Enter more stimulus here... Data_in <= ; wait for PERIOD; Shift <= 1 ; wait for PERIOD * 4; done <= true; Turn off the clock wait; Suspend simulation end process STIMULUS1; end stimulus; After you have made the above changes to your test bench template, save the module and compile it. To compile the module: 1. Highlight the test bench module in the Hierarchy Browser and click Compile on the toolbar. 2. After you have successfully compiled your new test bench, click Rebuild Hierarchy to bring the Hierarchy Browser display up-to-date. Your project is now ready for simulation. MultiVHDL 8 User Guide 2-21

61 VHDL Simulation 2.5 Using Simulation This section describes how you can use the built-in simulator features of MultiVHDL to verify your VHDL design projects. Note A testbench is needed to simulate a VHDL module (the testbench tells the simulator which stimulus to use). You must have a testbench for your design at this point. If you have been working through the example used in this chapter, you have already created a testbench. If you do not have a testbench, create one now, following the instructions in 2.4 Using the Test Bench Wizard on page Understanding Simulation Simulation of a VHDL design description using MultiVHDL involves three major steps: 1. Compiling the VHDL modules into an intermediate object file format. 2. Linking the object files to create a simulation executable. 3. Loading the simulation executable and starting the simulation. Each of these steps is represented by a toolbar button in MultiVHDL. If the dependency features of the application are enabled in the Compile tab of the Options dialog box (Compile only if out of date and Bottom-up to selected), the application checks the date and time stamps of files, and examines the hierarchy of your design to determine which files must be compiled and linked at each step. When a simulation executable has been successfully linked and loaded, the simulator interface appears and you are ready to start a simulation run. To help you understand this process, this section explains how to load and simulate the sample project developed in the previous sections. Note If you have not created a new project by following the example in this chapter, you can follow these steps using one of the standard examples provided with MultiVHDL in the samples folder. Note For details on the Compile tab of the Options dialog box, see Compiling Modules for Simulation on page Loading the Project To load the project: 1. Start MultiVHDL and choose File/Open Project Electronics Workbench

62 Using Simulation 2. Navigate to your project folder created in the previous tutorial and choose the MYPROJECT.ACC file. The project is loaded. If you are following the example, you see that there are two modules listed in the Hierarchy Browser (shown on the right side of the dialog box). These modules (TEST_SHIFTER and SHIFTER) are VHDL modules that you entered to describe the operation of the sample circuit. TEST_SHIFTER is a test bench for the circuit, while SHIFTER describes the function of the shifter circuit itself. You can examine or modify either of these modules by double-clicking on them to invoke a Source Code Editor window as described in Modifying the Test Bench on page The Hierarchy Browser does not provide any immediate indication of which module represents the top of your design. (The order of modules appearing in the Hierarchy Browser is not significant.) You may choose to select different top-level modules depending on whether you want to simulate just a portion of the circuit or simulate the entire circuit. You may also have more than one top-level test bench in your project. You can, however, display the hierarchy and file dependencies for any module displayed in the Hierarchy Browser by clicking on the + icons to the left of the module. The Hierarchy Browser is the point from which you initiate all processing of your design, from compiling and linking to simulation. MultiVHDL 8 User Guide 2-23

63 VHDL Simulation Compiling Modules for Simulation Before compiling this design, take a moment to examine the compile options that have been selected. To check compile options: 1. Highlight the module in the Hierarchy Browser. 2. Choose Options/Compile or click the Options button to display the Options dialog box and click on the Compile tab. For the module SHIFTER, the options should be set as shown below. The options set are: Bottom up to selected This option tells the compiler to examine the dependencies of the project, and to compile lower-level VHDL modules before compiling higher-level modules that depend upon them. Compile only if out of date This option enables the date and time stamp checking features so that modules are not compiled unless they are out of date. This can save time when you are compiling a large project repeatedly (such as when fixing syntax errors in higher-level modules). VHDL 93 This option enables VHDL language features. If this option is not selected, the compiler will accept only VHDL features. Compile Into Library This option specifies that the current module, SHIFTER, is to be compiled into a named library, in this case WORK. 3. Verify that the options are set to these values and click OK Electronics Workbench

64 Using Simulation Options not used for this example are: Selected file only Choose to compile only the selected VHDL module without compiling lower-level files. External ("use") libraries Enter the name(s) of any external libraries that are required to be made visible during analysis. This field can be used as an alternative to specifying "use libraryname.all;" in your VHDL source file. To enter multiple library names in this field, separate each library name with a space character. The next step is to compile the source modules. With the Bottom up to selected option selected, you have two choices: You can first compile the SHIFTER module, then compile the TEST_SHIFTER module. You can simply compile the TEST_SHIFTER module, and let the dependency features automatically compile the lower-level SHIFTER module. To use the second method to compile the two source files: 1. Highlight the TEST_SHIFTER module in the Hierarchy Browser and click the Compile button on the toolbar. During compilation, status and error messages are written to the Transcript dialog, as shown below. When compiled, each VHDL source file (module) in the project is processed to create an intermediate output file (an object file). These files, which have a.o file name extension, must be linked together to form a simulation executable. MultiVHDL 8 User Guide 2-25

65 VHDL Simulation Linking Modules for Simulation Before linking the modules, take a moment to examine the link options. To examine the link options: 1. Highlight the module TEST_SHIFTER in the Hierarchy Browser. 2. Choose Options/Link or click the Options button to display the Options dialog box and click on the Link tab. The options should be set as shown below: The options set are: Update object files before linking This tells the linker to examine the dependencies of the project, and to compile lower-level VHDL modules before linking. (If the Compile only if out of date option is specified in the Compile tab, only those source files that are out of date will be re-compiled.) Link only if out of date This option enables the date and time stamp checking features so that the modules are not re-linked unless the simulation executable is out of date. 3. Verify that the options are set to the values shown and click OK. Options not used for this example are: Top-level entity/configuration This options allows you to specify the default top-level entity for the link operation. To do so, type the entity name in the field. This field is ignored if you have selected an entity or architecture in the Hierarchy Browser prior to invoking the link process. Leave this field blank if you want MultiVHDL to use the default entity or configuration in the selected module. The default entity/configuration is the last entity or configuration in the module Electronics Workbench

66 Using Simulation Top-level architecture This option allows you to specify the default top-level architecture for the link operation. To do so, type the architecture name in the field. This field is ignored if you have selected an architecture in the Hierarchy Browser prior to invoking the link process. Leave this field blank if you want MultiVHDL to use the default architecture in the selected top-level entity. The default architecture is the last architecture appearing in the selected entity. SDF file name This option allows you to specify an SDF format file to be annotated onto a component instance in your design. This field should be used only if your project includes a VITAL-compliant timing model. See 2.9 VITAL Simulation Models on page 2-46 for more information about using SDF files. SDF instance path This option allows you to specify the which component instance in your design to which the specified SDF file is to be annotated. For example, if you are simulating a VITAL-compliant model that is referenced in your design as component instance DUT, you would enter the name DUT in this field. See 2.9 VITAL Simulation Models on page 2-46 for more information about using SDF files. SDF timing This option allows you to specify which data delay is to be used when annotating SDF timing data. When linking a project, the MultiVHDL linker collects all object files required for the selected top-level module, and combines these object files with any libraries you have specified in your design (such as the IEEE standard logic library) to create the simulation executable. To link your design and create a simulation executable: 1. Highlight the TEST_SHIFTER module in the Hierarchy Browser. 2. Click the Link button. MultiVHDL 8 User Guide 2-27

67 VHDL Simulation During the linking process, messages will be written to the Transcript dialog box, as shown below: The result of linking is a simulation executable file ready to be loaded for simulation Setting Simulation Options Before loading the simulation executable, take a moment to examine the simulation options. To examine the simulation options: 1. Make sure the TEST_SHIFTER module is still highlighted in the Hierarchy Browser. 2. Choose Options/ Simulate to display the Options dialog box and click on the Simulate tab. 3. The options should be set as shown below Electronics Workbench

68 Using Simulation The options set are: Update simulation executable before loading This option tells the simulator to examine the dependencies of the project and, if necessary, compile lower-level VHDL modules and re-link them before loading. Enable source-level debugging Enable to include source-level debugging. For details, see Understanding Source-Level Debugging on page Vector display format This option specifies how vector (array) data types should be displayed. Run to time and Step value These fields allow you to specify a default amount of time that the simulation should run. These values can be changed during simulation if necessary. Time unit This field specifies the unit of time (e.g. ns, ps) to be used during simulation. Max signal depth This field specifies the depth of signals to be loaded for into the Available Objects list in the Select Display Objects dialog box. The depth of a signal is determined by its position in the design hierarchy. For example, a signal DUT.Clk has a signal depth of 2, while signal DUT.U1.ControlSM.Var1 has a depth of 4. You can use this option to reduce the number of signals and speed simulation loading when simulating large structural models. 4. Verify that the options are set to the values shown and click OK System Options To set system options: 1. Select Options/System. The following dialog displays: MultiVHDL 8 User Guide 2-29

69 VHDL Simulation 2. Set the following as desired: Save options as default - the currently specified system options will be saved to the Windows Registry when you exit the program. Save files before running - all open text files will be saved before compiling, linking, or simulating. Clear transcript before running - clears any existing entries in the Transcript dialog box. Show Tips - tips will appear in various windows and displays, including the Transcript Window, the Module and Test Bench Wizards, the various Options dialogs, and the Hierarchy Browser. Small toolbars - enable to display small toolbuttons. Error limit - the maximum amount of errors permitted before either a compile or link action will be terminated. Use built-in editor - a built-in text editor will be invoked when modules are created and/or edited. If you use this option, you can also select Standard tabs, Auto indent, Tab Size and Set Font as desired. Use external editor - the specified external text editing program will be invoked (instead of the built-in text editor) when modules are created and/or edited. To specify an external editor, click on Use external editor to select this option. Then type in the full name and path of the editor (e.g., c:\editor\edit.exe) in the adjacent field. Note: If you specify an external editor, you will have to manually save files that you are editing prior to compiling or synthesizing. When selected, your selected text editor will be invoked with the currently selected VHDL (or other) file name as the program argument when you view or edit a file from within MultiVHDL. If your editor can accept (or requires) a more complex command line, you can include the command line in the editor text entry box along with the program name. Two special fields (%f and %l) are provided to allow you to insert the file name and line number in your editor's command line as appropriate. For example, to invoke the ED for Windows editor and include both the file name and line number on the command line, you would enter the following editing command into the external editor text entry field: c:\ed4w\ed4w.exe %f -l %l The %f and %l fields will be replaced by the file name and line number of the currently selected entry whenever you view or edit a file from within MultiVHDL. System Library Path - specifies the path the program uses when searching for simulation libraries during compile and link operations. To change or add to an entry, click on the System Library Path field and type the appropriate path. Please note the following: 2-30 Electronics Workbench

70 Using Simulation The current directory is always searched before the path you specify. You can specify multiple directory names in the System Library Path field. When entering multiple directory names, you must separate the directory names with a semicolon. 3. Click Close. Tip System options set in the System tab are not saved with your project. To save options as system defaults after exiting, check the Save Options as Default box Loading the Simulation Executable At this point, you have compiled each of the VHDL modules into an object file format, and have linked all of the object files to form a simulation executable. To start the simulation process, you will use the Load Simulation button. To load the simulation executable: 1. Make sure the TEST_SHIFTER module is selected in the Hierarchy Browser: 2. Click the Load Simulation button. The simulation executable is loaded and the Select Display Objects dialog box appears. MultiVHDL 8 User Guide 2-31

71 VHDL Simulation Select Display Objects Dialog This dialog box allows you to choose signals to observe during simulation. To select signals to observe in simulation: 1. Use the Add Primaries button to move the top-level signals from the Available list to the Object to Display list. Or Highlight individual signals in the Available Objects list and use the Add button to move individual signals to the Objects to Display list. 2. Use the Up and Down buttons to rearrange signals, putting them in any display order you wish. The screen capture below shows the Select Display Objects dialog box with some of the design s signals selected for display: Tip Use the Save Objects button to save the list of selected objects. This is a useful timesaver if you repeat the same simulation many times during the development of your project. To load a previously saved list, click Load Objects Electronics Workbench

72 Using Simulation 3. When you are satisfied with the selected signals, click Close to close the dialog box and prepare the simulation. The simulator interface appears. 4. Optionally, select Simulation/Options to display the Simulation Options dialog box, where you can make adjustments as desired. MultiVHDL 8 User Guide 2-33

73 VHDL Simulation Transcript Dialog During compilation and linking, status and error messages are written to the Transcript dialog box. To display an error message related to a specific error, select an error in the dialog and click Error Summary. The Error Message dialog box will display. Note For details, see Error Message Dialog on page The Compile tab of the Transcript dialog shows any errors that occur when a module is compiled. The Link tab of the Transcript dialog shows any errors that occur when modules are linked. The Simulate tab of the Transcript dialog shows any errors that occurs when you select Simulate/Load Selected. The System tab of the Transcript dialog shows any system errors that occur Starting a Simulation Run To start simulation using the previously-specified example: 1. Click Simulation/Go to simulate this project. The resulting waveform should look similar to that shown below. 2. Use the Zoom In button and the horizontal scroll bar to change the display range as shown. Note Simulation runs until either the specified simulation end time (duration) has been reached or all processes in your project have suspended Electronics Workbench

74 Working with the Simulator Interface 2.6 Working with the Simulator Interface MultiVHDL s simulator interface offers a variety of features for examining waveform results, saving and printing waveforms and measuring times between events. Source File Selection Box Waveform Display Object Display Pane Transcript Pane Source Level Display Pane (Debugging) To quickly pan across a dense (zoomed out) waveform and observe values, move the mouse pointer over the waveform display and observe the changing values displayed in the signal display area (the small window to the left of the waveform). The Waveform Display also includes selectable cursors that can be used to accurately measure the distances between events, and to view the timing relationships between events on different signals. To add a cursor to the Waveform Display, click within the Waveform Display area. A new cursor is displayed each time you click. When you add multiple cursors, MultiVHDL adds a measurement line and value allowing you to quickly determine the time between two or more events. To delete the cursors you have placed, choose View/Remove All Cursors. Other Options: File/Save Waveform - Clicking this button opens a Save As dialog box, allowing you to save the current simulation results as a waveform data file. This is the same as the File / Save Waveform As... option in the menu bar. File/Zoom In - Clicking this button magnifies the display for a closer look at the waveform MultiVHDL 8 User Guide 2-35

75 VHDL Simulation File/Zoom Out - Clicking this button demagnifies the display to show the "big picture." Restart Simulation - Click this button to reload the simulation executable. This button is the same as the Simulation/Restart option in the menu bar. GO - Click this button to start the simulation. The simulation will proceed until the specified Run to time value (see Simulation/Options) has been reached. This button is the same as the Simulation/Go option in the menu bar. STOP - Once you have clicked on the GO button and the simulation is running, a STOP button appears. To stop the simulation, click this button. This button is the same as the Simulation/Halt option in the menu bar. STEP - Clicking the STEP button advances the simulation time by the value specified in the Step time field (see Simulation/Options) and continues the simulation to that time value. This is useful for advancing simulation by a fixed incremental amount, such as a single clock cycle. Single-Step Into - Clicking this button advances the simulation by one source file line. If the current source file line is a subprogram call, the simulator will step into the subprogram. Single-Step Over - Clicking this button advances the simulation by one source file line. If the current source file line is a subprogram call, the simulator will step over the subprogram call to the next line in the current file. Source File Selection Box - Use to specify a file to be displayed in the Source Level Display Pane. You can use this feature when setting or removing simulation breakpoints. Waveform Cursors - The Waveform Display window has measurement cursors that can be used to measure the distance between events in the waveform. To add a cursor, simply click your mouse in the Waveform Display. A cursor and time mark will appear. You can add as many as eight different cursors to a waveform in this way. To remove a cursor, simply click on the cursor a second time. To remove all cursors from the display, select View/Remove All Cursors. To set or remove a breakpoint, double-click on a source file line in the Source Level Display Pane. The Transcript Pane collects and displays messages generated during simulation, including text I/O messages and assert statement outputs are also written to the transcript window. 2.7 Using the Debug Window MultiVHDL includes a powerful feature called source-level debugging that allows you to observe how your VHDL design is being executed during simulation. Using this feature, you will be able to step through your VHDL code, set breakpoints, and more easily find and fix problems in your VHDL design description Electronics Workbench

76 Using the Debug Window Understanding Source-Level Debugging The source-level debugging pane allows you to follow the execution of your VHDL design at the level of VHDL source file statements. This is useful for debugging complex sequential statements, determining the order in which statements are processed, and understanding the impact of scheduling, delta cycles and other complex aspects of model execution. To allow source-level debugging to be performed, the MultiVHDL linker must insert certain pre-compiled code statements into your simulation executable. These statements are not visible, but you may notice your compiled VHDL projects require more disk space after linking with source-level debugging enabled. During simulation of your design, MultiVHDL keeps track of which VHDL source file lines are related to the currently executing compiled and linked code, and displays the appropriate VHDL source file in a source file display window. In addition, MultiVHDL maintains a list of breakpoints that you have requested and stops the simulation whenever one of these break points is encountered. It then waits for you to either continue the simulation using the Go or Step Time buttons, or single-step through your code using the Step Over or Step Into buttons. Whenever the simulator stops at a break point or is stepped to a new line in the VHDL source file, the waveform window is updated to display the current values of all selected signals. This feature allows you to observe the order in which signals and variables are updated in your design, and allows you to (for example) determine when you have incorrectly specified a signal or variable assignment A Sample Project To give you a better understanding of source-level debugging, a sample project will be presented so you can see how it is compiled and run. You can follow along with this example by first opening the MultiVHDL standard example getpizza, which can be found in the samples folder of your MultiVHDL installation folder. The getpizza example project is intended as an exercise in writing test benches, and is also useful for demonstrating the concepts of source-level debugging. At the center of getpizza is a driving game that was inspired by the ChipTrip example first described by Altera Corporation using their AHDL PLD language. In this version of the design (which is described in more detail in VHDL Made Easy, published in 1996 by Prentice Hall), the objective is to create a sequence of test inputs that will cause an imaginary engineer to proceed from his office to the beach, as quickly as possible, without getting a speeding ticket. To make the trip more interesting, our hero must stop and pick up a pizza on the way. There are three different types of roads: freeways, commercial streets, and residential roads. The car being driven has only two possible speeds: fast and slow. When the car is driven slowly, it advances from one point on the map (say, from Ramp1 to Ramp2) in a given period MultiVHDL 8 User Guide 2-37

77 VHDL Simulation of time. When driven fast, the car proceeds twice as far. There is no speed limit on the freeway, so the car can travel at full speed without fear of getting a ticket. On commercial streets, the car may exceed the speed limit just once and get away with it. On residential roads, any attempt to drive fast will result in a ticket. In our simulation, and in the underlying design description, a fixed period of time is represented by a single clock cycle. Inputs for the speed and initial direction of travel are represented by signals Speed and Dir. The location of the car at any point is represented internally to the circuit by a state machine, but it is kept hidden at the top level of the design and in the test bench itself. The current status and success or failure of a trip are observed on the signals DriveTime, Tickets, and Party, which tell the player how long the drive has taken, how many traffic tickets have accrued, and whether he or she has yet arrived at the beach with the pizza. (The VHDL source files and the MultiVHDL project file for the entire design can be found in your samples\getpizza folder.) The test bench for this design reads symbolic test commands from a file, allowing the game to be easily tested and various driving scenarios to be described without having to re-compile the design each time. Loading the Sample Project To load the sample project: 1. Invoke MultiVHDL and choose File/Open Project or click the Open Project button. 2. Navigate to the samples\getpizza folder and select the GETPIZZA.ACC project file. After you have opened the project, you will see that there are four VHDL modules listed in the Hierarchy Browser. (You can invoke the text editor to examine these source files if you wish. To invoke the text editor, double-click on any entry in the Hierarchy Browser.) 2-38 Electronics Workbench

78 Using the Debug Window The TSTPIZZA module describes the test bench for this project, so select that module by clicking once on the MODULE TSTPIZZA.VHD entry in the Hierarchy Browser: Setting the Project Options Before processing this project for simulation, we ll need to set certain project options to enable source-level debugging. To set these options: 1. Choose Options/Link or click the Options button from the toolbar and select the Link tab. 2. Set the options as shown below: MultiVHDL 8 User Guide 2-39

79 VHDL Simulation The important link option being set for this example is Enable source level debugging. This option causes debugging code to be added to the compiled and linked simulation executable. Loading the Simulation Our sample project is now ready for simulation. To load this project for simulation: 1. Select (highlight) MODULE TSTPIZZA entry in the Hierarchy Browser. 2. Click the Load button, or select Load Selected from the Simulate menu. Before loading the project, MultiVHDL compiles all VHDL modules and links them to create a simulation executable. After the simulation executable has been loaded, MultiVHDL displays the Signal Display Objects dialog box, allowing you to select signals for display. To select signals: 1. Use the Available Objects list to select some or all of the signals in the design, or click Add Primaries to select all top-level signals in the design Electronics Workbench

80 Using the Debug Window 2. Click Close to display the following: Setting a Break Point You can set or remove breakpoints before starting the simulation, or at any time the simulation is stopped. Before starting a simulation run, set a break point in the pizzactl module. To set the break point: 1. Use the drop-down list box to select the PIZZACTL.VHD module. MultiVHDL 8 User Guide 2-41

81 VHDL Simulation 2. Scroll through the pizzactl module and find the source file line shown below: 3. Set a break point at the indicated line number by double-clicking or choosing Simulation/Toggle Breakpoint. Running Simulation you can now start the simulation and let it run to the selected break point. To start the simulation, click the Go button or select Simulation/Go. The simulation executes until it encounters the breakpoint that you have selected, or until it reaches the specified simulation end time if no breakpoint is encountered. It then stops execution and displays the current module and source file line in the source file display window. It also updates the waveform display so you can see the current values of all signals and variables being displayed. At this point you could single-step the design to view exactly how the state machine represented by this section of code operates, or click the Go button to continue to the next breakpoint (or to the specified simulation end time, if there are no more breakpoints set) Electronics Workbench

82 Using the Debug Window To single-step the simulation, click the Step Over button repeatedly until the current line pointer (the green arrow icon) is at the position shown below. The simulation is now stopped at a source file line that includes a call to a procedure named Drive. This procedure is defined elsewhere in the module (at the top of the architecture). You can use the Step Over button at this point to continue to the next line in the file, or use the Step Into button to cause the simulation to enter the Drive procedure and stop at the first line in that procedure. Try setting other breakpoints in the source files and continue the simulation (using the Go button) to get a feel for source-level debugging. Summary This tutorial has shown how source-level debugging can be used to examine the execution of a VHDL design with more precision than is possible using only waveforms. When you combine source level-debugging with the waveform display and export features of MultiVHDL, and the text I/O features of VHDL, you have a powerful set of debugging tools at your disposal. MultiVHDL 8 User Guide 2-43

83 VHDL Simulation 2.8 Using the Command Entry dialog box The Command Entry dialog box accepts text commands as an alternate method of controlling simulation. To access the Command Entry dialog box: 1. Select Window/Command Window from the simulator interface. Or Enable the Command window option in the Simulation/Options dialog and restart the MultiVHDL simulator. The following commands are supported: BP <filename> <linenumber> The BP command causes a breakpoint to be set at the specified file and line number. CHANGE <variablename> <value> [,<variablename> <value>...] The CHANGE command causes the current value of one or more specified variable(s) to be overwritten with a new value. This command is useful for interactive debugging. The CHANGE command does not schedule an event, and therefore should not be used to change the values of signals. To set the value of a signal, use the FORCE command described below. Variable values specified in the <value> field may be entered either as single-bit values (such as '1', '0', 'X') or as multibit arrays (such as " " or x"f2"). Binary, octal and hexadecimal formats are supported for arrays. The wildcard characters '*' and '?' may be used when specifying signal names. Note User-defined enumerated types, record types and other complex types are not currently supported in the CHANGE command. DESCRIBE <signalname> [,<signalname>...] The DESCRIBE command displays information about one or more specified signal(s). The signal data type information for the specified signal (or signals) is displayed in the transcript window. The wildcard characters '*' and '?' may be used when specifying signal names. DO <filename> The DO command causes the specified file to be loaded as a command file. Commands within the command file are executed in sequence, one file line at a time Electronics Workbench

84 Using the Command Entry dialog box EXECUTE <filename> The EXECUTE command causes the specified file to be loaded as a command file. Commands entered in the command file are executed in sequence, one file line at a time. This command is synonymous with the DO command. ECHO <text> The ECHO command causes a text message to be displayed in the transcript window. This command is useful when you are creating command files. FIND <signalname> [,<signalname>...] The FIND command displays all signals that match the specified pattern(s). The matching signals are displayed in the transcript window. The wildcard characters '*' and '?' may be used when specifying signal names. FORCE <signalname> <value> [<time>] [,<signalname> <value> [<time>]...] The FORCE command causes the current value of one or more specified signal(s) to be overwritten with a new value at a specified absolute time. This command is useful for interactive debugging, and for quickly testing a small VHDL module without the need for a test bench. Signal values specified in the <value> field may be entered either as single-bit values (such as '1', '0', 'X') or as multibit arrays (such as " " or x"f2"). Binary, octal and hexadecimal formats are supported for arrays. The wildcard characters '*' and '?' may be used when specifying signal names. Time values entered in the FORCE command are absolute (not relative) times specified in the time unit currently in effect. If no time unit is specified, the signal will be assigned the new value at the conclusion of the current simulation delta cycle. Note User-defined enumerated types, record types and other complex types are not currently supported in the FORCE command. NOWAVE <signalname> [,<signalname>...] The NOWAVE command removes one or more signals from the Waveform Display. The wildcard characters '*' and '?' may be used when specifying signal names. MultiVHDL 8 User Guide 2-45

85 VHDL Simulation RESTART The RESTART command causes the simulator to reset to time zero and clear all events. Use this command to restart simulation from the beginning. RUN [<time>] The RUN command causes the simulation to advance by the specified number of time units. You should select one or more signals to display before executing this command. If no time value is specified in the RUN command, the simulation will advance to the Run To Time specified in the Options dialog. STEP [-Over] [<value>] The STEP command causes the simulation to be advanced by one or a specified number of source file lines. By default, the STEP command will step into functions and procedures that are encountered on the current source file line. The -Over flag can be used to cause the simulator to step over functions and procedures without entering them. WAVE <signalname> [,<signalname>...] The WAVE command adds one or more signals to the Waveform Display. The wildcard characters '*' and '?' may be used when specifying signal names. 2.9 VITAL Simulation Models MultiVHDL includes support for VITAL-compliant models annotated using SDF (standard delay format) files. VITAL (IEEE Standard ) is a standard method for annotating timing information onto a VHDL simulation model. VITAL is commonly used by FPGA vendors to annotate post-route timing information onto an automatically-generated FPGA simulation model. To simulate VITAL-compliant FPGA models, including those that include standard delay format (SDF) data files, you must perform the following steps: 1. Generate a Post-route FPGA Model - The first major step in the simulation of an FPGA design is to generate a post-route model of the design. The method used to generate this model will depend on the FPGA device you are using, and on the features of the FPGA place-and-route software. Refer to your FPGA place-and-route software for details of how to generate the post-route model Electronics Workbench

86 VITAL Simulation Models The results of FPGA model generation should be a VHDL model (a file with a.vhd,.vho or other similar file name extension), and a standard delay format timing data file (a file with an.sdf file name extension). 2. Create an FPGA Vendor-specific Primitive Library - The second major step in simulating an FPGA is to create a vendor-specific library corresponding to the VITAL primitives supplied by your FPGA vendor. This step only needs to be performed once for each FPGA device family you will be using, if you use the following suggested method. When using VITAL primitive libraries supplied by FPGA vendors, we suggest you compile these libraries in a common place, such as in a sub-directory of the..\ieee93 section of the MultiVHDL installation area. Doing so will save disk space, and will prevent unwanted (and time-consuming) recompiles of the primitive libraries. To compile a VITAL primitive library: Create a new MultiVHDL project and save that project in a subdirectory of the..\ieee93 sub-directory. For example, if you are compiling VITAL primitive libraries supplied by Xilinx, you might save the new project as..\ieee93\xilinx\vitalprims.acc. Copy the VITAL primitive library source files provided by your FPGA vendor to the new directory. For example, the Xilinx primitive library source files are named SIMPRIM_VITAL.VHD, SIMPRIM_VPACKAGE.VHD, and SIMPRIM_VCOMPONENTS.VHD. Copy these three files to the XILINX subdirectory you created above. Use the File/Add Module menu item to add the VITAL primitive source files to your new project. Set the library name for each module (in the Compile tab of the Options dialog) to the name specified by your FPGA vendor. For example, Xilinx specifies a library name of SIMPRIM, so you would specify SIMPRIM in the Compile Into Library field. Compile each of the modules, save the project and exit MultiVHDL. 3. Set Simulation Options for Your Project - After you have created your FPGA vendorspecific library, you must import your post-route model into your original MultiVHDL project and set the appropriate simulation options. In MultiVHDL, all VITAL-related features are controlled from within the Link tab of the Options Dialog. The options are as follows: SDF file name - Enter the name of the SDF timing data file to be back-annotated. If this field is blank, no SDF file will be back-annotated and the delays will be 0. SDF instance path - Enter the instance name of the VITAL-compliant model that is to be annotated with the time values in the SDF file. If your test bench references the timing model with an instance name of U1, for example, enter U1 in this field. SDF timing - Specify if you wish the timing to be annotated using the Min, Avg or Max value from the SDF file. MultiVHDL 8 User Guide 2-47

87 VHDL Simulation 4. Before compiling and simulating a VITAL timing model (such as one generated by FPGA place-and-route software), be sure to add the new library directory to the System library path field in the System tab of the Options dialog. For the above example, your Library Path field would specify: <installation_directory>\ieee93;<installation_directory>\ieee93\xilinx, where <installation_directory> is replaced by the appropriate installation directory path name. Your project is now ready for normal simulation processing Using MultiVHDL LIB MultiVHDL s VLIB is a utility that you can use to createmultivhdl s VHDL libraries and add or delete references to compiled VHDL modules (in the form of.an files) from within existing library files MultiVHDL s LIB Overview MultiVHDL s VLIB is a DOS (command line) application that has been provided for MultiVHDL library creation and maintenance. MultiVHDL library files (.LIB files) are created for you automatically when you specify a library name in the Compile tab of the Options dialog box and compile a VHDL source file from within MultiVHDL. (If you have not specified a library file, the default library name of WORK is assumed.) This method of automatically creating libraries is fine for most projects, and is quite convenient because it allows you to associate library names with VHDL source files and have them automatically compiled into the correct library every time. There are a few limitations inherent in creating libraries from within MultiVHDL, however: MultiVHDL includes path (drive and folder) information in.lib files that it generates. This makes it impossible to move existing projects to different drives or directories without recompiling the project, and makes library files essentially non-portable. MultiVHDL does not provide any way to move existing.an files from one library to another without recompiling the VHDL source file. In some cases (such as when you have purchased proprietary simulation models) you might not have access to the original VHDL source code. MultiVHDL does not provide any way to remove a library entry from an existing library. For example, you may need to remove and replace entries in the IEEE library provided with MultiVHDL if you are using other VHDL tools that have specific requirements for IEEE library contents Electronics Workbench

88 Using MultiVHDL LIB Examining the Contents of a Library File MultiVHDL library files (.LIB files) are ASCII text files (with the exception of the first two characters in the file) and can be examined using any text editor, including the text editor provided in MultiVHDL. Each line of the library file includes a reference to a specific design unit located in the library and a corresponding reference to a compiled VHDL source file (an.an file). The information in the library file is used by the MultiVHDL analyzer and elaborator (during the compile and link processes) to locate and use externally-referenced design units such as packages, components and lower-level entities Adding a.an File to a Library You can use MultiVHDL s VLIB to add a reference to an existing.an file (compiled VHDL module) to a library file. If the library you specify does not already exist, it will be created. To add an object file to a new or existing library: 1. Open a DOS window and change the directory so that you are in the folder that contains vlib.exe. 2. Type the command: vlib c:\vhdl\ieee93\<libname> c:\vhdl\ieee93\<filename> where libname is the name of the library (such as IEEE.LIB), and filename is the name of a compiled VHDL module (such as TEST.AN). Sample filepaths to the libname and filename are shown above (c:\vhdl\ieee93\). Update these as required. 3. Press ENTER on your keyboard. The command is executed as in the following example: MultiVHDL 8 User Guide 2-49

89 VHDL Simulation Deleting a.an File Reference from a Library To delete a reference to an object file from an existing library, use the -d command as shown below: 1. Open a DOS window and change the directory so that you are in the folder that contains vlib.exe. 2. Type the command: vlib -d c:\vhdl\ieee93\<libname> c:\vhdl\ieee93\<filename> where libname is the name of the library (such as IEEE.LIB), and filename is the name of a compiled VHDL module (such as TEST.AN). Sample filepaths to libname and filename are shown above (c:\vhdl\ieee93\). Update these as required. Note The -d command must be typed in lower case. 3. Press ENTER on your keyboard. The command will be executed as in the following example: 2.11 MultiVHDL Menu Items File Menu New Project - closes the currently open project and creates a new, empty project. Open Project - allows you to open a project. Project files have a.acc file extension. Note that all files related to a project (.VHD,.ACC, etc.) are assumed to be in the same directory. Close Project - closes the currently open project. Save Project - saves the current project (and any associated open files). Note that the project is saved to a.acc file Electronics Workbench

90 MultiVHDL Menu Items Save Project As - saves the current project to a new file name. Note that the project is saved to an.acc file. Rebuild Hierarchy - This option (which is only available when the Hierarchy Browser is the current window) causes all VHDL files to be analyzed and the Hierarchy Browser display to be updated. This option should be used to update the hierarchy prior to compiling, linking or simulating your project. Clean Up Project - deletes all of the following project files from your project working directory: all *.O,.AN and.dp intermediate files; all *.LIB files; all.vx simulation executable files. New Module - displays the New Module dialog box, where you select the type of module to create. Open Module - opens a selected module in a text editing window. The file represented by the module will be opened using either the built-in text editor (a notepad-equivalent editor) or your choice of external text editing programs. To change the text editor invoked when modules are opened, select the System tab in the Options dialog. Add Module - causes a selected VHDL design file (.VHD file) to be added to the current project. Note that the program will copy the VHDL source file to the current directory if it is not already in the current directory. If there are already one or more modules in the project, the new module will be added at the end of the list of modules. Remove Module - removes the currently selected module from the project. However, the VHDL source file represented by the module is not deleted from its folder. Close Module - closes the currently active text editing window. Save Module - saves the contents of the currently active text editing window. Save Module As - saves the contents of the currently active text editing window to a new or different file name. Save Transcript As - saves the contents of the currently active Transcript dialog to a specified file name. Print - prints the currently selected text file. Edit Menu Along with the more commonly used Edit items (Undo, Redo, Find, etc.) this menu also contains the following items: Insert Declaration - displays a dialog, where you can enter a new declaration to insert into a module. Insert Instance - displays a dialog where you can insert an instance into a selected module. Insert Component - displays a dialog where you can insert a component into a selected module. MultiVHDL 8 User Guide 2-51

91 VHDL Simulation Search Project - opens the Search Project dialog box which allows you to perform a multi-file text search in the current project. View Menu Toolbar - lets you display or hide the toolbar. Show Hierarchy - shows all levels of hierarchy in the Hierarchy Browser. Note that you can selectively show hierarchy items by clicking on the "+" symbols displayed in the Hierarchy Browser. Hide Hierarchy - hides all lower-level hierarchy items (entities, architectures, packages, etc.) in the Hierarchy Browser. Only the modules corresponding to VHDL source files will be displayed. Simulate Menu Compile Selected - compiles the selected VHDL module and, optionally (via the Compile Options dialog), all files upon which the selected file depends. The result of compilation is an object file. Link Selected - links modules for simulation, using the selected VHDL module, entity or architecture as the top-level design unit. The result of linking is a simulation executable. Load Selected - loads the currently selected simulation executable. Options - opens the Options dialog with the current Simulation options displayed. Rebuild All - rebuilds all modules in the current project. Options Menu Compile - opens the Options dialog with the current Compile options displayed. Link - opens the Options dialog with the current Link options displayed. Simulate - opens the Options dialog with the current Simulation options displayed. System - opens the Options dialog with the current System options displayed. FSM Menu These menu items are used when creating and editing state machine diagrams: New State Machine - opens a new state machine window. Set Clock - sets the selected input port as the clock signal. Set Reset State - specifies the selected state as the initial state of the state machine when a reset is received. See also, 4.4 Setting State Machine Properties on page 4-4. Set Reset Condition - displays the FSM Properties dialog box, where you can enter the Reset Condition. See also, 4.4 Setting State Machine Properties on page 4-4. Add Input - adds an input port to the state machine diagram Electronics Workbench

92 Simulator Interface Menu Items Add Output - adds an output port to the state machine diagram. Add Bidirectional - adds a bidirectional port to the state machine diagram. Add Local - adds a local signal to the state machine diagram. Properties - displays the FSM Properties dialog box. View Source - displays the VHDL code generated for the state machine diagram Note For details on state machine functions, see State Machine Editor on page 4-1. WaveTest Menu New Graphical Testbench - use to create a graphical testbench. For details, see 3.1 Creating a New Waveform Testbench on page 3-1. Properties - Displays the Waveform Testbench Properties dialog box. For details, see 3.1 Creating a New Waveform Testbench on page Simulator Interface Menu Items File Menu Save Waveform As - saves a selected waveform to a new or different file name using the SynaptiCAD Waveformer format. Waveform files are saved with a.tim file extension. Print - prints a graphic image of the currently selected Waveform Display. Print Setup - opens up the standard Windows print setup dialog box. Exit - closes the program. The calling application is not closed. View Menu Remove all Cursors - removes all waveform cursors from the Waveform Display. Toolbar - allows you to display or hide the toolbar. Status Bar - allows you to display or hide the status bar. Zoom In - causes the Waveform Display zoom level to be decreased by a factor of two. Use this option to expand the waveform to get a closer look at simulation results. Zoom Out - causes the Waveform Display zoom level to be increased by a factor of two. Use the Zoom Out option to compress the waveform so you can see a broader range of simulation events. Zoom Range - causes the Waveform Display zoom level to be set according to the two mostrecently placed waveform cursors. Use the Zoom Range option to select a specific range for viewing. MultiVHDL 8 User Guide 2-53

93 VHDL Simulation Zoom All - causes the Waveform Display zoom level to be adjusted so that the entire waveform is visible. Zoom Normal - causes the Waveform Display zoom level to be readjusted to the default zoom level. Simulation Menu Select Display Objects - displays the Select Display Objects dialog. For details, see Loading the Simulation Executable on page Go - runs a simulation executable for a specified length of time. Stop - stops the current simulation run. Clear Events - clears all recorded simulation events. Restart - reloads the current simulation executable and clears all waveform event data. Toggle Breakpoint - use to set or remove a breakpoint at the line containing the source code cursor. Double-clicking in the Debugging window will also set or remove a breakpoint. Step - steps the simulation by a specified length of time. Step Over - steps the simulation by once source file line. If the current source file line is a subprogram call, the simulator does not step into the subprogram. This feature is only available if the project was linked with source-level debugging enabled. Step Into - steps the simulation by once source file line. If the current source file line is a subprogram call, the simulator steps into the subprogram. This feature is only available if the project was linked with source-level debugging enabled. Options - displays the Simulation Options dialog box. For details, see Loading the Simulation Executable on page Window Menu Command Window - displays the Command Entry dialog box. For details, see 2.8 Using the Command Entry dialog box on page Electronics Workbench

94 Chapter 3 Graphical Waveform Editor This chapter describes the use of MultiVHDL s Graphical Waveform Editor. The Graphical Waveform Editor is a graphical editor that you use to create stimulus for a design, expected output data for auto-checking testbenches, and connections to streams on the stream diagram. Note For information about streams, see 3.11 Streams on page The following topics are found in this chapter. Subject Creating a New Waveform Testbench Creating Clock Waveforms Creating Derived Clock Waveforms Editing Waveforms Adding and Removing Timing Checks Adding and Removing Data Checks Setting Graphical Testbench Properties Timing Parameters Limitations Running a Graphical Testbench Streams File Stream Reference Random Stream Reference Page No Creating a New Waveform Testbench Before creating a testbench for a given entity, a project containing that entity must exist. For details on creating projects, see Creating a Project File on page 2-3. To create a new waveform testbench: 1. Open the project containing the design under test. MultiVHDL 8 User Guide 3-1

95 Graphical Waveform Editor 2. Select WaveTest/New Graphical Testbench or click the Create New Module button and click Testbench Wizard (Graphical). The following dialog appears. 3. Click Next to accept the filepath and filename as displayed. Or Edit the filepath and filename as desired and click Next. The following dialog appears. 3-2 Electronics Workbench

96 Creating a New Waveform Testbench 4. Select the entity for which this testbench is being created and click Next. Enter the desired Simulation Time and click Next. When the final dialog appears, click Finish. The waveform diagram displays and includes a waveform for each port in the design under test. The waveform diagram is used to specify stimulus for the inputs of the design under test and the expected response on its outputs. MultiVHDL 8 User Guide 3-3

97 Graphical Waveform Editor To optionally edit the testbench s properties: 1. Select WaveTest/Properties. The Waveform Testbench Properties dialog box appears. 2. Edit the contents of the dialog as desired and click OK. 3.2 Creating Clock Waveforms By default, waveforms are graphical event lists that can be edited by adding and removing events. This can be tedious for clock signals that have many events at fixed intervals. Clock waveforms allow you to easily specify a clock in terms of its period. To change an event-list waveform to a clock waveform: 1. Double-click on the name of the signal to open the Signal Properties dialog box. Double-click to display Signal Properties dialog box. 3-4 Electronics Workbench

98 Creating Clock Waveforms 2. Change the Type field to "Clock", to make the dialog box appears as follows: 3. Make changes as desired: Initial value can be set to either 0 or 1 to indicate the value of the clock when it starts. Period should be set to the period of the clock, that is, the time duration of a single cycle. Duty must be a value from 1 to 99 that specifies the percentage of the clock cycle that the clock value is 1. Start time specifies when the clock should start. If the start time is non-zero then the value of the clock from time 0 up to the start time will be the opposite of the initial value specified. Caution If you change a waveform that already contains events to a clock waveform, the existing events will be overwritten and you will not be able to recover them. MultiVHDL 8 User Guide 3-5

99 Graphical Waveform Editor 4. Click OK to close the dialog. Your changes are reflected in the waveform editor. 3.3 Creating Derived Clock Waveforms A derived clock waveform is derived from some other clock (the master clock) on the diagram. Whenever the master clock waveform is modified, the derived clock waveform is automatically updated appropriately. To change a waveform to a derived clock waveform: 1. Double-click on the name of the signal to open the Signal Properties dialog box. 3-6 Electronics Workbench

100 Creating Derived Clock Waveforms 2. Change the Type field to "Derived clock", to make the dialog box appear as follows: 3. Select the desired master clock from the Reference signal drop-down list. The drop-down list includes all the other clocks and derived clocks on the diagram that can be used as a master clock. 4. Make changes as desired: Divisor specifies how the period of the derived clock is calculated from the period of the master clock. The period of the derived clock will be equal to the period of the master clock multiplied by the value of the divisor field. Thus a value of 2 will create a clock divider, and a value of 0.5 will create a clock doubler. Duty must be a percentage from 1 to 99 that specifies the percentage of the clock cycle that the clock value is 1. The duty of the derived clock is independent of the duty of the master clock. Phase a value from 0 to 359 that indicates the degree of shift between the derived clock and the master clock. A phase of 0 would mean that the derived clock's cycles start and end at the same time as the master clock's cycles, whereas a phase of 90 would indicate that the derived clock's cycles start 25% of the clock's period later than the master clock's cycles. Inverted when checked, the initial value of the derived clock is the opposite of that for the master clock. Otherwise, the initial value of the derived clock is equal to that of the master clock. Note The start time of the derived clock is always equal to the master clock's start time plus any phase shift specified. MultiVHDL 8 User Guide 3-7

101 Graphical Waveform Editor Caution If you change a waveform that already contains events to a clock waveform, the existing events will be overwritten and you will not be able to recover them. 3.4 Editing Waveforms Each waveform is either an event-list waveform or clock waveform. This section describes how to edit event-list waveforms. These waveforms are represented as a list of events. The waveform is edited by adding or removing events using one of the following event tools from the Waveform Editor toolbar. Low (0) High (1) Unknown (X) Numeric Value Move Editing Tool Erase Editing Tool These toggle buttons are used to select the active editing tool. The first four tools represent event values that can be added to the waveform. From left to right, they are are low ('0'), high ('1'), unknown ('X'), or a numeric value. When the numeric value tool is selected, the user is prompted for the numeric value each time the tool is used to edit a waveform. The first four tools can be used to modify binary and binary vector waveforms. The numeric value tool can also be used to modify integer and real number waveforms. The last two buttons are used to move and erase events. Events can be entered using either of the two following methods: A single edge can be inserted by clicking on the waveform with the left mouse button. The new edge will change the value of the waveform at the place where the left button was pressed according to the current editing tool. The waveform will have that value from that point until the point of the next edge in the waveform. A value range can be specified by pressing and holding the left mouse button at the start of the range, dragging the mouse to the end of the range, and releasing the mouse button. The value of the waveform in the specified range will be changed according to the current editing tool. The value of the waveform everywhere else will remain unchanged. Existing edges can be moved by dragging them. To drag an edge: 1. Click and hold the mouse button on the edge, then drag the mouse to where you wish to move the edge and release the mouse button. 3-8 Electronics Workbench

102 Adding and Removing Timing Checks Note When the move editing tool ( ) is selected, all the events to the right of the event being moved will follow the event being moved. If any other editing tool is selected, only the selected edge will be moved. To remove a single edge, select the erase editing tool ( ) and click on that edge. To remove multiple edges: 1. Select the erase editing tool. 2. Click and hold the mouse button down to the left of the first edge to be deleted, drag the mouse to the right of the last edge and release the mouse button. 3.5 Adding and Removing Timing Checks If desired, timing checks can be added to the waveform diagram. These checks are added to make sure that data is set up long enough before a clock edge and stays (holds) for long enough for it to be processed. In the following example, the setup time is the minimum allowed time between a change in the input and a positive clock edge. Similarly, the hold time is the minimum allowed time between a positive clock edge and a change in the input. To add a timing check: 1. Select either the Setup or Hold button from the toolbar. Press to enter setup checks Press to enter hold checks 2. For setup checks - press and hold the left mouse button on the test-signal edge, drag the mouse to the clock edge and release the mouse button. For hold checks - press and hold the left mouse button on the clock edge, drag the mouse to the test-signal edge and release the mouse button. MultiVHDL 8 User Guide 3-9

103 Graphical Waveform Editor A Timing Check Properties dialog like the following will be displayed. 3. Change the contents of the dialog as desired: Timing parameter specifies a name for the time value. The name can be a standard VHDL identifier, or it can have the form <name>/<subscript>. In the later case, the name will be displayed with the specified subscript on the diagram. If the specified name is already used elsewhere on the diagram, then the time value of the new check must be the same. If they are not the same, you will be prompted to change the name. Please consult 3.8 Timing Parameters on page 3-14 for an explanation of timing parameters. Repeat for all events can be checked if this timing constraint applies to all events on the test signal. If this box is not checked, the check will only be performed for the single event that the check is attached to. On the diagram, timing checks that are repeated for all events on the test signal are denoted by an asterisk next to the timing parameter name. 4. Click OK. The selected type of timing check appears. Setup Check Hold Check 3-10 Electronics Workbench

104 Adding and Removing Data Checks 5. Optionally, click on the Parameters tab in the Graphical Waveform Editor to view the timing checks in the diagram. Note For more details on this tab, see 3.8 Timing Parameters on page To remove a timing check: 1. Click on the timing parameter to select it. 2. Select Edit/Cut. 3.6 Adding and Removing Data Checks By default, the output response of the design under test is not validated when running the testbench. Data checks are used to specify when waveforms of the design under test should be validated against the expected waveform of the testbench. The outputs can be checked at individually specified points, or exhaustively One-time Data Checks One-time data checking can be included in the testbench by adding checkpoints to the timing diagram at the points where a signal's actual value should be checked against the expected value in the waveform diagram. To add a checkpoint: 1. Select the Checkpoint tool. MultiVHDL 8 User Guide 3-11

105 Graphical Waveform Editor 2. Click on the output waveform at each place where you wish to place a check. One-time data checks. To remove a checkpoint, click on it with the mouse while the Checkpoint tool is still selected Exhaustive data checks Running an exhaustive data check is the most convenient method of adding data validation to the testbench. This method specifies that each event in the actual output response should match an event on the waveform diagram. To use this method: 1. Double-click on the name of the output signal. The following dialog box appears Electronics Workbench

106 Setting Graphical Testbench Properties 2. Change the settings as desired: Verify all events enables exhaustive checking. Delay used to specify the maximum amount of delay that may occur between an actual event and the corresponding event on the timing diagram. When the delay field is 0, the actual output must exactly match the timing diagram waveform. 3. Click OK to close the dialog. Indicates exhaustive check 3.7 Setting Graphical Testbench Properties The main testbench options can be viewed/changed from the properties window shown below. To open the properties box: 1. Select WaveTest/Properties. Architecture Entity 2. Edit the following fields as desired: Testbench Entity Name controls the name of the entity used for the testbench when generating VHDL code. Entity/architecture under test used to select the entity/architecture pair to be tested. The entity is selected when the testbench is created and cannot be changed afterwords since the testbench is specific to the particular interface specified by the entity. The architecture, however, is independent of the interface and can be changed at any time. By default, any is selected, in which case, the first architecture found for the given MultiVHDL 8 User Guide 3-13

107 Graphical Waveform Editor entity is used. To select a specific architecture, click on the drop-down list, which includes all the architectures defined in the project for the given entity. Simulation time is used to specify both the size of the waveform diagram and to determine how long to run the simulator when running the testbench. This is also important when using continuous mode to design a testbench because the output waveforms will only be updated up to the time specified here. 3.8 Timing Parameters Timing parameters are names assigned to the time values used in setup and hold timing checks. The use of named values rather than actual numeric time values provides easier readability and useful documentation. The actual numeric time value associated with a given timing parameter is initially established the first time it is used in the diagram. All timing checks in the diagram that use the same timing parameter name must have the same time interval between edges. Once a diagram has been created and contains timing checks, the values of the existing timing parameters can be changed. Whenever a timing parameter is changed, every timing check using that parameter is updated on the diagram to reflect the change. To change the values of timing parameters: 1. Click on the Parameters tab at the bottom of the Graphical Waveform Editor. A window, like the following, appears displaying a list of all the timing parameters and text entry fields for their values. 2. Edit the values as desired and click on the Waveforms tab. Your changes will be reflected in the appropriate waveforms Electronics Workbench

108 Limitations 3.9 Limitations The waveform testbench editor has two limitations on the interface of the design under test: Generics are not supported. Generics are typically items created by chip manufacturers to work with their chip architecture. Examples include counters, adders and comparators. These are not necessarily written in VHDL, but the vendor tools would know how to compile them and include them in a project. Only ports of certain types will be accessible from the waveform editor. If the design under test has ports of an unsupported type, the waveform testbench editor can still be used, but those ports will not appear in the waveform diagram. The supported types are: standard types bit, character, integer, real, and time user-defined character enumeration types (e.g. std_ulogic) vectors whose element type is bit, character, or a user-defined character enumeration type (e.g. std_ulogic) Running a Graphical Testbench To run the graphical testbench: 1. Click on the Rebuild Hierarchy button in the Hierarchy Browser. Rebuild Hierarchy button Files with.wtb extensions are graphical testbenches. 2. Select the graphical testbench in the Hierarchy Browser and select Simulate/Compile Selected. The Transcript dialog appears and displays messages as the file is compiled. Note For details on compiling see Compiling Modules for Simulation on page Select Simulate/Link Selected. The Transcript dialog displays messages as the file is linked. Note For details on linking, see Linking Modules for Simulation on page MultiVHDL 8 User Guide 3-15

109 Graphical Waveform Editor 4. Select Simulate/Load Selected. The following dialog appears: Select the Objects to Display as desired and click Close. The simulator interface appears. Note For details on selecting objects, see Select Display Objects Dialog on page Select Simulation/Go. The waveforms for the selected objects appear. Note For details on the simulator interface, see 2.6 Working with the Simulator Interface on page Electronics Workbench

110 Streams 3.11 Streams The Streams tab of the Graphical Waveform Editor is where you create streams of data that can be used to drive the design under test in the form of stimulus or to validate the design with expected output data. In MultiVHDL, there are three types of streams available: Input File Stream reads records from a text file. This stream can be used as stimulus or expected output data. Random Stream generates records with randomized values within user-specified constraints. Output File Stream writes records to a text file. This stream can be used to record simulation outputs for later inspection or post-processing. All streams either generate or consume a list of records. Each record consists of one or more fields of a user-specified type. Input File Streams and Random Streams are streams that generate data. These streams can provide stimulus by connecting them to input signals on the waveform diagram. They may also be used as expected output data for validating output signals by connecting them to output signals on the waveform diagram. Output File Streams are streams that consume data. This kind of stream is used to store simulation results by connecting them to output signals on the waveform diagram. The following sections describe how to use streams Creating Streams To create a stream: 1. Click on one of the stream buttons on the stream editor's toolbar (you must be in the Streams tab of the Graphical Waveform Editor. Input File Stream tool. Random Stream tool. Output File Stream tool. MultiVHDL 8 User Guide 3-17

111 Graphical Waveform Editor The stream appears on the diagram, as in the following example of an Input File Stream. 2. Double-click on the new stream to edit its fields and other stream dependent properties. For details, refer to the following sections: Setting Up Input File Streams on page Setting Up Output File Streams on page Setting Up Random Streams on page Using a stream for stimulus Both Input File Streams and Random Streams can be used to provide stimulus for the design under test. This is accomplished by associating an input-type signal with a field of the stream. To associate an input signal with a stream: 1. Create the stream as described in Creating Streams on page Click on the the Waveform tab of the Graphical Waveform Editor and double-click on the desired input signal to open its Signal Properties dialog box. Note In this example, the input signal called "Data" is selected. (See step 6. on page 3-20 for a complete diagram) Electronics Workbench

112 Streams 3. Select "Stream" from the Type drop-down list. 4. Using the Stream and Field drop-down lists, select the stream and field that should be used for stimulus data on this signal. Streams have no concept of simulation time and the Reference signal and Reference edge together specify when values from the stream field are scheduled on the input signal. On every occurrence of the specified edge, the value of the specified field of the next record in the specified stream is assigned to the input signal. 5. Edit the following fields as desired: Enable specifies a condition that will enable/disable the stream. Delay can be used to specify the delay used when scheduling values on the signal. Uncertainty is currently unused and reserved for future use. The value should not be changed. Initial value specifies the value of signal from time 0 up to the time the first value from the stream is scheduled. This field may be left blank, in which case, a default value will be used. MultiVHDL 8 User Guide 3-19

113 Graphical Waveform Editor 6. Click OK to close the dialog. Refer to the diagram below for an example. This data stream was created using the settings shown here. stream1, which was set up in the Streams tab, is referenced in the Signal Properties dialog box Using a stream for expected output data Both Input File Streams and Random Streams can be used to provide expected output data for the design under test. This is accomplished by associating an output signal with a field of the stream. To connect an output signal to a stream: 1. Create the stream as described in Creating Streams on page Open the Signal Properties dialog box of the output signal in the Waveform tab of the Graphical Waveform Editor Electronics Workbench

114 Streams 3. Select "Stream" from the Type drop-down list. The top portion of the dialog box will appear as follows: 4. Using the Stream and Field drop-down lists, select the stream and field that should be used as expected output data on this signal. Streams have no concept of simulation time and the Reference signal and Reference edge together specify when values from the stream field are compared to the output signal. On every occurrence of the specified edge, the value of the specified field of the next record in the specified stream is compared to the current value of the output signal. 5. Edit the following fields as desired: Enable specifies a condition that will enable/disable the stream. Delay can be used to specify that the signal be validated at the specified amount of time after the reference signal's reference edge. Uncertainty is currently unused and reserved for future use. The value should not be changed Using a stream to save simulation results An Output File Stream is used to store simulation results in a text file. This is accomplished by associating an output signal with a field of the stream. To connect an output signal to a stream: 1. Create the Output File Stream as described in Creating Streams on page MultiVHDL 8 User Guide 3-21

115 Graphical Waveform Editor 2. Double-click on the desired output signal in the Waveform tab to display the Signal Properties dialog box and click on the Data Capture tab. In this example, we are using the "Count" output signal. Double-click an output signal to display the Signal Properties dialog. 3. Enable the Capture data checkbox. The dialog box will appear as shown below. 4. Using the Stream and Field drop-down lists, select the stream and field where the output signal's values should be output Electronics Workbench

116 Streams Streams have no concept of simulation time and the Reference signal and Reference edge together specify when values are output to the stream field. On every occurrence of the specified edge, the current value of the output signal is stored in the specified field of the current record of the specified stream. 5. In the Enable field, enter a condition that will enable/disable the stream. When you are finished, the dialog will appear similar to the example below. 6. Click OK to close the dialog. When you run the simulation, the output will be written to the text file specified when you set up the Output File Stream. Output Text File Example. The output file appears in the same folder as the VHDL project file. Note See also, Setting Up Output File Streams on page MultiVHDL 8 User Guide 3-23

117 Graphical Waveform Editor Multi-field streams Any stream may have multiple fields that can be associated with signals in the Waveforms tab. When more than one signal is connected to a single stream, the stream data must be accessed at the same rate by each signal. This implies that the reference signals specified for all connected signals must have the same period. Otherwise, stream data will be lost. Streams generate or consume data one record at a time without any buffering. Thus, when a signal requires access to the next record of a stream, the stream advances to the next record even if other signals have not yet used the current record. Consider the following example. An Input File Stream named "Vectors" has two fields a and b. Field a is connected to an input signal sa with a reference signal clka that has a 100 ns period, and field b is connected to signal sb with a reference signal clkb that has a 200 ns period. Simulation would proceed as follows: At 100 ns: The first reference edge occurs on the clka signal so a read is performed on the Vectors stream. Let's say that the first record in the file is (a => "00", b => "11"). The "00" value will then be schedule on signal sa. At 200 ns: The second reference edge occurs on the clka signal and the a field of the current record of Vectors has already been consumed so a second read is performed on the Vectors stream. The new record is (a=> "01", b => "10"), and "01" is scheduled on signal sa. At 200 ns: The first reference edge occurs on the the clkb signal and the b field of the current record of Vectors has not yet been consumed so, the "10" value of the current record is scheduled on signal sb. Since there is no buffering of the Vectors stream, the "11" value of the first record is no longer available and was never scheduled on sb Placing Data Paths Between Streams You can create a data path so that an Input File Stream or a Random Stream feeds an Output File Stream. To create data paths between streams: 1. Create the desired streams in the Streams tab of the Graphical Waveform Editor. For details on creating file streams, see Creating Streams on page Electronics Workbench

118 File Stream Reference 2. Hold down the right mouse button over either an Input File Stream or a Random Stream, drag the cursor to an Output File Stream and release the mouse. Data Path Data Path 3. To change the shape of the data path s arrow, select it and drag the handles that appear to the desired location File Stream Reference Input File Streams and Output File Streams provide the ability to read and write text files during simulation. These streams read or write one record per line in a user specified format. The following sections describe how to set up input and output file streams. Note See also, Creating Streams on page Setting Up Input File Streams This section discusses how to set up an Input File Stream. For details on creating a file stream, see Creating Streams on page To set up or edit an Input File Stream s properties: 1. Click the Streams tab in the Graphical Waveform Editor. MultiVHDL 8 User Guide 3-25

119 Graphical Waveform Editor 2. Click on the desired stream and select Edit/Properties. The I/O Properties dialog box displays. 3. Edit the following fields as desired: Name specifies the name of the stream block as displayed on the diagram, and as referenced from the Waveforms tab of the Graphical Waveform Editor. Filename the name of the file that the stream reads (for example, "teststreams.txt"). This file must be placed in the same folder as the.acc project file. Each line of the file must contain a comment (any line beginning with the '#' character) or a single record formatted according to the format specified in the Format field. Format The format is specified in a similar manner to the scanf function in C. The format consists of one or more conversion specifiers separated by zero or more ordinary characters. Each conversion specifier describes the format of the corresponding record field. Conversion specifiers from left to right correspond to record fields from first to last. Conversion specifiers have the following syntax: %[width]<type> That is, the literal character '%', followed optionally by an integer text width, followed by a type specifier. No spaces may appear between these items. If the width is present, it specifies the maximum number of characters read for the conversion. The type indicates how the field value is represented in the file. The type may be any one of 'd', 'u', 'o', 'x', 'X', 'f', 'c', or 's', and are interpreted as follows: d - An integer value in decimal form is read. Any whitespace characters preceding the value will be skipped Electronics Workbench

120 File Stream Reference u - An unsigned integer value in decimal form is read. Any whitespace characters preceding the value will be skipped. o - An unsigned integer value in octal form is read. Any whitespace characters preceding the value will be skipped. x, X - An unsigned integer value in hexadecimal form is read. Any whitespace characters preceding the value will be skipped. f - A floating point value is read. Any whitespace characters preceding the value will be skipped. c - A single character is read. s - A string of characters is read. If the type of the value read does not match the field's type, the value will be automatically converted. Thus, a bit_vector field could use a %d conversion specifier just as well as the %s conversion specifier. If there are any ordinary characters in between conversion specifiers (other than the space character) then those characters must appear between the text fields in the input file. If the space character appears in between conversion specifiers then any whitespace present at that point will be skipped. Consider the following format string: %2d%d,%x and the input line 23456, 25 The input line would be interpreted as follows: The first format specifier %2d requires that a decimal integer of at most 2 characters be read, so the first value read is 23. If the first field in the stream's record type is not an integer, the integer value will be converted and stored in the stream record. The next format specifier %d requires that a decimal integer of any number of characters be read, so characters are read up to the first non-digit character, and the result is 456. Again the integer value is converted as needed by the second field of the stream's record type. Next there is a ',' character in the format string, so a ',' will be read from the input line. If the character read was not the ',' character, an error would be reported. The next format specifier %x requires that a hexadecimal unsigned integer of any number of characters be read. As for the d, u, o, and X conversion types, any leading whitespace is ignored, so the space in the input line will be skipped, the 25 will be read, and the result is 37. Again the integer value is converted as needed for the third field of the stream's record type. MultiVHDL 8 User Guide 3-27

121 Graphical Waveform Editor 4. When you have finished entering data in the General tab, it will resemble the following example: 5. Using the Fields listbox in the Type tab, you can add, remove, or edit the fields of the stream's record type, as in the following example: 6. Click OK to close the dialog Electronics Workbench

122 File Stream Reference Setting Up Output File Streams This section discusses how to set up an Output File Stream. For details on creating a file stream, see Creating Streams on page To set up or edit an Output File Stream s properties: 1. Click the Streams tab in the Graphical Waveform Editor. 2. Click on the desired stream and select Edit/Properties. The I/O Properties dialog box displays. 3. Edit the fields as desired: Name specifies the name of the stream block as displayed on the diagram, and as referenced from the Waveforms tab of the Graphical Waveform Editor. Filename is the name of the file that records will be written to (for example, "testoutput2.txt"). Format each line written to the file will contain a single record formatted according to the format specified in this field. The format is specified in a similar manner to the printf function in C. The format consists of one or more conversion specifiers separated by zero or more ordinary characters. Each conversion specifier describes the format of the corresponding record field. Conversion specifiers from left to right correspond to record fields from first to last. Conversion specifiers have the following syntax: %[0][width]<type> That is, the literal character '%', followed optionally by the literal character '0', followed optionally by an integer text width, followed by a type specifier. No spaces may appear MultiVHDL 8 User Guide 3-29

123 Graphical Waveform Editor between these items. If the optional '0' character is present, zero padding is used to fill the specified text width. If the width is present, it specifies the minimum number of characters used to hold the field value. The type indicates how the field value will be formatted in the output file. The type may be any one of 'd', 'o', 'x', 'X', 'f', 'c', or 's', and are interpreted as follows: d - An integer value is output in decimal format. o - An integer value is output in octal format. x - An integer value is output in hexadecimal format using lowercase letters. X - An integer value is output in hexadecimal format using uppercase letters. f - A floating point value is output. c - A bit, or std_ulogic value is output as a character. s - A vector of bit or std_ulogic values is output as a string of characters. If the type of the record field value does not match the conversion type, the value will be automatically converted. Thus, a bit_vector field could be output using a %d conversion specifier just as well as the %s conversion specifier. If there are any ordinary characters in between conversion specifiers then those characters will be written to the output file just as they appear in the format string. Consider the following example format string %02x,%2s and the output record ("LLLLLLHH","LL") The output line in this example would be constructed as follows: The first conversion specifier %02x requires an integer be output in hexadecimal format using at least two characters with zero padding as necessary. The first field of the record "LLLLLLHH" will first be converted to an integer (3), and output as 03. Following the first conversion specifier is the ordinary ',' character that is simply output as is. The next conversion specifier %2s requires a vector be output as a string of characters. The second field of the record "LL" is therefore simply output as LL. The resulting output line is 03,LL 3-30 Electronics Workbench

124 File Stream Reference 4. When you have finished entering data in the General tab, it will resemble the following example: 5. Using the Fields listbox in the Type tab, you can add, remove, or edit the fields of the stream's record type, as in the following example: 6. Click OK to close the dialog. MultiVHDL 8 User Guide 3-31

125 Graphical Waveform Editor 3.13 Random Stream Reference A Random Stream generates random data within user-specified constraints and can be used as stimulus for the design under test. As with any other stream, the Random Stream generates records of values. The value of each field of the stream's record type is randomized according to its own constraints Setting Up Random Streams This section discusses how to set up a Random Stream. For details on creating a stream, see Creating Streams on page To set up or edit a Random Stream s properties: 1. Click the Streams tab of the Graphical Waveform Editor. 2. Click on the desired stream and select Edit/Properties. The Random Properties dialog box appears. 3. Edit the following fields as desired: Name specifies the name of the stream block as displayed on the diagram, and as referenced from the waveform diagram. Constraints you can add, remove, or edit constraints. Constraints are used to constrain the random numbers generated for a field to a given range of values. For example, the constraint 0 < g < 100 restricts the random number generator to 3-32 Electronics Workbench

126 Random Stream Reference producing only values 1 to 99 for the g field of the stream. The syntax of a constraint must be: constraint ::= <field> <relation> <expression> Or constraint ::= <expression> <relation> <field> <relation> <expression> In the above, <field> must be the name of a field in the Fields list box. The <relation> must be one of the following relational operators: relation ::= "<" ">" ">=" ">=" "=" And finally, expressions have the following syntax: expression ::= <term> { <adding_operator> <term> } term ::= <factor> { <multiplying_operator> <factor> } factor ::= ["-"] primary "(" expression ")" primary ::= <field> <number> adding_operator ::= "+" "-" multiplying_operator ::= "*" "/" Notice that constraint expressions may refer to other fields of the stream. When this is the case, the random number of the field referenced in the constraint is generated first and then used to determine the value of the constraint expression. 4. When you have finished entering data in the General tab, it will resemble the following example: 5. Using the Fields listbox in the Type tab, you can add, remove or edit the fields of the stream s record type. 6. Click OK to close the dialog. MultiVHDL 8 User Guide 3-33

127 Graphical Waveform Editor Random number generation Random number generation is based on the algorithm published by Pierre L'Ecuyer in Communications of the ACM, v31n6, June 1998, pp This algorithm generates uniform 32-bit random numbers for 32-bit platforms. Regardless of the field type, a single 32- bit random number is used to generate the field's value. The range of random numbers generated will be restricted to 32-bits even for longer vector fields. After applying L'Ecuyer's algorithm to produce a random number, the range of permissible values is determined for the field. If there are no constraints defined for the field, the range will simply be the largest range possible for the field's type. Otherwise, the field's constraint will be evaluated to determine the permissible range. Constraint expressions are also evaluated using 32-bit values. The 32-bit random number is then mapped to the permissible range using the modulus operator. The result may not be uniform due to the use of the modulus operator. The seed values (the algorithm requires two seed values) used for random number generation are determined when the stream is created and do not change thereafter. Thus, simulation results will be reproducible. The VHDL code generated for testbenches using random streams define two shared variables initialized with these seed values. Therefore, it is possible to make copies of the testbench and change these initial values for additional coverage. The initial values of the seeds must be within the following bounds 1 <= Seed1 <= , and 1 <= Seed2 <= Floating point numbers The production of random floating point numbers is slightly different. If a field of the real type does not have any associated constraint then the field will be assigned random values that are uniform over the range of 32-bit floating point representations. In this case, the bits of the 32-bit random number are used to construct a floating point number. On the other hand, if a field of the real type does have an associated constraint then the field will be assigned real values uniform over the range defined by the constraint. In this case, the 32-bit random number is mapped to the interval 0.0 to 1.0, which is then mapped to the range defined by the constraint Electronics Workbench

128 Chapter 4 State Machine Editor This chapter discusses MultiVHDL s State Machine Editor. The following topics are found in this chapter. Subject Introduction Creating a New State Machine Defining Ports Setting State Machine Properties Adding and Editing States Adding and Editing State Transitions Using local signals Debugging State Machines State Machine Example Page No Introduction A Finite State Machine (FSM) is a behavioral model that consists of states, transitions and actions: States - reflect the input changes from the system start to the present moment. Transitions - indicate a state change and include a condition that would need to be fulfilled to enable the transition. MultiVHDL 8 User Guide 4-1

129 State Machine Editor Actions - are descriptions of an activity to be performed at a given point. They are assigned to states and/or transitions. State Transition Transition Condition Action In MultiVHDL, FSMs are represented using a state machine diagram as in the example below. State machine diagrams are created by the State Machine Editor, which in turn is used to graphically create VHDL code. To view the text version of the following, see 4.9 State Machine Example on page Electronics Workbench

130 Creating a New State Machine 4.2 Creating a New State Machine To create a new state machine diagram, select FSM/New State Machine and enter the name of the new file. Note All state machine diagrams in MultiVHDL have the extension.vsm. When designing a new state machine, the following design flow works best: 1. Determine the interface (ports) to the state machine, and add them to the diagram accordingly. See 4.3 Defining Ports on page Configure the state machine properties. 3. Add states to the diagram. 4. Add transitions between the states. 4.3 Defining Ports To add input, output or bidirectional ports to the state machine: 1. Select one of the following toolbar buttons. Adds a new input port. (Or select FSM/Add Input). Adds a new output port. (Or select FSM/Add Output). Adds a new bidirectional port. (Or select FSM/Add Bidirectional). The Signal Properties dialog box appears. Tip The toolbar buttons shown in this step remain pressed so that you can continue placing the selected port type. To stop placing the selected port, click on the button again to deselect it. 2. Enter the Name and Type of the port. Note The Mode is set according to the type of port you requested, although you can change it here. MultiVHDL 8 User Guide 4-3

131 State Machine Editor 3. Set the following as desired: Registered checkbox allows you to configure how code is generated for output ports. Each registered output, has a corresponding register that is fed by the combinational logic that computes the output's value. The output of the combinational logic is immediately latched on the active clock edge, and the delay on the output value is limited to the register delay rather than the delay path in the combinational logic. Only the timing behavior of the state machine is affected by registered ports; the functional behavior is the same whether the port is registered or not. Default Action Value can be used to specify a default value to be assigned an output signal when no other actions are defined on the signal. The value may be any valid VHDL expression. This field is only present for output and bidirectional signals. Note The above elements do not appear for input ports. 4. Click the Add button to add the port to the diagram and continue adding more ports, or click Done to add the signal and close the dialog box. Note Every state machine should have at least one input, the clock. Port ordering As ports are added to the diagram, they are automatically arranged on the left side of the diagram. The ordering, from top to bottom, determines the order that the ports appear in the port clause of the generated VHDL entity. To change the order of the ports, drag and drop them on the diagram in the desired sequence. 4.4 Setting State Machine Properties We recommend that you set the state machine properties as soon as you have defined port signals, to avoid error messages that appear when saving the file. 4-4 Electronics Workbench

132 Setting State Machine Properties To set the global properties of the state machine: 1. Select FSM/Properties. The FSM Properties dialog box appears. 2. Set the following fields as desired: Entity Name specifies the name of the VHDL entity generated for the state machine. By default, this will be the name of the file. Clock specifies which input port is the clock signal. The drop-down list will include all input ports defined for the state machine. This property can also be set by selecting a port in the diagram editor window and selecting the FSM/Set Clock menu item. Clock Edge specifies whether the state machine is clocked by the rising or falling edge of the clock signal. Reset State specifies the initial state of the state machine when a reset is received. The reset state is optional. The drop-down list can be used to select any state in the state machine. This property can also be set by selecting a state in the diagram editor window and selecting the FSM/Set Reset State menu item. Reset Condition can be any boolean VHDL expression of the input ports. The reset condition is optional. This property can also be set by selecting the FSM/Set Reset Condition menu item. Reset Style can be used to specify whether the reset is synchronous or asynchronous. This field is irrelevant, if a reset state is not being used. Context Clause specifies the context clause to be included in the generated VHDL code. By default, only the std_logic_1164 package is included. Adding other items (such as use ieee.numeric_std.all;) will allow you to use signals of other types in your state machine. MultiVHDL 8 User Guide 4-5

133 State Machine Editor 4.5 Adding and Editing States To add new states to the diagram: 1. Click the State toggle button. 2. Click in the diagram editor window with the left mouse button to insert a new state at that location. To exit state insertion mode, click the State button again. To move a state, drag it with the left mouse button. To resize a state, select it and use the anchor boxes that appear around it. To de-select a state, click on it again. To delete a state, select it and select Edit/Cut. When states are added to the diagram, they have a default name and default properties which can be edited using the State Properties dialog box. To edit the state's properties: 1. Double-click on the state or select the state and then select Edit/Properties. The State Properties dialog box appears 2. Edit the fields as desired: Action specifies output values for this state. This field must be zero or more VHDL signal assignment statements to output ports. Display Action checkbox use to control whether an action is shown on the display. 4-6 Electronics Workbench

134 Adding and Editing State Transitions 4.6 Adding and Editing State Transitions To add a state transition to a diagram: 1. Press and hold the right mouse button on the source state, drag the mouse to the target state and release the mouse button over the target state. Source State State Transition Target State To change the shape of the transition arrow: 1. Select it with the left mouse button. 2. Anchor boxes appear along the transition that can be dragged to change the shape of the arrow as desired. To move a transition, drag it with the left mouse button. To delete a transition, select it and choose Edit/Cut or click on the cut tool bar button. To edit the transition's properties: 1. Double-click on the transition. Or Select the transition and choose Edit/Properties. The Transition Properties dialog box appears. 2. Edit the following fields as desired: Condition - specifies the condition under which the transition is to take place. The condition must be a valid boolean VHDL expression of the input ports. MultiVHDL 8 User Guide 4-7

135 State Machine Editor Action - can be used to specify outputs on any output ports, which will will be applied whenever this transaction is active. The output action must contain zero or more valid VHDL signal assignments to output ports. Priority - can be used to give a transition priority relative to other transitions from the same state. The priority level can be any number greater than or equal to 1, where 1 is the highest priority. There may be multiple transitions at the same priority level. The transition to be taken is determined as follows: 1. Determine the highest level of priority that has one or more transitions whose condition is true. 2. Arbitrarily chose a transition from the transitions that are at the determined priority level and whose condition is true. Transitions that are not assigned a priority level are assumed to be of the lowest priority. 4.7 Using local signals If a state machine makes multiple references to some common expression in conditions or actions, it may be convenient to create a local signal to replace the common expression. To create a local signal: 1. Select FSM/Add Local. Or Select the toolbar button. The Signal Properties dialog box appears. 2. Edit the following fields as desired: Name - specifies the name of the signal, and the Type field specifies the type of the signal. Value - should contain a legal VHDL expression that defines the value of the local signal. When VHDL code is generated for the state machine, the ready signal will be 4-8 Electronics Workbench