Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery

Transcription

1 Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Yu Cai, Yixin Luo, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *LSI Corporation 1

2 Many use cases: You Probably Know + High performance, low energy consumption 2

3 Flash Controller NAND Flash Memory Challenges Requires erase before program (write) High raw bit error rate CPU Raw Flash Memory Chips ECC Controller 3

4 Raw bit error rate (RBER) ~2000 ~3000 Limited Flash Memory Lifetime Goal: Extend flash memory lifetime at low cost P/E Cycle Lifetime ECC-correctable RBER Program/Erase (P/E) Cycles (or Writes Per Cell) 4

5 Retention Loss Charge leakage over time 0 0 Flash cell Retention error 1 One dominant source of flash memory errors [DATE 12, ICCD 12] 5

6 Before I show you how we extend flash lifetime NAND Flash 101 6

7 Threshold Voltage (V th ) Flash cell Flash cell 1 0 Normalized V th 7

8 Threshold Voltage (V th ) Distribution Probability Density Function (PDF) 1 0 Normalized V th 8

9 Read Reference Voltage (V ref ) DF V ref 1 0 Normalized V th 9

10 Multi-Level Cell (MLC) DF Erased (11) ER-P1 V ref P1 (10) P1-P2 V ref P2 (00) P2-P3 V ref P3 (01) Normalized V th 10

11 Threshold Voltage Reduces Over Time Before After some retention retention loss: loss: DF P1 (10) P2 (00) P3 (01) Normalized V th 11

12 Fixed Read Reference Voltage Becomes Suboptimal Before After some retention retention loss: loss: DF P1 (10) P1-P2 V ref P2 (00) P2-P3 V ref P3 (01) Raw bit errors Normalized V th 12

13 Optimal Read Reference Voltage (OPT) DF P1 (10) P1-P2 V ref P2 (00) P2-P3 V ref P1-P2 OPT P2-P3 OPT After some retention loss: P3 (01) Minimal raw bit errors Normalized V th 13

14 Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage 14

15 Retention Failure After significant some retention retention loss: loss: DF P1 (10) P1-P2 V ref P2 (00) P2-P3 V ref P3 (01) Uncorrectable Correctable errors Normalized V th 15

16 Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage Goal 2: Design an offline mechanism to recover data after detecting uncorrectable errors 16

17 To understand the effects of retention loss: - Characterize retention loss using real chips 17

18 To understand the effects of retention loss: - Characterize retention loss using real chips Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage Goal 2: Design an offline mechanism to recover data after detecting uncorrectable errors 18

19 Characterization Methodology FPGA-based flash memory testing platform [Cai+,FCCM 11] 19

20 Characterization Methodology FPGA-based flash memory testing platform Real 20- to 24-nm MLC NAND flash chips 0- to 40-day worth of retention loss Room temperature (20⁰C) 0 to 50k P/E Cycles 20

21 Characterize the effects of retention loss 1. Threshold Voltage Distribution 2. Optimal Read Reference Voltage 3. RBER and P/E Cycle Lifetime 21

22 PDF 1. Threshold Voltage (V th ) Distribution P1 P2 P3 Normalized V th 22

23 1. Threshold Voltage (V th ) Distribution 40-day 0-day 40-day 0-day P1 P2 P3 Finding: Cell s threshold voltage decreases over time 23

24 2. Optimal Read Reference Voltage (OPT) 40-day OPT 0-day OPT 40-day OPT 0-day OPT P1 P2 P3 Finding: OPT decreases over time 24

25 RBER 3. RBER and P/E Cycle Lifetime P/E Cycles 25

26 Nominal Lifetime Extended Lifetime 3. RBER and P/E Cycle Lifetime Reading data with 7-day worth of retention loss. V ref closer to actual OPT Actual OPT ECC-correctable RBER Finding: Using actual OPT achieves the longest lifetime 26

27 Characterization Summary Due to retention loss Cell s threshold voltage (V th ) decreases over time Optimal read reference voltage (OPT) decreases over time Using the actual OPT for reading Achieves the longest lifetime 27

28 To understand the effects of retention loss: - Characterize retention loss using real chips Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage Goal 2: Design an offline mechanism to recover data after detecting uncorrectable errors 28

29 Naïve Solution: Sweeping V ref Key idea: Read the data multiple times with different read reference voltages until the raw bit errors are correctable by ECC Finds the optimal read reference voltage Requires many read-retries higher read latency 29

30 Comparison of Flash Read Techniques Flash Read Techniques Lifetime (P/E Cycle) Performance (Read Latency) Fixed V ref Sweeping V ref Our Goal 30

31 Observations 1. The optimal read reference voltage gradually decreases over time Key idea: Record the old OPT as a prediction (V pred ) of the actual OPT Benefit: Close to actual OPT Fewer read retries 2. The amount of retention loss is similar across pages within a flash block Key idea: Record only one V pred for each block Benefit: Small storage overhead (768KB out of 512GB) 31

32 Retention Optimized Reading (ROR) Components: 1. Online pre-optimization algorithm Periodically records a V pred for each block 2. Improved read-retry technique Utilizes the recorded V pred to minimize read-retry count 32

33 1. Online Pre-Optimization Algorithm Triggered periodically (e.g., per day) Find and record an OPT as per-block V pred Performed in background Small storage overhead DF New V pred Old V pred Normalized V th 33

34 2. Improved Read-Retry Technique Performed as normal read V pred already close to actual OPT Decrease V ref if V pred fails, and retry DF OPT V pred Very close Normalized V th 34

35 Retention Optimized Reading: Summary Flash Read Techniques Lifetime (P/E Cycle) Performance (Read Latency) Fixed V ref Sweeping V ref 64% ROR Nom. Life: 2.4% 64% Ext. Life: 70.4% 35

36 To understand the effects of retention loss: - Characterize retention loss using real chips Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage Goal 2: Design an offline mechanism to recover data after detecting uncorrectable errors 36

37 Retention Failure After some significant retention retention loss: loss: DF P1 (10) P1-P2 V ref P2 (00) P2-P3 V ref P3 (01) Uncorrectable Correctable errors Normalized V th 37

38 Leakage Speed Variation DF S low-leaking cell F ast-leaking cell Normalized V th 38

39 Initially, Right After Programming DF P2 P3 S S F F F S F S Normalized V th 39

40 After Some Retention Loss DF Fast-leaking cells have lower V th P2 P3 Slow-leaking cells have higher V th S S F F F S F S Normalized V th 40

41 Eventually: Retention Failure DF P2 OPT P3 S S F F F F S S Normalized V th 41

42 Retention Failure Recovery (RFR) Key idea: Guess original state of the cell from its leakage speed property Three steps 1. Identify risky cells 2. Identify fast-/slow-leaking cells 3. Guess original states 42

43 OPT σ OPT OPT+σ 1. Identify Risky Cells DF Risky + S = P2 cells + F = P3 Key Formula S F F S Normalized V th 43

44 OPT σ OPT OPT+σ 2. Identifying Fast- vs. Slow-Leaking Cells DF Risky + S = P2 cells + F = P3 Key Formula???? Normalized V th 44

45 OPT σ OPT OPT+σ 2. Identifying Fast- vs. Slow-Leaking Cells DF Risky + S = P2 cells + F = P3 Key Formula S??? F?? F S? Normalized V th 45

46 3. Guess Original States DF Risky + S = P2 cells + F = P3 Key Formula S F F S Normalized V th 46

47 RFR Evaluation Program with random data 28 days Expect to eliminate 50% of raw bit errors ECC can correct remaining errors Detect failure, backup data Recover data 12 addt l. days 47

48 To understand the effects of retention loss: - Characterize retention loss using real chips Goal 1: Design a low-cost mechanism that dynamically finds the optimal read reference voltage Goal 2: Design an offline mechanism to recover data after detecting uncorrectable errors 48

49 Conclusion Problem: Retention loss reduces flash lifetime Overall Goal: Extend flash lifetime at low cost Flash Characterization: Developed an understanding of the effects of retention loss in real chips Retention Optimized Reading: A low-cost mechanism that dynamically finds the optimal read reference voltage 64% lifetime, 70.4% read latency Retention Failure Recovery: An offline mechanism that recovers data after detecting uncorrectable errors Raw bit error rate 50%, reduces data loss 49

50 Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Yu Cai, Yixin Luo, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *LSI Corporation 50

51 Backup Slides 51

52 RFR Motivation Data loss can happen in many ways 1. High P/E cycle 2. High temperature accelerates retention loss 3. High retention age (lost power for a long time) 52

53 What if there are other errors? Key: RFR does not have to correct all errors Example: ECC can correct 40 errors in a page Corrupted page has 20 retention errors, 25 other errors (45 total errors) After RFR: 10 retention errors, 30 other errors (40 total errors ECC correctable) 53

54 Threshold voltage mean Threshold Voltage (V th ) Mean P1 P2 P3 Relatively constant Slowly decrease Quickly decrease Finding: V th shifts faster in higher voltage states 54

55 Raw Bit Error Rate (RBER) RBER gradually decreases as read reference voltage approaches the actual OPT Actual OPT Reading data with 7-day retention age. Finding: The actual OPT achieves the lowest RBER 55

56 Online Pre-Optimization Algorithm DF Case: V 0 < OPT V 0 OPT DF Case: V 0 > OPT OPT V 0 Normalized V th Normalized V th 56

57 Online Pre-Optimization Algorithm Periodically learn and record OPT for page 255 as per-block starting read reference voltage (V 0 ) Page 255 has the shortest retention age Other pages within the block have longer retention age and retention age will increase over time Step 1: Read with V ref = old V 0, record RBER Step 2: Decrease V ref =V ref ΔV * compare RBER Step 3: Increase V ref = V ref + ΔV compare RBER Step 4: Record new V 0 = V ref minimal RBER * ΔV is the smallest step size for changing read reference voltage. 57

58 Naive Read-Retry Latency Diagnosis II Read page A (Stage-0): Attempt 1 time Flash Read Latency ECC Latency = Constant Raw bit error * Observation: Average ECC latency RBER * We provide detailed analysis of ECC latency in the paper. 58

59 Arrhenius Law 1 year Room temperature (20 C) 32 hours High temperature (70 C) High temperature accelerates retention loss 59

60 Average V th shift Fast- and Slow-Leaking Cells Slow-leaking cells Ends up in higher V th Fast-leaking cells Ends up in higher V th (-,-3σ) (-3σ,-2σ) (-2σ,-1σ) (-1σ,μ) (μ,1σ) (1σ,2σ) (2σ,3σ) (3σ,+ ) Retention age (days) * Similar trends are found in P2 state, as shown in the paper. 60

61 Fast- and Slow-Leaking Cells DF Threshold voltage marks after 28 days: -3σ -2σ -1σ μ 1σ 2σ 3σ Normalized V th 61

62 Average V th shift Fast- and Slow-Leaking Cells Slow-leaking cells Ends up in lower V th Fast-leaking cells Ends up in higher V th (-,-3σ) (-3σ,-2σ) (-2σ,-1σ) (-1σ,μ) (μ,1σ) (1σ,2σ) (2σ,3σ) (3σ,+ ) Retention age (days) * Similar trends are found in P2 state, as shown in the paper. 62

63 CG Control gate (CG) FG Inter-poly oxide Floating gate (FG) S Substrate D Tunnel oxide Source Drain Substrate 63