How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime?

Size: px
Start display at page:

Download "How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime?"

Transcription

1 How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime? Jiangpeng Li *, Kai Zhao *, Xuebin Zhang *, Jun Ma, Ming Zhao, and Tong Zhang * * Rensselaer Polytechnic Institute Shanghai Jiao Tong University Florida International University

2 NAND Flash Memory Bit cost reduction Price/GB Lifetime 2

3 Damage of NAND Flash memory cell q Damage to the NAND Flash memory cell Floating gate Oxide Electrons Oxide layer becomes thinner Number of electrons held in floating gate is reduced P/E cycling causes Charge trap : Damage to memory cell q Threshold voltage distribution overlap 3

4 Method to improve the lifetime Solid State drive Data Program NAND Read Data Log-Structured File system Damage causes limited lifetime Flash Translation Layer Data manipulation data compression Error Correction Coding Data compressibility NAND Uncompressed data Compressed data NAND Saved space Lifetime 4

5 Data compression in NAND Flash Data compressibility :α? Lifetime extends: 1/α q Unused space in one NAND Flash page One sector data Physical NAND Flash page data compression q Impact of compression ratio variance Unused space Minimize{damage} Compressed data Unused space Type-III Lower page Upper page wordline uncompressed data compressed data Type-I Type-II MLC NAND Flash wordline 5

6 Content-dependent damage characteristics Floating gate Oxide Electrons Floating gate State Lower page Upper page Erase 1 1 P1 P2 P V th Ø Electrons quantity differentiate the damage of data patterns Ø NAND Flash memory experiences content-dependent memory damage Ø Damage of data pattern: pattern 11 < pattern 10 < pattern 00 < pattern 01 6

7 Content-dependent damage: test result Raw BER Pattern content 11 Pattern content 10 Pattern content 00 Pattern content 01 Random pattern content P/E cycles x nm MLC NAND Flash chip 7

8 Unused space filling strategies Lower page Compressed data l head Unused space Type- III S (l) : Unused space in lower page S (u) : Unused space in upper page b l : lower page bit in memory cell k b u : upper page bit in memory cell k Upper page Unused space filling rule: Type- III Type- I Type- II b () l Ø If and (Type-III) l S b b Set ; l u = b = 1 u S ( u) Increase pattern 11 and 10 ; Decrease random data pattern and 01 Unidirectional data layout (UD) b () l Ø If and (Type-II-a) b l S b = 1 Set ; l () l b u S ( u) Ø If and (Type-II-b) l S b Set. l = b u b u S ( u) 8

9 Bidirectional data layout q Bidirectional data layout (BD): To reduce the percentage of random data pattern (Type-I) Compressed data Unused space l head Lower page Upper page Type- II Type- III Type- I Type- II 9

10 Conditional data exchange l head Type- III Compressed data Unused space l head Type- III Lower page Upper page Damage is reduced Type- III Type- I Type- II Type- III Type- I Type- II Type-II: pattern 11 or 00 Type-II: pattern 11 or 10 damage of 10 < damage of 00 q Conditional data exchange: exchange the compressed lower page data with upper page data to ensure the compressed lower page data has larger unused space May introduce extra overhead for FTL 10

11 Explicit compression and implicit compression q Conventional compressed data storage : Explicit compression Ø Complicate FTL/file system design q Implicit compression : A transparent data compression stored method Compressed data sector Unused space Compared with non-compression storage, the number of data sector in one Flash page is not increased Ø Transparent to FTL and file system, simplify system design Ø Sacrifice data compressibility and damage reduction 11

12 Damage factor of data pattern q 20nm MLC NAND Flash test results BER tolerance limitation η η 11 max r max q Damage Factor ρ i : Measure the damage of data pattern i η ρi = η ( r) max i max 12

13 Mathematical model to evaluate Flash lifetime : Model input : Model output Compressed data length in one page : ( e) C S Data compressibility (mean, variance) Mathematical model Lower page Upper page Compressed data Type- III Type- I Type- II Unused space Type- III After t P/E cycles, NAND Flash memory device survival probability Mathematical model Block survival probability Distribution of Mathematical model Damage factor of data patterns Distribution of memory cell damage per P/E Mathematical model ( e) C S Wordline survival probability Mathematical model NAND Flash physical parameters 13

14 Simulation results q Selected data compressibility (LZ77 compression algorithm, 4kB data sector length) 14

15 Simulation results q Lifetime improvement by data compression storage techniques DLL Text EXE XML 15

16 Impact of data compression ratio mean q Compression ratio standard deviation fixes at 0.01 Lifetime gain exp+ud exp+bd exp+udc exp+bdc imp+ud imp+bd imp+udc imp+bdc Compression ratio mean 16

17 Impact of data compression deviation q Compression ratio mean fixes at 0.5 Lifetime gain exp+ud exp+bd exp+udc exp+bdc imp+ud imp+bd imp+udc imp+bdc Compression ratio variance 17

18 Conclusion q Research on the employing data compressibility to reduce NAND Flash physical damage, in order to improve memory lifetime Ø Ø Ø Ø Content-dependent damage feature of MLC NAND Flash to reduce damage from data program and erase. A set of design strategies to exploit unused space from data compression in order to minimize the overall memory damage. File system/ftl-friendly implicit compression as a complementary of conventional explicit compression. Mathematical model to evaluate NAND Flash memory lifetime based on the data compressibility. 18

Reducing Solid-State Storage Device Write Stress Through Opportunistic In-Place Delta Compression

Reducing Solid-State Storage Device Write Stress Through Opportunistic In-Place Delta Compression Reducing Solid-State Storage Device Write Stress Through Opportunistic In-Place Delta Compression Xuebin Zhang, Jiangpeng Li, Hao Wang, Kai Zhao and Tong Zhang xuebinzhang.rpi@gmail.com ECSE Department,

More information

Could We Make SSDs Self-Healing?

Could We Make SSDs Self-Healing? Could We Make SSDs Self-Healing? Tong Zhang Electrical, Computer and Systems Engineering Department Rensselaer Polytechnic Institute Google/Bing: tong rpi Santa Clara, CA 1 Introduction and Motivation

More information

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch February 6, 2017

More information

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension DPA: A data pattern aware error prevention technique for NAND flash lifetime extension *Jie Guo, *Zhijie Chen, **Danghui Wang, ***Zili Shao, *Yiran Chen *University of Pittsburgh **Northwestern Polytechnical

More information

Reducing MLC Flash Memory Retention Errors through Programming Initial Step Only

Reducing MLC Flash Memory Retention Errors through Programming Initial Step Only Reducing MLC Flash Memory Retention Errors through Programming Initial Step Only Wei Wang 1, Tao Xie 2, Antoine Khoueir 3, Youngpil Kim 3 1 Computational Science Research Center, San Diego State University

More information

SLC vs MLC: Considering the Most Optimal Storage Capacity

SLC vs MLC: Considering the Most Optimal Storage Capacity White Paper SLC vs MLC: Considering the Most Optimal Storage Capacity SLC vs MLC: Considering the Most Optimal Storage Capacity P. 1 Introduction Proficiency should be a priority for the storage in computers.

More information

PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash

PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash Abstract: With aggressive scaling and multilevel cell technology, the reliability of NAND flash continuously degrades.

More information

Improving the Reliability of Chip-Off Forensic Analysis of NAND Flash Memory Devices. Aya Fukami, Saugata Ghose, Yixin Luo, Yu Cai, Onur Mutlu

Improving the Reliability of Chip-Off Forensic Analysis of NAND Flash Memory Devices. Aya Fukami, Saugata Ghose, Yixin Luo, Yu Cai, Onur Mutlu Improving the Reliability of Chip-Off Forensic Analysis of NAND Flash Memory Devices Aya Fukami, Saugata Ghose, Yixin Luo, Yu Cai, Onur Mutlu 1 Example Target Devices for Chip-Off Analysis Fire damaged

More information

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *Seagate Technology

More information

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Yu Cai, Yixin Luo, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *LSI Corporation 1 Many use

More information

HeatWatch Yixin Luo Saugata Ghose Yu Cai Erich F. Haratsch Onur Mutlu

HeatWatch Yixin Luo Saugata Ghose Yu Cai Erich F. Haratsch Onur Mutlu HeatWatch Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness Yixin Luo Saugata Ghose Yu Cai Erich F. Haratsch Onur Mutlu Storage Technology Drivers

More information

NAND Flash: Where we are, where are we going?

NAND Flash: Where we are, where are we going? NAND Flash: Where we are, where are we going? Pranav Kalavade Intel Corporation Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary Cell Size [um

More information

SLC vs. MLC: An Analysis of Flash Memory

SLC vs. MLC: An Analysis of Flash Memory SLC vs. MLC: An Analysis of Flash Memory Examining the Quality of Memory: Understanding the Differences between Flash Grades Table of Contents Abstract... 3 Introduction... 4 Flash Memory Explained...

More information

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation YIXIN LUO, Carnegie Mellon University SAUGATA GHOSE, Carnegie Mellon University YU CAI, SK Hynix, Inc. ERICH

More information

Improving Min-sum LDPC Decoding Throughput by Exploiting Intra-cell Bit Error Characteristic in MLC NAND Flash Memory

Improving Min-sum LDPC Decoding Throughput by Exploiting Intra-cell Bit Error Characteristic in MLC NAND Flash Memory Improving Min-sum LDPC Decoding Throughput by Exploiting Intra-cell Bit Error Characteristic in MLC NAND Flash Memory Wenzhe Zhao, Hongbin Sun, Minjie Lv, Guiqiang Dong, Nanning Zheng, and Tong Zhang Institute

More information

NAND Controller Reliability Challenges

NAND Controller Reliability Challenges NAND Controller Reliability Challenges Hanan Weingarten February 27, 28 28 Toshiba Memory America, Inc. Agenda Introduction to NAND and 3D technology Reliability challenges Summary 28 Toshiba Memory America,

More information

When it comes to double-density Flash memory, some pairs are just better.

When it comes to double-density Flash memory, some pairs are just better. MirrorBit Flash When it comes to double-density Flash memory, some pairs are just better. AMD pairs high-performance with reliability in a single Flash memory cell, with revolutionary results. Introducing

More information

Flash type comparison for SLC/MLC/TLC and Advantech s Ultra MLC technology

Flash type comparison for SLC/MLC/TLC and Advantech s Ultra MLC technology Flash type comparison for SLC/MLC/TLC and Advantech s Ultra MLC technology Author: Andy Chen, Product Engineer, Advantech Corporation Introduction Flash memory is a non-volatile storage element that can

More information

Improving LDPC Performance Via Asymmetric Sensing Level Placement on Flash Memory

Improving LDPC Performance Via Asymmetric Sensing Level Placement on Flash Memory Improving LDPC Performance Via Asymmetric Sensing Level Placement on Flash Memory Qiao Li, Liang Shi, Chun Jason Xue Qingfeng Zhuge, and Edwin H.-M. Sha College of Computer Science, Chongqing University

More information

NAND Flash Memory. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University

NAND Flash Memory. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University NAND Flash Memory Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) Flash

More information

White Paper: Increase ROI by Measuring the SSD Lifespan in Your Workload

White Paper: Increase ROI by Measuring the SSD Lifespan in Your Workload White Paper: Using SMART Attributes to Estimate Drive Lifetime Increase ROI by Measuring the SSD Lifespan in Your Workload Using SMART Attributes to Estimate Drive Endurance The lifespan of storage has

More information

SSD (Solid State Disk)

SSD (Solid State Disk) SSD (Solid State Disk) http://en.wikipedia.org/wiki/solid-state_drive SSD (Solid State Disk) drives Most SSD drives gives very good performance 4x ~ 100x No noise, low weight, power and heat generation

More information

Flash memory talk Felton Linux Group 27 August 2016 Jim Warner

Flash memory talk Felton Linux Group 27 August 2016 Jim Warner Flash memory talk Felton Linux Group 27 August 2016 Jim Warner Flash Memory Summit Annual trade show at Santa Clara Convention Center Where there is money, trade shows follow. August 8 11, 2016 Borrowing

More information

NAND flash memory must use error correction code (ECC)

NAND flash memory must use error correction code (ECC) 2412 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 60, NO. 9, SEPTEMBER 2013 Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead Guiqiang

More information

S-FTL: An Efficient Address Translation for Flash Memory by Exploiting Spatial Locality

S-FTL: An Efficient Address Translation for Flash Memory by Exploiting Spatial Locality S-FTL: An Efficient Address Translation for Flash Memory by Exploiting Spatial Locality Song Jiang, Lei Zhang, Xinhao Yuan, Hao Hu, and Yu Chen Department of Electrical and Computer Engineering Wayne State

More information

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Carnegie Mellon University Research Showcase @ CMU Department of Electrical and Computer Engineering Carnegie Institute of Technology 6-2015 Read Disturb Errors in MLC NAND Flash Memory: Characterization,

More information

Technical Notes. Considerations for Choosing SLC versus MLC Flash P/N REV A01. January 27, 2012

Technical Notes. Considerations for Choosing SLC versus MLC Flash P/N REV A01. January 27, 2012 Considerations for Choosing SLC versus MLC Flash Technical Notes P/N 300-013-740 REV A01 January 27, 2012 This technical notes document contains information on these topics:...2 Appendix A: MLC vs SLC...6

More information

Wear Leveling Static, Dynamic and Global. White paper CTWP013

Wear Leveling Static, Dynamic and Global. White paper CTWP013 Wear Leveling Static, Dynamic and Global White paper CTWP013 Cactus Technologies Limited Suite C, 15/F, Capital Trade Center 62 Tsun Yip Street, Kwun Tong Kowloon, Hong Kong Tel: +852-2797-2277 Email:

More information

A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks

A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks Jinho Seol, Hyotaek Shim, Jaegeuk Kim, and Seungryoul Maeng Division of Computer Science School of Electrical Engineering

More information

HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness

HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness Yixin Luo Saugata Ghose Yu Cai Erich F. Haratsch Onur Mutlu Carnegie Mellon University

More information

Advanced Information Storage 11

Advanced Information Storage 11 Advanced Information Storage 11 Atsufumi Hirohata Department of Electronics 16:00 11/November/2013 Monday (P/L 002) Quick Review over the Last Lecture Shingled write recording : * Bit patterned media (BPM)

More information

Data Organization and Processing

Data Organization and Processing Data Organization and Processing Indexing Techniques for Solid State Drives (NDBI007) David Hoksza http://siret.ms.mff.cuni.cz/hoksza Outline SSD technology overview Motivation for standard algorithms

More information

WHITE PAPER. Title What kind of NAND flash memory is used for each product? ~~~ Which is suitable SD card from reliability point of view?

WHITE PAPER. Title What kind of NAND flash memory is used for each product? ~~~ Which is suitable SD card from reliability point of view? Panasonic SD memory card White Paper Number : 002 Issue Date : 25-March-2015 Rev : 1.00 Title What kind of NAND flash memory is used for each product? ~~~ Which is suitable SD card from reliability point

More information

Optimizing Translation Information Management in NAND Flash Memory Storage Systems

Optimizing Translation Information Management in NAND Flash Memory Storage Systems Optimizing Translation Information Management in NAND Flash Memory Storage Systems Qi Zhang 1, Xuandong Li 1, Linzhang Wang 1, Tian Zhang 1 Yi Wang 2 and Zili Shao 2 1 State Key Laboratory for Novel Software

More information

arxiv: v2 [cs.ar] 5 Jan 2018

arxiv: v2 [cs.ar] 5 Jan 2018 1 Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery YU CAI, SAUGATA GHOSE Carnegie Mellon University arxiv:1711.11427v2 [cs.ar] 5 Jan 2018 ERICH F. HARATSCH Seagate Technology

More information

Flash ( p.531)

Flash ( p.531) Introduction to CMOS VLSI Design Flash (12.4.3.531) J. J. Nahas and P. M. Kogge Modified from slides by Jay Brockman 2008, 2015,2018 [Including slides from Harris & Weste, Ed 4, Adated from Mary Jane Irwin

More information

Differential RAID: Rethinking RAID for SSD Reliability

Differential RAID: Rethinking RAID for SSD Reliability Differential RAID: Rethinking RAID for SSD Reliability Mahesh Balakrishnan Asim Kadav 1, Vijayan Prabhakaran, Dahlia Malkhi Microsoft Research Silicon Valley 1 The University of Wisconsin-Madison Solid

More information

Improved Error Correction Capability in Flash Memory using Input / Output Pins

Improved Error Correction Capability in Flash Memory using Input / Output Pins Improved Error Correction Capability in Flash Memory using Input / Output Pins A M Kiran PG Scholar/ Department of ECE Karpagam University,Coimbatore kirthece@rediffmail.com J Shafiq Mansoor Assistant

More information

Sub-block Wear-leveling for NAND Flash

Sub-block Wear-leveling for NAND Flash IBM Research Zurich March 6, 2 Sub-block Wear-leveling for NAND Flash Roman Pletka, Xiao-Yu Hu, Ilias Iliadis, Roy Cideciyan, Theodore Antonakopoulos Work done in collaboration with University of Patras

More information

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives This paper reviews the most recent advances in solid-state drive (SSD) error characterization, mitigation, and

More information

I/O Devices & SSD. Dongkun Shin, SKKU

I/O Devices & SSD. Dongkun Shin, SKKU I/O Devices & SSD 1 System Architecture Hierarchical approach Memory bus CPU and memory Fastest I/O bus e.g., PCI Graphics and higherperformance I/O devices Peripheral bus SCSI, SATA, or USB Connect many

More information

Designing with External Flash Memory on Renesas Platforms

Designing with External Flash Memory on Renesas Platforms Designing with External Flash Memory on Renesas Platforms Douglas Crane, Segment Manager Micron Technology Class ID: CL23A Renesas Electronics America Inc. Douglas Crane Doug is a 27 year veteran in the

More information

arxiv: v3 [cs.ar] 22 Sep 2017

arxiv: v3 [cs.ar] 22 Sep 2017 Appears in Proceedings of the IEEE, September 2017. Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives Yu Cai Saugata Ghose Erich F. Haratsch Yixin Luo Onur Mutlu

More information

Read Disturb Characterization for Next-Generation Flash Systems

Read Disturb Characterization for Next-Generation Flash Systems Gary Tressler, Tom Griffin and Patrick Breen IBM Corporation August 2015 1 Agenda Industry Trend Background Mixed Mode Analysis Influence of Environment / Flash Access Mode Read Disturb Tolerance vs. Technology

More information

From Silicon to Solutions: Getting the Right Memory Mix for the Application

From Silicon to Solutions: Getting the Right Memory Mix for the Application From Silicon to Solutions: Getting the Right Memory Mix for the Application Ed Doller Numonyx CTO Flash Memory Summit 2008 Legal Notices and Important Information Regarding this Presentation Numonyx may

More information

FLASH DATA RETENTION

FLASH DATA RETENTION FLASH DATA RETENTION Document #AN0011 Viking Rev. B Purpose of this Document This application note was prepared to help OEM system designers evaluate the performance of Viking solid state drive solutions

More information

Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems Sensors 214, 14, 18851-18877; doi:1.339/s14118851 Article OPEN ACCESS sensors ISSN 1424-822 www.mdpi.com/journal/sensors Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND

More information

Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns

Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns March 12, 2018 Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns Wen Wen Lei Zhao, Youtao Zhang, Jun Yang Executive Summary Problems: performance and reliability of write operations

More information

FPGA Programming Technology

FPGA Programming Technology FPGA Programming Technology Static RAM: This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters and uses a standard CMOS process. The configuration cell drives the gates of

More information

REAL: A Retention Error Aware LDPC Decoding Scheme to Improve NAND Flash Read Performance

REAL: A Retention Error Aware LDPC Decoding Scheme to Improve NAND Flash Read Performance REAL: A Retention Error Aware LDPC Decoding Scheme to Improve NAND Flash Read Performance Meng Zhang, Fei Wu* Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology,

More information

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook. Pranav Kalavade Intel Corporation

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook. Pranav Kalavade Intel Corporation NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook Pranav Kalavade Intel Corporation pranav.kalavade@intel.com October 2012 Outline Flash Memory Product Trends Flash Memory Device Primer

More information

Pseudo SLC. Comparison of SLC, MLC and p-slc structures. pslc

Pseudo SLC. Comparison of SLC, MLC and p-slc structures. pslc 1 Pseudo SLC In the MLC structures, it contains strong pages and weak pages for 2-bit per cell. Pseudo SLC (pslc) is to store only 1bit per cell data on the strong pages of MLC. With this algorithm, it

More information

Flash Memory. Gary J. Minden November 12, 2013

Flash Memory. Gary J. Minden November 12, 2013 Flash Memory Gary J. Minden November 12, 2013 1 Memory Types Static Random Access Memory (SRAM) Register File Cache Memory on Processor Dynamic Random Access Memory (DRAM, SDRAM) Disk Solid State Disk

More information

Optimize your system designs using Flash memory

Optimize your system designs using Flash memory Optimize your system designs using Flash memory Howard Cheng Sr. Segment Applications Manager Embedded Solutions Group, Micron 2012 Micron Technology, Inc. All rights reserved. Products are warranted only

More information

A File-System-Aware FTL Design for Flash Memory Storage Systems

A File-System-Aware FTL Design for Flash Memory Storage Systems 1 A File-System-Aware FTL Design for Flash Memory Storage Systems Po-Liang Wu, Yuan-Hao Chang, Po-Chun Huang, and Tei-Wei Kuo National Taiwan University 2 Outline Introduction File Systems Observations

More information

2 Asst Prof, ECE Dept, Kottam College of Engineering, Chinnatekur, Kurnool, AP-INDIA.

2 Asst Prof, ECE Dept, Kottam College of Engineering, Chinnatekur, Kurnool, AP-INDIA. www.semargroups.org ISSN 2319-8885 Vol.02,Issue.06, July-2013, Pages:480-486 Error Correction in MLC NAND Flash Memories Based on Product Code ECC Schemes B.RAJAGOPAL REDDY 1, K.PARAMESH 2 1 Research Scholar,

More information

Solid State Drives (SSDs) Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Solid State Drives (SSDs) Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University Solid State Drives (SSDs) Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Memory Types FLASH High-density Low-cost High-speed Low-power High reliability

More information

Increasing NAND Flash Endurance Using Refresh Techniques

Increasing NAND Flash Endurance Using Refresh Techniques Increasing NAND Flash Endurance Using Refresh Techniques Yu Cai 1, Gulay Yalcin 2, Onur Mutlu 1, Erich F. Haratsch 3, Adrian Cristal 2, Osman S. Unsal 2 and Ken Mai 1 DSSC, Carnegie Mellon University 1

More information

DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives

DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives Ren-Shuo Liu and Jian-Hao Huang System and Storage Design Lab Department of Electrical Engineering

More information

Content courtesy of Wikipedia.org. David Harrison, CEO/Design Engineer for Model Sounds Inc.

Content courtesy of Wikipedia.org. David Harrison, CEO/Design Engineer for Model Sounds Inc. Content courtesy of Wikipedia.org David Harrison, CEO/Design Engineer for Model Sounds Inc. Common FLASH Memory SD cards + mini, micro versions serial interface slower Compact Flash - parallel interface

More information

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University NAND Flash-based Storage Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics NAND flash memory Flash Translation Layer (FTL) OS implications

More information

Chapter 12 Wear Leveling for PCM Using Hot Data Identification

Chapter 12 Wear Leveling for PCM Using Hot Data Identification Chapter 12 Wear Leveling for PCM Using Hot Data Identification Inhwan Choi and Dongkun Shin Abstract Phase change memory (PCM) is the best candidate device among next generation random access memory technologies.

More information

Improving NAND Endurance by Dynamic Program and Erase Scaling

Improving NAND Endurance by Dynamic Program and Erase Scaling Improving NAND Endurance by Dynamic Program and Erase Scaling Jaeyong Jeong, Sangwook Shane Hahn, Sungjin Lee, and Jihong Kim Department of Computer Science and Engineering, Seoul National University,

More information

CS311 Lecture 21: SRAM/DRAM/FLASH

CS311 Lecture 21: SRAM/DRAM/FLASH S 14 L21-1 2014 CS311 Lecture 21: SRAM/DRAM/FLASH DARM part based on ISCA 2002 tutorial DRAM: Architectures, Interfaces, and Systems by Bruce Jacob and David Wang Jangwoo Kim (POSTECH) Thomas Wenisch (University

More information

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy.

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 4, 7 Memory Overview, Memory Core Cells Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM

More information

Holistic Flash Management for Next Generation All-Flash Arrays

Holistic Flash Management for Next Generation All-Flash Arrays Holistic Flash Management for Next Generation All-Flash Arrays Roman Pletka, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Haris Pozidis, Sasa Tomic IBM Research Zurich Aaron

More information

NAND Flash Basics & Error Characteristics

NAND Flash Basics & Error Characteristics NAND Flash Basics & Error Characteristics Why Do We Need Smart Controllers? Thomas Parnell, Roman Pletka IBM Research - Zurich Santa Clara, CA 1 Agenda Part I. NAND Flash Basics Device Architecture (2D

More information

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery

Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery Carnegie Mellon University Research Showcase @ CMU Department of Electrical and Computer Engineering Carnegie Institute of Technology 2-2015 Data Retention in MLC NAND Flash Memory: Characterization, Optimization,

More information

Understanding SSD overprovisioning

Understanding SSD overprovisioning Understanding SSD overprovisioning Kent Smith, LSI Corporation - January 8, 2013 The over-provisioning of NAND flash memory in solid state drives (SSDs) and flash memory-based accelerator cards (cache)

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 8 Dr. Ahmed H. Madian ah_madian@hotmail.com Content Array Subsystems Introduction General memory array architecture SRAM (6-T cell) CAM Read only memory Introduction

More information

A Caching-Oriented FTL Design for Multi-Chipped Solid-State Disks. Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo

A Caching-Oriented FTL Design for Multi-Chipped Solid-State Disks. Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo A Caching-Oriented FTL Design for Multi-Chipped Solid-State Disks Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo 1 June 4, 2011 2 Outline Introduction System Architecture A Multi-Chipped

More information

GANGRENE: Exploring the Mortality of Flash Memory

GANGRENE: Exploring the Mortality of Flash Memory GANGRENE: Exploring the Mortality of Flash Memory Naval Surface Warfare Center, Crane Division Indiana University Apu Kapadia Indiana University Flash memory is ubiquitous http://www.flickr.com/photos/sucello/6220857499/

More information

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory 1 Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory Yixin Luo, Saugata Ghose, Yu Cai, Erich F Haratsch, Onur Mutlu Abstract NAND flash memory is a widely-used

More information

POWER ANALYSIS RESISTANT SRAM

POWER ANALYSIS RESISTANT SRAM POWER ANALYSIS RESISTANT ENGİN KONUR, TÜBİTAK-UEKAE, TURKEY, engin@uekae.tubitak.gov.tr YAMAN ÖZELÇİ, TÜBİTAK-UEKAE, TURKEY, yaman@uekae.tubitak.gov.tr EBRU ARIKAN, TÜBİTAK-UEKAE, TURKEY, ebru@uekae.tubitak.gov.tr

More information

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University NAND Flash-based Storage Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics NAND flash memory Flash Translation Layer (FTL) OS implications

More information

A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs

A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs Li-Pin Chang, Chia-Hsiang Cheng, and Kai-Hsiang Lin Department of Computer Science National Chiao-Tung University, Taiwan Presented

More information

High Performance and Highly Reliable SSD

High Performance and Highly Reliable SSD High Performance and Highly Reliable SSD -Proposal of the Fastest Storage with B4-Flash - Moriyoshi Nakashima GENUSION,Inc http://www.genusion.co.jp/ info@genusion.co.jp Santa Clara, CA 1 Big Data comes

More information

+1 (479)

+1 (479) Memory Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Memory Arrays Memory Arrays Random Access Memory Serial

More information

At first glance, using an external flash device with

At first glance, using an external flash device with Dave Hughes, CEO, HCC Embedded Rapidly Advancing Flash is a Double-Edged Sword for Embedded IoT Though more-enriched flash brings a number of benefits to an IoT application, it also often creates challenges

More information

Flash Trends: Challenges and Future

Flash Trends: Challenges and Future Flash Trends: Challenges and Future John D. Davis work done at Microsoft Researcher- Silicon Valley in collaboration with Laura Caulfield*, Steve Swanson*, UCSD* 1 My Research Areas of Interest Flash characteristics

More information

Flash Memory Overview: Technology & Market Trends. Allen Yu Phison Electronics Corp.

Flash Memory Overview: Technology & Market Trends. Allen Yu Phison Electronics Corp. Flash Memory Overview: Technology & Market Trends Allen Yu Phison Electronics Corp. 25,000 20,000 15,000 The NAND Market 40% CAGR 10,000 5,000 ($Million) - 2001 2002 2003 2004 2005 2006 2007 2008 2009

More information

CSCI 350 Ch. 12 Storage Device. Mark Redekopp Michael Shindler & Ramesh Govindan

CSCI 350 Ch. 12 Storage Device. Mark Redekopp Michael Shindler & Ramesh Govindan 1 CSCI 350 Ch. 12 Storage Device Mark Redekopp Michael Shindler & Ramesh Govindan 2 Introduction Storage HW limitations Poor randomaccess Asymmetric read/write performance Reliability issues File system

More information

FLASH memory has been widely employed in both consumer

FLASH memory has been widely employed in both consumer Every 100 s 1 Using Dynamic Allocation of Write Voltage to Extend Flash Memory Lifetime Haobo Wang, Student Member, IEEE, Nathan Wong, Student Member, IEEE, Tsung-Yi Chen, Member, IEEE, and Richard D.

More information

Don t Let RAID Raid the Lifetime of Your SSD Array

Don t Let RAID Raid the Lifetime of Your SSD Array Don t Let RAID Raid the Lifetime of Your SSD Array Sangwhan Moon Texas A&M University A. L. Narasimha Reddy Texas A&M University Abstract Parity protection at system level is typically employed to compose

More information

COMPUTER ARCHITECTURE

COMPUTER ARCHITECTURE COMPUTER ARCHITECTURE 8 Memory Types & Technologies RA - 8 2018, Škraba, Rozman, FRI Memory types & technologies - objectives 8 Memory types & technologies - objectives: Basic understanding of: The speed

More information

Storage Systems : Disks and SSDs. Manu Awasthi July 6 th 2018 Computer Architecture Summer School 2018

Storage Systems : Disks and SSDs. Manu Awasthi July 6 th 2018 Computer Architecture Summer School 2018 Storage Systems : Disks and SSDs Manu Awasthi July 6 th 2018 Computer Architecture Summer School 2018 Why study storage? Scalable High Performance Main Memory System Using Phase-Change Memory Technology,

More information

Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures

Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Prof. Lei He EE Department, UCLA LHE@ee.ucla.edu Partially supported by NSF. Pathway to Power Efficiency and Variation Tolerance

More information

Tutorial FTL. Sejun Kwon Computer Systems Laboratory Sungkyunkwan University

Tutorial FTL. Sejun Kwon Computer Systems Laboratory Sungkyunkwan University Tutorial FTL Sejun Kwon Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Contents NAND Flash Memory NAND Flash Operation NAND Flash Architecture NAND Controller Tutorial FTL ICE3028:

More information

Performance and Reliability Study and Exploration of NAND Flash-based Solid State Drives

Performance and Reliability Study and Exploration of NAND Flash-based Solid State Drives Virginia Commonwealth University VCU Scholars Compass Theses and Dissertations Graduate School 2013 Performance and Reliability Study and Exploration of NAND Flash-based Solid State Drives Guanying Wu

More information

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University NAND Flash-based Storage Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics NAND flash memory Flash Translation Layer (FTL) OS implications

More information

Purity: building fast, highly-available enterprise flash storage from commodity components

Purity: building fast, highly-available enterprise flash storage from commodity components Purity: building fast, highly-available enterprise flash storage from commodity components J. Colgrove, J. Davis, J. Hayes, E. Miller, C. Sandvig, R. Sears, A. Tamches, N. Vachharajani, and F. Wang 0 Gala

More information

Quasi-Cyclic Non-Binary LDPC Codes for MLC NAND Flash Memory

Quasi-Cyclic Non-Binary LDPC Codes for MLC NAND Flash Memory for MLC NAND Flash Memory Ahmed Hareedy http://www.loris.ee.ucla.edu/ LORIS Lab, UCLA http://www.uclacodess.org/ CoDESS, UCLA Joint work with: Clayton Schoeny (UCLA), Behzad Amiri (UCLA), and Lara Dolecek

More information

3D NAND Assessment for Next Generation Flash Applications

3D NAND Assessment for Next Generation Flash Applications ** Patrick Breen, ** Tom Griffin, * Nikolaos Papandreou, * Thomas Parnell, ** Gary Tressler * IBM Research Zurich, Switzerland ** IBM Systems Poughkeepsie, NY, USA IBM Corporation August 2016 1 Agenda

More information

Self-Adaptive NAND Flash DSP

Self-Adaptive NAND Flash DSP Self-Adaptive NAND Flash DSP Wei Xu 2018/8/9 Outline NAND Flash Data Error Recovery Challenges of NAND Flash Data Integrity A Self-Adaptive DSP Technology to Improve NAND Flash Memory Data Integrity 6

More information

Improving Performance and Lifetime of Solid-State Drives Using Hardware-Accelerated Compression

Improving Performance and Lifetime of Solid-State Drives Using Hardware-Accelerated Compression 1732 IEEE Transactions on Consumer Electronics, Vol. 57, No. 4, November 2011 Improving Performance and Lifetime of Solid-State Drives Using Hardware-Accelerated Compression Sungjin Lee, Jihoon Park, Kermin

More information

Improving MLC flash performance and endurance with Extended P/E Cycles

Improving MLC flash performance and endurance with Extended P/E Cycles Improving MLC flash performance and endurance with Extended P/E Cycles Fabio Margaglia, André Brinkmann Johannes Gutenberg University, Mainz, Germany Motivation Flash wear out is dependent on the number

More information

NAND/MTD support under Linux

NAND/MTD support under Linux 12 July 2012 NAND Features 1 Flash is everywhere NAND Features non-volatile computer storage chip that can be electrically erased and reprogrammed usb flash drives memory cards solid-state drives Flash

More information

An LDPC-Enabled Flash Controller in 40 nm CMOS

An LDPC-Enabled Flash Controller in 40 nm CMOS An LDPC-Enabled Flash Controller in 40 nm CMOS Marvell Semiconductor Engling Yeo Santa Clara, CA 1 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara,

More information

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014 http://dx.doi.org/10.5573/jsts.2014.14.5.537 Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge

More information

Tutorial FTL. Jinyong Computer Systems Laboratory Sungkyunkwan University

Tutorial FTL. Jinyong Computer Systems Laboratory Sungkyunkwan University Tutorial FTL Jinyong Ha(jinyongha@csl.skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Contents NAND Flash Memory NAND Flash Operation NAND Flash Configuration NAND Controller

More information