Flash Memory. Gary J. Minden November 12, 2013

Transcription

1 Flash Memory Gary J. Minden November 12,

2 Memory Types Static Random Access Memory (SRAM) Register File Cache Memory on Processor Dynamic Random Access Memory (DRAM, SDRAM) Disk Solid State Disk (SSD) Magnetic Tape 2

3 TI 512KW by 32-bits (16 Mb) 3

4 SRAM Signals Address to read or write -- A[18:0] Data -- DQ[31:0] Chip Enables -- E1Z and E2 Write Enable -- WZ Output Enable -- GZ SMV512K32 has four control inputs called chip enable-1 (E1Z), chip enable-2 (E2), write enable (WZ) and output enable (GZ); 19 address inputs A[18:0] and a 32-bit bidirectional data bus DQ[31:0]. E1Z and E2 enable control device selection, active and stand-by modes (with and without scrub). WZ controls read and write operations. During read operation, GZ must be asserted to enable the outputs. 4

5 Generic SRAM Block Address WrtEnb OutEnb ChipEnb1 ChipEnb2 Data 5

6 Wider Memory Address WrtEnb OutEnb ChipEnb1 ChipEnb2 Data 2x Data Bits Data 6

7 Deeper Memory Address Address[19] WrtEnb OutEnb ChipEnb1 ChipEnb2 Data 2x Words 7

8 Dual-Ported SRAM CY7C006A 8

9 Error Detection and Control The SMV512K32 is a radiation hardened SRAM It includes an error detection and control circuit Supports single error correction/double error detection 9

10 Flash and SSD 10

11 Flash and SSDs Flash technology SSDs Interface to SSDs 11

12 Basic Floating Gate Structure Drain Gate Source Metal-Oxide- Semiconductor (MOS) Field Effect Transistor (FET) (MOSFET) Two gates, center one is floating or insulated. 12

13 Basic Floating Gate Structure 3.3 V 0 V Gate 3.3 V Drain Source When Gate is positive with respect to Drain, a channel is formed between Source and Drain 13

14 Programming 12 V 0 V Gate 3.3 V Drain Source Apply high voltage to Gate Charge is injected onto the floating gate Charge remains on the floating gate when programming voltage removed because it is insulated MOSFET is ON Erasing is similar using a 0 V Gate voltage and 12 V Source voltage 14

15 Two Structures NAND and NOR 15

16 Reading NAND Flash 16

17 Flash Structure Features NAND Erasing and programming times are shorter High capacity data storage High cell densities Requires flash management SRAM based byte-serial interface NOR Interface is similar to SRAM Fast access Execute directly from flash memory 17

18 Flash Reliability Issues Bit-flipping 0 -> 1 or 1 -> 0 Requires Error Correcting Codes (more powerful than the Hamming Code) Bad-Blocks NAND flash chips are shipped with bad-blocks Must scan device before use Must keep track (manage) bad blocks Keeps chip cost low Endurance Number of program/erase cycles NAND ~ 1M NOR ~ 100K Retention 18

19 Flash Failure Modes Program/Erase Cycling Charge trapped in dielectric Permanent change in cell characteristics Observed is failed program or erase status Blocks that fail should be retired Data Retention Charge loss/gain on floating gate Cell can be erased/programmed without problems Related to number of erase/program cycles 19

20 NAND Interface 20

21 Micron MT29Exxx Features 21

22 NAND Organization 22

23 Array Organization 23

24 LUNs per Package 24

25 Array Organization Page 8K data bytes 448 ECC bytes Block 256 Pages 2,048 KB (2 MB) Data 112 KB ECC Plane 2,048 Blocks 4 GB Data 234 MB ECC LUN 2 Planes Package 2 LUNs 16 GB 25

26 NAND Characteristics Erasure is at Block level, 2 MB Write Operation Read entire Block into Cache Update Page in Cache Write entire Block into storage array Leads to Log-based file systems Higher Capacity NAND Flash Single Level Cell -- Each cell hold 1 bit Multiple Level Cell -- Each cell holds 2 bits Triple Level Cell -- Each cell holds 3 bits 26

27 Flash Signals 27

28 Flash Command Cycle 28

29 Flash Address Transfer 29

30 Flash Write Transfer 30

31 Flash Read Transfer 31

32 Flash Commands 32

33 Flash Commands 33

34 Flash Commands 34

35 Flash Package (VBGA) Dimensions 35

36 Micron MT29F1 Serial Flash 36

37 SPI Flash Architecture 37

38 SPI Flash Memory Array 38

39 SPI Flash Memory Map 39

40 SSD Block Diagram 40

41 Solid State Drives Physical Interface same as Hard Disk Drives SATA 3-6 bps Physical Form Factor same as Hard Disk Drives 2.5 inch and 1.8 inch On-board embedded processor manages Logical Block Address to Physical Page Mapping Write-leveling -- spread erase/write operations across all Blocks Logging File System -- collect writes to any file in one Block before writing to storage array 41

42 SSD Typical Performance 42

43 Seagate Momentus Laptop HDD 43