Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Transcription

1 Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *Seagate Technology

2 Executive Summary Read disturb errors limit flash memory lifetime today Apply a high pass-through voltage (V pass )to multiple pages on a read We characterize read disturb on real NAND flash chips Slightly lowering V pass greatly reduces read disturb errors Some flash cells are more prone to read disturb Technique 1: Mitigate read disturb errors online V pass Tuning dynamically finds and applies a lowered V pass Flash memory lifetime improves by 21% Technique 2: Recover after failure to prevent data loss Read Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errors Reduces raw bit error rate (RBER) by up to 36% 2

3 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 3

4 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 4

5 NAND Flash Memory Background Page 0 Page 1 Page 2 Read Pass Pass Page 256 Page 257 Page 258 Flash Memory Page M Page M+1 Page M+2 Block 0 Block 1 Block N Page 255 Pass Page 511 Page M+255 Flash Controller 5

6 Column Flash Cell Array Block X Row Page Y Sense Amplifiers Sense Amplifiers 6

7 Flash Cell Floating Gate Drain Gate V th = 2.5 V Source Floating Gate Transistor (Flash Cell) 7

8 Flash Read V read = 2.5 V V th = V read = 2.5 V V th = 2 V 3V Gate 1 0 8

9 Flash Pass-Through V pass = 5 V V th = 2 V Gate V pass = 5 V V th = 3V 1 1 9

10 Read from Flash Cell Array V pass = 5.0 V Pass (5V) 3.0V 3.8V 3.9V 4.8V Page 1 V read = 2.5 V Read (2.5V) 3.5V 2.9V 2.4V 2.1V Page 2 V pass = 5.0 V Pass (5V) 2.2V 4.3V 4.6V 1.8V Page 3 V pass = 5.0 V Pass (5V) 3.5V 2.3V 1.9V 4.3V Page 4 Correct values for page 2: 10

11 Read Disturb Problem: Weak Programming Effect Pass (5V) 3.0V 3.8V 3.9V 4.8V Page 1 Pass (5V) 3.5V 2.9V 2.4V 2.1V Page 2 Read (2.5V) 2.2V 4.3V 4.6V 1.8V Page 3 Pass (5V) 3.5V 2.3V 1.9V 4.3V Page 4 Repeatedly read page 3 (or any page other than page 2) 11

12 Read Disturb Problem: Weak Programming Effect V pass = 5.0 V 3.0V 3.8V 3.9V 4.8V Page 1 V read = 2.5 V 3.5V 2.9V 2.4V 2.6V 2.1V Page 2 V pass = 5.0 V 2.2V 4.3V 4.6V 1.8V Page 3 V pass = 5.0 V 3.5V 2.3V 1.9V 4.3V Page 4 Incorrect values from page 2: High pass-through voltage induces weak-programming effect 12

13 Read disturb errors: Reading from one page can alter the values stored in other unread pages Goal: Mitigate and Recover Read Disturb Errors 13

14 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 14

15 Methodology FPGA-based flash memory testing platform [Cai+, FCCM 11] Real 20- to 24-nm MLC NAND flash chips 0 to 1M read disturbs 0 to 15K Program/Erase Cycles (PEC) 15

16 PDF Read Disturb Effect on V th Distribution (No Read Disturbs) 0.25M Read Disturbs 0.5M Read Disturbs 1M Read Disturbs ER state P1 state V th gradually increases with read disturb counts P2 state P3 state Normalized Threshold Voltage 16

17 Other Experimental Observations Lower threshold voltage states are affected more by read disturb Wear-out increases read disturb effect 17

18 Normalized Tolerable Read Disturb Count Key Observation 1: Slightly lowering V pass greatly reduces read disturb errors Reducing The Pass-Through Voltage % 1% 2% 3% 4% 5% 6% Percentage of Vpass Reduction 18

19 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 19

20 Read Disturb Mitigation: V pass Tuning Key Idea: Dynamically find and apply a lowered V pass Trade-off for lowering V pass +Allows more read disturbs Induces more read errors 20

21 Read Errors Induced by V pass Reduction Reducing V pass to 4.9V V pass = 4.9 V 3.0V 3.8V 3.9V 4.8V Page 1 V read = 2.5 V 3.5V 2.9V 2.4V 2.1V Page 2 V pass = 4.9 V 2.2V 4.3V 4.6V 1.8V Page 3 V pass = 4.9 V 3.5V 2.3V 1.9V 4.3V Page

22 Read Errors Induced by V pass Reduction Reducing V pass to 4.7V V pass = 4.7 V 3.0V 3.8V 3.9V 4.8V Page 1 V read = 2.5 V 3.5V 2.9V 2.4V 2.1V Page 2 V pass = 4.7 V 2.2V 4.3V 4.6V 1.8V Page 3 V pass = 4.7 V 3.5V 2.3V 1.9V 4.3V Page 4 Incorrect values from page 2:

23 RBER Utilizing the Unused ECC Capability ECC Correction Capability Unused ECC capability N-day Retention 1. Huge unused ECC correction capability can be used to tolerate read errors 2. Unused ECC capability decreases over time Dynamically adjust V pass so that read errors fully utilize the unused ECC capability 23

24 V pass Reduction Trade-Off Summary Conservatively set V pass to a high voltage Accumulates more read disturb errors at the end of each refresh interval +No read errors Dynamically adjust V pass to unused ECC capability + Minimize read disturb errors ocontrol read errors to be tolerable by ECC oif read errors exceed ECC capability, read again with a higher V pass to correct read errors 24

25 V pass Tuning Steps Perform once for each block every day: 1. Estimate unused ECC capability 2. Aggressively reduce V pass until read errors exceeds ECC capability 3. Gradually increase V pass until read error just becomes less than ECC capability 25

26 Evaluation of V pass Tuning 19 real workload I/O traces Assume 7-day refresh period Similar methodology as before to determine acceptable V pass reduction Overhead for a 512 GB flash drive: 128 KB storage overhead for per-block V pass setting and worst-case page sec/day average V pass Tuning overhead 26

27 homes web-vm mail mds rsrch prn web stg ts proj src wdev usr postmark hm cello99 websearch financial prxy P/E Cycle Lifetime V pass Tuning Lifetime Improvements Baseline VVpass Tuning Average lifetime improvement: 21.0% 27

28 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 28

29 Read Disturb Resistance DF Disturb-Resistant R N read disturbs Disturb-Prone P N read disturbs Normalized V th 29

30 DF Observation 2: Some Flash Cells Are More Prone to Read Disturb After 250K read disturb: Disturb-prone cells have higher threshold voltages ER P1 Disturb-resistant cells have lower threshold voltages R P R Disturb-prone ER state P R P R Disturb-resistant P1 state P Normalized V th 30

31 Read Disturb Oriented Error Recovery (RDR) Triggered by an uncorrectable flash error Back up all valid data in the faulty block Disturb the faulty page 100K times (more) Compare V th s before and after read disturb Select cells susceptible to flash errors (V ref σ<v th <V ref σ) Predict among these susceptible cells Cells with more V th shifts are disturb-prone Higher V th state Cells with less V th shifts are disturb-resistant Lower V th state 31

32 RBER RDR Evaluation No Recovery RDR 0 0.2M 0.4M 0.6M 0.8M 1M Read Disturb Count Reduce total error counts up to 1M read disturbs ECC can be used to correct the remaining errors 32

33 Outline Background (Problem and Goal) Key Experimental Observations Mitigation: V pass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 33

34 Executive Summary Read disturb errors limit flash memory lifetime today Apply a high pass-through voltage (V pass )to multiple pages on a read We characterize read disturb on real NAND flash chips Slightly lowering V pass greatly reduces read disturb errors Some flash cells are more prone to read disturb Technique 1: Mitigate read disturb errors online V pass Tuning dynamically finds and applies a lowered V pass Flash memory lifetime improves by 21% Technique 2: Recover after failure to prevent data loss Read Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errors Reduces raw bit error rate (RBER) by up to 36% 34

35 Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *Seagate Technology

36 Raw Bit Error Rate (RBER) Slower Faster Read Disturb Induced RBER Increases Faster with Higher PEC K 40K 60K 80K 100K Read Disturb Count PEC Slope 15K K K K K K K

37 Norm. Vth Mean Norm. Vth Standard Deviation Threshold Voltage Increases with Read Disturb Count Read Disturb Count (Millions) Read Disturb Count (Millions) Showing results for P1 8K PEC, other states have similar trends 37

38 Norm. Vth Mean Norm. Vth Mean Lower Voltage States Are More Prone to Read Disturb ER State Read Disturb Count (Millions) P1 State Read Disturb Count (Millions) 38

39 RBER Reducing V pass Increases Tolerable Read Disturb % 99% 98% Count 97% 100% V pass 99% V pass 98% V pass 97% V pass 96% V pass 95% V pass 94% V pass Read Disturb Count 96% 95% 94% Pct. V pass Value 100% 99% 98% 97% 96% 95% 94% Rd. Disturb. Cnt. 1x 1.7x 6.8x 22x 100x 470x 1300x 39

40 Pass-Through Voltage Reduction Induced Read Error Addl. RBER Due to Reduced V pass day 1-day 2-day 6-day 9-day 17-day 21-day Relaxed V pass 40

41 Read Errors Induced by V pass Reduction Will generate a read error only if: Max(V th ) > V pass Correct read value is 1 These errors do not affect lifetime can usually be tolerated by the unused ECC capability These errors are temporary can be corrected (if necessary) by reading with the default V pass 41

42 Illustration of V pass Tuning Results 42

43 Some Flash Cells Are More Prone to Read Disturb Predict to be P1 state - Area I is correct - Area II is 50/50 Predict to be ER state - Area III is correct - Area IV is 50/50 Showing V th with 8K PEC from 250K to 350K read disturbs 43