SMIC PHY Spec. Single port 10/100 Fast Ethernet Transceiver

Transcription

1 SMIC PHY Spec. Single port 10/100 Fast Ethernet Transceiver 1. General Description: Octans is a single-port PHYceiver with an RMII (Reduce Media Independent Interface)/MII (Media Independent Interface) for 10M/100M modes and SNI (Serial Network Interface) for 10M mode. It implements all 10M/100M Ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Serial Management Interface (SMI). One can set the internal registers to configure Octans statuses by SMI (MDC/MDIO). With DSP technology, Octans provides excellent performance under all operating conditions. Octans can be integrated into many networking application chip, such as communication chips, network consumer chips, and so on. It has a much smaller area than other Ethernet PHYceivers and very suitable for SOC designs. In Octans, we also integrate PLL and 3.3V to 1.8V regulator. Besides Octans, we also provide TX/RX IO PAD for users integration. 2. Function Features: Support 10/100Mbps TX. Support Full-duplex and half-duplex mode. Support auto MDI/MDIX (auto-crossover) function with IEEE Fully compliant with IEEE 802.3/802.3u. Support IEEE 802.3u auto-negotiation in TX mode. Support MII / RMII / SMII interface. Support automatic receiving/transmitting power saving function. Support 25MHz/50MHz OSC/XTAL input PLL. 100M timing recovery and performance exceeds 110 meters for UTP 5. 10M timing recovery and performance exceeds 140 meters for UTP 5. Support 10M RX/TX jabber monitor functions. Support 10M auto polarity detection function. Support Interrupt function. Support repeater mode. Support Parallel/Serial LED display. Single 3.3V power supply with built-in 1.8V regulator. Embedded regulator can support more than 150mA current. DSP-based PHY Transceiver technology. Support flow control to communicate with other MAC through MDC and MDIO 0.18um, CMOS SMIC technology. Total chip current consumption is less than 80mA. Support dedicated TX/RX IO PAD for customers. Page 1 of 16

2 3. System Block: SMII RMII SMI MII RMII SMII to MII Converter MII RMII to MII Converter Register Set MII to RMII Auto-negotiation MII_RMII_SEL MUX 10M/100M MUX 4B to 5B Encoder De-screamble Manchaster code converter Parallel to Serial 100M 10M MLT3 to NRZI Timing recovery Screamble NRZI to Manchaster Code Timing recovery Polarity detection NRZI to MLT3 Encoder Line Driver Controller DSP filter Squelch D/A & Line Driver ADC & Comparator Aanalog Filter Bandpass Filter 4. Chip Size & FloorPlan: Page 2 of 16

3 5. PIN description: 5.1 Analog TX/RX Pin Name Pin Type Pin Description TXP I/O, MDI mode Twisted Pair Transmit Output Positive. It should be connected to Ethernet analog IO PAD TXN I/O, MDI mode Twisted Pair Transmit Output Negative. It should be connected to Ethernet analog IO PAD RXP I/O, MDI mode Twisted Pair Receive Output Positive. It should be connected to Ethernet analog IO PAD RXN I/O, MDI mode Twisted Pair Receive Output Negative. It should be connected to Ethernet analog IO PAD TRXP I/O, MDIX mode Twisted Pair Transmit Output Positive. It should be connected to Ethernet analog IO PAD TRXN I/O, MDIX mode Twisted Pair Transmit Output Negative. It should be connected to Ethernet analog IO PAD RRXP I/O, MDIX mode Twisted Pair Receive Output Positive. It should be connected to Ethernet analog IO PAD RRXN I/O, MDIX mode Twisted Pair Receive Output Negative. It should be connected to Ethernet analog IO PAD 5.2 Power Ground Pin Name Pin Type Pin Description A_GNDAD Analog Ground Analog Ground Pad A_GNDTX A_GND A_VDD33AD Analog Power Analog 3.3V Power A_VDD33TX A_VDD33 R_GND Regulator Ground 3.3V Regulator ground R_VDD33 Regulator Power 3.3V Regulator power in D_VDD18 1.8V Digital Power 1.8V digital power input D_GND Digital Ground Digital ground XTAL_VDD33 Crystal Power Crystal 3.3V VDD XTAL_VDD18 Crystal Power Crystal 1.8V VDD XTAL_GND Crystal Ground Crystal Ground POWER_OUT 1.8V regulator output: It can provide 150mA current. 5.3 MII/RMII Pin Name MII_TXC Pin Type Pin Description Output, MII Transmit Clock. 25M Clock output in 100BASE-X mode and 16mA 2.5M Clock output for 10BASE-T mode. This clock is continuously driven output and generated from XI. Before Speed is recognized, this pin drives out continuous 25M clock. RMII 25M Clock input. This signal output continuous 25M clock in RMII mode. Page 3 of 16

4 MII_TXD[3:0] Input MII Mode. Nibbe-wide transmit data stream in MII mode. These four bits are synchronous to the rising edge of TXCLK. RMII Mode. MII_TXD[1:0] for the di-bits that are transmitted and are driven synchronously to REFCLK. MII_TXD can change once per REFCLK cycle, whereas in 10Mb/s mode, MII_TXD must be held steady for 10 consecutive REFCLK cycles. MII_TXEN Input MII Mode. Transmit Enable to indicate that the data on TXD[3:0] is valid. RMII Mode. TXEN indicates that the di-bit on TXD is valid and it is driven synchronously to REFCLK. MII_RXC Output MII Receive Clock. 25M Clock output in 100BASE-X mode, 2.5M Clock output for 10BASE-T MII mode and 10M clock for 10BASE- T 1M8 mode. This clock is recovered from the received data on the cable input. Due to recovered from incoming receive data, it is possible that MII_RXC starts running yet MII_RXDV keeps low for a while. MII_RXDV/ CRSDV/ MII_RXD[3:0] MII_CRS MII_COL MII_RXER RMII 50M Clock Output. This pin outputs continuous 50M clock in RMII mode. To reduce the BOM cost for system application, user can connect this pin directly to REFCLK to proper RMII operation. Output MII Receive Data Valid. Active high signal to indicate that the data on MII_RXD[3:0] is valid. Synchronous to the rising edge of MII_RXC in MII mode. RMII Mode. Represents Receive Carrier Sense and Data Valid in RMII mode. CRSDV asserts when the receive medium is non-idle. The assertion of CRSDV is asynchronous to REFCLK. At the deassertion of carrier, CRSDV de-asserts synchronously to REFCLK only on the first di-bit of MII_RXD. If there is still data in the FIFO not yet presented onto RXD, then on the second di-bit of MII_RXD, CRSDV is asserted synchronously to REFCLK. The toggling of CRSDV on the first and second di-bit continues until all the data in the FIFO is presented onto MII_RXD. CRSDV is asserted for the duration of carrier activity for a false carrier event. Output MII Mode. Nibbe-wide receive data stream in MII mode. These four bits are synchronous to the rising edge of MII_RXC and MII_RXD[3] is the most significant bit. RMII Mode. MII_RXD[3:2] for the di-bits that are received and are driven synchronously to MII_RXC. MII_RXD[1] is the MSB. Note that in 100Mb/s mode, RXD can change once per REFCLK cycle, whereas in 10Mb/s mode, MII_RXD must be held steady for 10 consecutive MII_RXC cycles. Output MII Mode. This bit indicates that there is carrier sense presented on the medium. Note that in half duplex mode, this pin will also be asserted high under transmit condition. This pin is asynchronous to Output 4mA Output 4mA, MII_CLK. MII Collision. In half duplex mode, active high to indicate that there is collision on the medium. In full duplex mode, this pin will keep low all the time. MII/RMII Receive Error. Active high signal to indicate that there is error condition detected by Octans. Page 4 of 16

5 5.4 Serial Management Interface (SMI MDC/MDIO) Pin Name Pin Type Pin Description SMI_MDI Input Management Data Input. MDI transfers management data in which is synchronous to MDC. SMI_MDO output Management Data Output. MDO transfer management data out and which is synchronous to MDC. MDENX output Management Data Enable. 0: It receives data from SMI_MDI. 1: It transmits data to SMI_MDO. SMI_MDC output Management Data Reference Clock. A non-continuous clock input for management usage. It will use this clock to sample data input on MDIO and drive data onto MDIO according to rising edge of this clock. 5.5 Configuration Setting Pin Name Pin Type Pin Description RESET# Input Reset Signal. Active low signal. RMII_SEL Input RMII_SEL.: 0 : MII interface 1 : RMII interface MULTI_MODE Input MULTI_MODE. It should be connected to 1 b0. SPEED_100 Input SPEED_100. 0: 10M capability 1: 100M capability DUPLEX_FULL Input DUPLEX_FULL. 0: Half duplex 1: Full duplex AN_ENABLE Input AN_ENABLE. 0: Disable auto-negotiation function 1: Enable auto-negotiation function DULA_LED Input DUAL_LED. 0: Single color LED mode 1: Dual color LED mode POWER_DOWN Input POWER_DOWN. 0: Power up mode 1: Power down mode DRV_CTRL Input Drive Control 0: It cannot be power saving 1: It can be power saving PHY_ADDRESS[4:0] Input PHY_ADDRESS. It represents the 5 bits PHY address. They are from 5 h00 to 5 h1f to identify PHY. REG2[15:0] Input REG2: PHY identifier ID configurations. REG3[15:0] Input REG3: PHY identifier ID configurations. TEST_MODE[3:0] Input TEST_MODE. It should be connected to 4 h0. TEST_IN[5:0] Input TEST_IN. It should be connected to 5 h00. TEST_OUT[8:0] Output TEST_OUT. It should be floating. Page 5 of 16

6 5.5 DFT Setting Pin Name Pin Type Pin Description SCAN_ENABLE Input SCAN_ENABLE. 0: Normal mode operation 1: ATPG mode SCAN_MODE Input SCAN_MODE 0: Normal mode 1: ATPG mode SCAN_CLK Input SCAN_CLK For scan mode used 5.6 Output Pin Name Pin Type Pin Description LED0 Output, 16mA LED0. Active low (Note) 100ms (blink 100ms) to indicate that there is transmitting or receiving activity after Link Up. Keeps high all the time when link is failed. LED1 LED2 Outpu, 16mA Outpu, 16mA See Chapter 8. LED1. 0 : 100M 1 : 10M See Chapter 8. LED2. 0: Full duplex 1: Half duplex See Chapter Crystal Signal Pin Name Pin Type Pin Description X1 Input Crystal/Oscillator input. RMII_SEL = 0 : 25M Crystal/Oscillator Input. RMII _SEL = 1 : Leave unconnected X2 Output Crystal output. When 25M Oscillator is used, this pin should left unconnected. See XI/OSCI description CLK_50M_IN Input 50M Reference clock input. Function on this pin is highly depended upon the setting on RMII_SEL. When RMII_SEL is setting to high, the PLL will select the clock input as CLK_50M_IN. Otherwise, the PLL will select XI to be the clock source. CLK_50M_OUT Output 50M output. 50M clock output which is generated by PLL Page 6 of 16

7 5.8 Other Signal Pin Name Pin Type Pin Description CLK_125M_TEST Output, 24mA CLK_125M_TEST 125M clock output for jitter testing BIAS_RESISTOR Input BIAS_RESISTOR For Regulator s current resistor. It should be connected to a 26.4K resistor. ANA_TEST[1:0] Output It should be floating 6. Register description: Register 0 : MII Control Register 15 Reset When set, this action will bring both status and control registers of the PHY to default state. This bit is self-clearing. 1 = Software reset 0 = Normal operation 14 Loop-back This bit enables loop-back of transmit data to the receive data path, i.e., TXD to RXD. Octans requires at least 512us to link after programming this bit. TX/RX packets should be activated after 512us. 1 = enable loop-back 0 = normal operation 0, RW 0, RW 13 Speed Selection This bit sets the speed of transmission. 1 = 100Mbps 0 = 10Mbps During 100Base-FX mode, and when this bit = 1, it indicates read only. 1, RW 12 Auto-Negotiation Enable This bit determines the auto-negotiation function. 1 = enable auto-negotiation; bits 13 and 8 will be ignored. 0 = disable auto-negotiation; bits 13 and 0:<8> will determine the link speed and the data transfer mode, under this condition. When 100Base-FX mode is enabled, this bit is read only and read as 0. Auto-MDIX function should be disabled (set Reg16.11=1) if this bit has been set to 0. Please refer to section 7 Auto- MDIX function description for details. 11 Power Down This bit will turn down the power of the PHY chip and the internal crystal oscillator circuit if this bit is enabled. The MDC and MDIO are still activated for accessing to the MAC. 1 = power down 0 = normal operation 10 Isolate 1=electrically Isolate PHY from MII but not isolate MDC and MDIO 0=normal operation 1, RW (TP) 0, RO (FX) 0, RW 0,RW 9 Restart Auto- Negotiation This bit allows the auto-negotiation function to be reset. 1 = restart auto -negotiation 0 = normal operation 0, RW 8 Duplex Mode This bit sets the duplex mode if auto -negotiation is disabled (bit 12=0) 1 = full duplex 0 = half duplex After completing auto-negotiation, this bit will reflect the duplex status.(1: Full duplex, 0: Half duplex) When 100Base-FX mode is enabled, this bit can be set through the MDC/MDIO SMI interface or DUPLEX pin. 1, RW Page 7 of 16

8 7 Collision Test 1=enable COL signal test 0=disable COL signal test 0,RW 6:0 Reserved Register 1 : MII Status Register Base-T4 1 = enable 100Base-T4 support 0 = suppress 100Base-T4 support Base-TX Full Duplex BASE-TX Half Duplex 12 10Base-T Full Duplex 11 10_Base-T Half Duplex 1 = enable 100Base-TX full duplex support 0 = suppress 100Base-TX full duplex support 1 = enable 100Base-TX half duplex support 0 = suppress 100Base-TX half duplex support 1 = enable 10Base-T full duplex support 0 = suppress 10Base-T full duplex support 1 = enable 10Base-T half duplex support 0 = suppress 10Base-T half duplex support 1, RO 1, RO 1, RO 1, RO 10:7 Reserved 6 MF Preamble Suppression The Octans will accept management frames with preamble suppressed. The IP101A accepts management frames without preamble. A Minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as per IEEE802.3u specifications 1, RO 5 Auto-Negotiation Complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 4 Remote Fault 1 = remote fault condition detected (cleared on read) 0 = no remote fault condition detected When in 100Base-FX mode, this bit means an in-band signal Far-End-Fault is detected. 3 Auto- 1 = Link had not been experienced fail state Negotiation 0 = Link had been experienced fail state 2 Link Status 1 = valid link established 0 = no valid link established 1 Jabber Detect 1 = jabber condition detected 0 = no jabber condition detected 0 Extended Capability 1 = extended register capability 0 = basic register capability only 0, RO/L H 1, RO 0, RO/L L 0, RO/L H 1, RO Register 4 : Auto-Negotiation Advertisement Register 15 NP Next Page bit. 0 = transmitting the primary capability data page 1 = transmitting the protocol specific data page 14 Reserved 13 RF 1 = advertise remote fault detection capability 0 = do not 0, RW advertise remote fault detection capability 12 Reserved 11 Asymmetric. 1 = asymmetric flow control is supported by local node 0 = 0, RW Pause asymmetric flow control is NOT supported by local node 10 Pause 1 = flow control is supported by local node 0 = flow control is NOT supported by local node 0, RW Page 8 of 16

9 9 T4 1 = 100Base-T4 is supported by local node 0 = 100Base-T4 not supported by local node 8 TX Full Duplex 1 = 100Base-TX full duplex is supported by local node 0 = 100Base-TX full duplex not supported by local node 7 TX 1 = 100Base-TX is supported by local node 0 = 100Base-TX not supported by local node 6 10 Full Duplex 1 = 10Base-T full duplex supported by local node 0 = 10Base- T full duplex not supported by local node = 10Base-T is supported by local node 0 = 10Base-T not supported by local node 4:0 Selector Binary encoded selector supported by this node. Currently only CSMA/CD <00001> is specified. No other protocols are supported. 1, RW 1, RW 1, RW 1, RW <0000 1>, RO Register 5 : Auto-Negotiation Link Partner Ability Register 15 Next Page Next Page bit. 0 = transmitting the primary capability data page 1 = transmitting the protocol specific data page 14 Acknowledge 1 = link partner acknowledges reception of local node s capability data word 0 = no acknowledgement 13 Remote Fault 1 = link partner is indicating a remote fault 0 = link partner does not indicate a remote fault 12 Reserved 11 Asymmetric. 1 = asymmetric flow control is supported by local node Pause 0 = asymmetric flow control is NOT supported by local node 10 Pause 1 = flow control is supported by Link partner 0 = flow control is NOT supported by Link partner 9 T4 1 = 100Base-T4 is supported by link partner 0 = 100Base-T4 not supported by link partner 8 TXFD 1 = 100Base-TX full duplex is supported by link partner 0 = 100Base-TX full duplex not supported by link partner 7 100BASE-TX 1 = 100Base-TX is supported by link partner 0 = 100Base-TX not supported by link partner This bit will also be set after the link in 100Base is established by parallel detection. 6 10FD 1 = 10Base-T full duplex is supported by link partner 0 = 10Base-T full duplex not supported by link partner 5 10Base-T 1 = 10Base-T is supported by link partner 0 = 10Base-T not supported by link partner This bit will also be set after the link in 10Base is established by parallel detection. 4:0 Selector Link Partner s binary encoded node selector Currently only CSMA/CD <00001> is specified <0000 0>, RO Register 6 : Auto-Negotiation Expansion Register 15:5 Reserved This bit is always set to 0. 4 MLF This status indicates if a multiple link fault has occurred. 1 = fault occurred 0 = no fault occurred Page 9 of 16

10 3 LP_NP_AB LE This status indicates if the link partner supports Next Page negotiation. 1 = supported 0 = not supported 2 NP_ABLE This bit indicates if the device is able to send additional Next Pages. 1 PAGE_RX This bit will be set if a new link code word page has been received. It is cleared automatically after the auto-negotiation link partner s ability register (register 5) is read by the management. 0 LP_NW_A BLE 1 = link partner supports auto-negotiation. Register 16 : PHY Spec. Control Register 15:10 Reserved 9 Jabber Enable Jabber function enable at 10Base-T 0, R/W 8 Far-End Fault Enable/Disable 7 Analog Power Saving Disable To enable or disable the functionality of Far-End Fault Mode Enable Disable 100Base-TX 1 0 0, R/W 100Base-FX 0 1 Set high to disable the power saving during auto-negotiation 0, R/W 6:3 Reserved 2 Repeater Mode Set high to put Octans into repeater mode 0, R/W 1 APS Mode Set high to enable Auto Power Saving mode 0, R/W 0 Analog Off Set high to power down analog transceiver 0, R/W Register 17 : Interrupt Register 15:10 Reserved Reserved 9 XOVER_ CHANGE Cross Over mode Changed Interrupt Enable 8 SPEED_ CHANGE Speed Changed Interrupt Enable 7 DUPLEX_ CHANGE Duplex Changed Interrupt Enable 6 PAGE_ RX Page Received Interrupt Enable 5 LINK_CHANGE Link Status Changed Interrupt Enable 4 SYMBOL_ CHANGE Symbol Error Interrupt Enable Page 10 of 16

11 3 FCAR_ CHANGE False Carrier Interrupt Enable 2 TX_JAB_ CHANGE Transmit Jabber Interrupt Enable 1 RX_JAB_ CHANGE Receive Jabber Interrupt Enable 0 ESD_ERROR_INT Error End of Stream Enable Register 18 : PHY Status Register 15:12 Reserved Reserved 9 MEDIUM Medium_Detect Signal 8:0 Reserved 0 : Medium_Off 1 : Medium_On 7. Timing Diagram REFCLK CRSDV RXD Data Data Data Data Data Data Data Data Data RXER Carrier Sense Detected Preamble SFD Carrier Deasserted Data Figure 2. RMII Reception Without Error REFCLK CRSDV_P RXD_P RXER_P Carrier Sense Detected Carrier Deasserted False Carrier Detected False Carrier Figure 3. RMII Reception with False Carrier (100M Only) Page 11 of 16

12 REFCLK CRSDV_P RXD_P Data Data RXER_P Carrier Sense Detected RX Error Detected Error Data Carrier Deasserted Figure 4. RMII Reception with Symbol Error REFCLK CRSDV RXD Data Data Preamble/SFD Transition once every 10 cycles Data Transition once every 10 cycles Figure 5. 10M RMII Receive Diagram REFCLK TXEN TXD[1:0] Data Data Data Data Data Data Data Data Data Preamble SFD Data gure M RMII Transmit Diagram Fi REFCLK TXEN_P TXD_P Data Data Preamble/SFD Transition once every 10 cycles Data Transition once every 10 cycles Figure 7. 10M RMII Transmit Diagram Page 12 of 16

13 8. LED Descriptions Single Color LED When Single Color LED is programmed (DUALLED is set to low during power on reset), all ports LED will be Off during power on reset (Output value same as recommend value on LED pins). After power on reset, all internal parallel LEDs will be On for 2 seconds, internal parallel LED status will be streamed out through LED_DATA and this signal is output by AD2107 at the falling edge of LED_CLK. Before describing the serial LED output data format, we tend to describe the meaning of internal parallel LEDs. There are two types of LED supported by Apus internally. The first is LINK_ADCTIVITY, which represents the status of Link and Transmit/Receive Activity; the second is SPEED, which indicates the speed status and the last is DUPLEX_COLLISION, which shows pure duplex status in full duplex and duplex/collision combined status in half duplex. After LED self test, following tables, show the On/Off polarity according to different recommended value setting for SPEED, DUPLEX_COLLISION and LINK_ADCTIVITY. When the recommend value is high, it will drive LED LOW; it will drive the LED HIGH when the recommend value is low, instead. SPEED SPEED 10M 0 100M 1 LINK FAIL 1 DUPLEX DUPLEX_COLLISION HALF FULL LINK UP Blink (HIGH) When Collision LOW All the Time LINK FAIL HIGH All the Time HIGH All the Time SPEED LINK_ADCTIVITY Link Activity LINK UP LOW Blink (HIGH) When RX/TX LINK FAIL HIGH All the Time HIGH All the Time Table 1. Activity/Link LED Display Dual Color LED After LED self test, following tables show the On/Off polarity according to different speed detected by Apus. DUPCOL is always set to single color mode display no matter the value of DUALLED is. SPEED SPEED 10M 0 100M 1 LINK FAIL 1 Page 13 of 16

14 Table 2. Speed LED Display SPEED LINK_ACTIVITY Link Activity 100M LINK UP LOW Blink (HIGH) When RX/TX 10M LINK_UP HIGH Blink (LOW) When RX/TX LINK FAIL HIGH All the Time HIGH All the Time 9. SMI Description Management Register Access The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The Apus is designed to support an MDC frequency specified in the IEEE specification of up to 2.5 MHz. The MDIO line is bidirectional and may be shared by up to 32 devices. The MDIO pin requires a 1.5 KΩ pull-up which, during idle and turnaround periods, will pull MDIO to a logic one state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous logic one bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-of-frame field indicated by a <01> pattern. The next field signals the operation code (OP) : <10> indicates read from MII management register operation, and <01> indicates write to MII management register operation. The next two fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most significant bit is transferred first. During Read operation, a 2-bit turnaround (TA) time spacing between the register address field and data field is provided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written into the MII management registers of the Octans. Preamble Suppression Apus supports a preamble suppression mode as indicated by an 1 in bit 6 of the basic mode status register (Register 1h). If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management entity needs not generate preamble for each management transaction. It requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by pulling-up the resistor of MDIO. While the Octans will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. When Octans detects that there is physical address match, then it will enable Read/Write capability for external access. When neither physical address nor register address is matched, then it will tri-state the MDIO pin. Page 14 of 16

15 MDC MDIO (MAC) MDIO (PHY) z z z Preamble Start Opcode (Read) PHY Address (5'h0C in this example) Register Address (5'h00 in this example) TA Register Data (16'h1300 in this Example) Reset Operation The Octans can be reset either by hardware or software. A hardware reset is accomplished by applying a negative pulse, with a duration of at least 400 ms to the RC pin of the Octans during normal operation to guarantee internal Power On Reset Circuit is reset well. A software reset is activated by setting the reset bit in the basic mode control register (bit 15, register 0h). This bit is self-clearning and, when set, will return a value of 1 until the software reset operation has completed, please note that internal SRAM will not be reset during software reset. MDC MDIO (MAC) z z Preamble Start Opcode (Write) PHY Address (5'h0C in this example) Register Address (5'h00 in this example) TA Register Data (16'h1300 in this Example) Hardware reset operation samples the pins and initializes all registers to their default values. This process includes re-evaluation of all hardware configurable registers. A hardware reset affects the PHY in the device. A software reset can reset an individual PHY and it does not latch the external pins nor reset the registers to their respective default value. Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of Octans. Some of these pins are used as output ports after reset operation. 10. PLL Description Octans has its own embedded PLL (Phase Lock Loop) circuit. The PLL circuit can provide 10MHz, 25MHz, 50MHz, 100MHz, 125MHz, and 200MHz clocks to baseband or other circuits. As long as other circuits need these frequencies to operate, one can easily connect these clock sources to the design. Page 15 of 16

16 11. Regulator Description Octans has its own embedded regulators which converts the input voltage from 3.3V to 1.8V. In Octans, it contains analog regulator, PLL regulator, and digital regulator. In PLL regulator, it can provide 50mA current at most. They can provide 100mA and 200mA in analog and digital regulators, respectively. In user s design, the regulators can also provide enough current for their ASIC designs easily. Page 16 of 16