AES, DES, and RSA Support (Intended for Domestic Use) SASEBO-W Smart Card OS Specification
|
|
|
- Allison Conley
- 5 years ago
- Views:
Transcription
1 AES, DES, and RSA Support (Intended for Domestic Use) SASEBO-W Smart Card OS Specification Version April 1, 2011 National Institute of Advanced Industrial Science and Technology (AIST)
2 Table of Contents 1. Overview Electrical Specifications Anwer To Reset (ATR) Application Protocol Data Unit (APDU) AES Commands MAKE_AES_KEY ENCRYPT_AES DECRYPT_AES DES Commands MAKE_DES_KEY ENCRYPT_DES DECRYPT_DES RSA Commands LOAD_RSA_EXP LOAD_RSA_CRT_EXP LOAD_RSA_CRT_EXP LOAD_RSA_MOD LOAD_RSA_CRT_PRM LOAD_RSA_CRT_PRM LOAD_RSA_CRT_COEF MAKE_RSA_KEY ENCRYPT_RSA Other Common Commands GET_RESPONSE NOP ECHO
3 ATR Command Sequences AES Encryption AES Decryption DES Encryption DES Decryption RSA Encryption[[Only the encryption sequence seems to be given]] RSA-CRT Decryption Test Sequences NOP ECHO AES Encryption AES Decryption DES Encryption DES Decryption RSA Encryption RSA Decryption RSA-CRTDecryption Cryptographic Algorithms AES Encryption (Byte-oriented) AES Decryption (Byte-oriented) AES Encryption (Hardware-like) AES Decryption (Hardware-like) DES Encryption and Decryption RSA Encryption and Decryption RSA Encryption and Decryption (Equal Timing) RSA-CRT Decryption
4 1. Overview SASEBO-W Smart Card OS provides software implementations of cryptographic algorithms. This operating system is installed on an ISO/IEC contact card that includes an 8-bit Atmel AVR microcontroller, ATmega163. The SASEBO-W Smart Card OS supports the following cryptographic algorithms. Advance Encryption Standard (AES-)128-bit encryption and decryption Data Encryption Standard (DES) encryption and decryption Rivest, Shamir and Adleman (RSA) 32-bit encryption and decryption Figure 1 : Card Schematic (Top View) Figure 2 : Internal Equivalent Circuit 4
5 2. Electrical Specifications The hardware interface specifications of the ATmega microcontroller that contains SASEBO-W Smart Card OS are given below. Table 1 : Card Interface Specifications Parameter Value Transfer protocol T = 0 Clock frequency MHz Transfer bit rate 9600 bps C1:VCC C2:RST C3:CLK C4:AUX1 C5:GND C6:VPP C7:I/O C8:AUX2 Figure 3 : Assignments of Card Contacts and Functions (Top View) Table 2 : Pin Assignments Contact Function Direction Description C1 VCC Power C2 RST In Reset (negative logic) C3 CLK In Clock C4 AUX1 Out EXEC (pin driven high during processing) C5 GND Ground C6 VPP Unused C7 I/O In/Out Serial data (open drain) C8 AUX2 Out Unused Other electrical specifications conform to the Atmel ATmega163 specifications. 5
6 3. Answer To Reset (ATR) SASEBO-W Smart Card OS returns the ATR as follows. 0x3B 0xAE 0x00 0x40 0x32 0x73 0x61 0x53 0x65 0x42 0x4F 0x32 0x30 0x31 0x30 0x31 0x32 0x30 0x31 Table 3 : ATR Format Offset Data Element Value Description 0 TS 0x3B Direct convention 1 T0 0xAE TB1 & TD1 sent (0xA) Number of historical characters = 14 (0xE) 2 TB1 0x00 VPP contact is not used (II = 0, PI1 = 0) 3 TD1 0x40 TC2 sent (0x4) Transmission protocol T = 0 (0x0) 4 TC2 0x32 Work waiting time = ms (WI = 50 (0x32)) 5 18 Historical characters sasebo Identification & version number 6
7 4. Application Protocol Data Unit (APDU) SASEBO-W Smart Card OS supports the following APDU commands (Terminal Smart Card). Table 4 : APDU Command List Command CLA INS P1 P2 P3 Data Response MAKE_AES_KEY 0x80 0x12 0x00 0x00 0x10 Key Status ENCRYPT_AES 0x80 0x04 0x04 0x?? 0x10 Plaintext Status DECRYPT_AES 0x80 0x08 0x04 0x?? 0x10 Ciphertext Status MAKE_DES_KEY 0x80 0x0A 0x00 0x00 0x08 Key Status ENCRYPT_DES 0x80 0x04 0x00 0x00 0x08 Plaintext Status DECRYPT_DES 0x80 0x08 0x00 0x00 0x08 Ciphertext Status LOAD_RSA_EXP 0x80 0x00 0x00 0x00 0x04 Key Status LOAD_RSA_CRT_EXP1 0x80 0x00 0x01 0x00 0x02 Key Status LOAD_RSA_CRT_EXP2 0x80 0x00 0x02 0x00 0x02 Key Status LOAD_RSA_MOD 0x80 0x02 0x00 0x00 0x04 Key Status LOAD_RSA_CRT_PRM1 0x80 0x02 0x01 0x00 0x02 Key Status LOAD_RSA_CRT_PRM2 0x80 0x02 0x02 0x00 0x02 Key Status LOAD_RSA_CRT_COEF 0x80 0x02 0x03 0x00 0x02 Key Status MAKE_RSA_KEY 0x80 0x06 0x00 0x00 0x00 Status ENCRYPT_RSA 0x80 0x04 0x01 0x?? 0x04 Plaintext Status GET_RESPONSE 0x80 0xc0 0x00 0x00 length Data + Status NOP 0x80 0x80 0x00 0x00 0x00 Status ECHO 0x80 0x82 0x00 0x00 length Any data Status ATR 0x80 0x84 0x00 0x00 0x00 Status The list of status words in the response APDU (Smart Card Terminal) is given in the following table. Status 0x9000 0x9F?? 0x6D00 0x6E00 0x6A86 0x6700 Table 5 : Status List Description OK without response data OK with response data (length = 0x??) Bad INS Bad CLS Bad P1 or P2 Bad P3 7
8 8
9 4.1. AES Commands MAKE_AES_KEY The MAKE_AES_KEY command sets the AES key. This command must be re-issued after issuing commands to other cryptographic algorithms. Command: CLA INS P1 P2 P3 Data 0x80 0x12 0x00 0x00 0x10 Key (16-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 9
10 ENCRYPT_AES The ENCRYPT_AES command executes AES encryption. A response is returned upon completion of AES encryption. The AES algorithm can be specified in the P2 value. Details of the algorithms are described in Section 7, Cryptographic Algorithms. Command: CLA INS P1 P2 P3 Data 0x80 0x04 0x04 0x?? 0x10 Plaintext (16-byte) P2: P2 0x00 0x01 Algorithm Byte-oriented implementation Hardware-like implementation Response: SW1 SW2 Description 0x9F 0x10 Successfully executed (16-byte Ciphertext is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 10
11 DECRYPT_AES The DECRYPT_AES command executes AES decryption. A response is returned upon completion of AES decryption. The AES algorithm can be specified in the P2 value. Details of the algorithms are given in Section 7, Cryptographic Algorithms. Command: CLA INS P1 P2 P3 Data 0x80 0x08 0x04 0x?? 0x10 Ciphertext (16-byte) P2: P2 0x00 0x01 Algorithm Byte-oriented implementation Hardware-like implementation Response: SW1 SW2 Description 0x9F 0x10 Successfully executed (16-byte Plaintext is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 11
12 4.2. DES Commands MAKE_DES_KEY The MAKE_DES_KEY command sets the DES key. This command must be re-issued after issuing commands to other cryptographic algorithms. Command: CLA INS P1 P2 P3 Data 0x80 0x0A 0x00 0x00 0x08 Key (8-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 12
13 ENCRYPT_DES The ENCRYPT_DES command executes DES encryption. A response is returned upon completion of DES encryption. Command: CLA INS P1 P2 P3 Data 0x80 0x04 0x00 0x00 0x08 Plaintext (8-byte) Response: SW1 SW2 Description 0x9F 0x08 Successfully executed (8-byte ciphertext is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 13
14 DECRYPT_DES The DECRYPT_DES command executes DES decryption. A response is returned upon completion of DES decryption. Command: CLA INS P1 P2 P3 Data 0x80 0x08 0x00 0x00 0x08 Ciphertext (8-byte) Response: SW1 SW2 Description 0x9F 0x08 Successfully executed (8-byte plaintext is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 14
15 4.3. RSA Commands LOAD_RSA_EXP The LOAD_RSA_EXP command sets the RSA exponent. This command must be re-issued after issuing commands to other algorithms (include RSA-CRT). Command: CLA INS P1 P2 P3 Data 0x80 0x00 0x00 0x00 0x04 Exponent (4-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 15
16 LOAD_RSA_CRT_EXP1 The LOAD_RSA_CRT_EXP1 command sets the first exponent of RSA-CRT. This command must be re-issued after issuing commands to other cryptographic algorithms (including RSA). Command: CLA INS P1 P2 P3 Data 0x80 0x00 0x01 0x00 0x02 Exponent (2-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 16
17 LOAD_RSA_CRT_EXP2 The LOAD_RSA_CRT_EXP2 command sets the second exponent of RSA-CRT. This command must be re-issued after issuing commands to other cryptographic algorithms (including RSA). Command: CLA INS P1 P2 P3 Data 0x80 0x00 0x02 0x00 0x02 Exponent (2-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 17
18 LOAD_RSA_MOD The LOAD_RSA_EXP command sets the RSA modulus. This command must be re-issued after issuing commands to other algorithms (including RSA-CRT). Command: CLA INS P1 P2 P3 Data 0x80 0x02 0x00 0x00 0x04 Modulus (4-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 18
19 LOAD_RSA_CRT_PRM1 The LOAD_RSA_CRT_PRM1 command sets the first prime of RSA-CRT. This command must be re-issued after issuing commands to other cryptographic algorithms (include RSA). Command: CLA INS P1 P2 P3 Data 0x80 0x02 0x01 0x00 0x02 Prime (2-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 19
20 LOAD_RSA_CRT_PRM2 The LOAD_RSA_CRT_PRM1 command sets the second prime of RSA-CRT. This command must be re-issued after issuing commands to other cryptographic algorithms (include RSA). Command: CLA INS P1 P2 P3 Data 0x80 0x02 0x02 0x00 0x02 Prime (2-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 20
21 LOAD_RSA_CRT_COEF The LOAD_RSA_CRT_COEF command sets the coefficient of RSA-CRT. This command must be re-issued after issuing commands to other cryptographic algorithms (including RSA). Command: CLA INS P1 P2 P3 Data 0x80 0x02 0x03 0x00 0x02 Coefficient (2-byte) Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 21
22 MAKE_RSA_KEY The MAKE_RSA_KEY command initializes the RSA key. This command must be re-issued after the settings of RSA or RSA-CRT are changed. Command: CLA INS P1 P2 P3 0x80 0x06 0x00 0x00 0x00 Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 22
23 ENCRYPT_RSA The ENCRYPT_RSA command executes RSA or RSA-CRT encryption and decryption. A response is returned upon completion of encryption or decryption. Selection of the algorithm used for the encryption or decryption is made with P2. Command: CLA INS P1 P2 P3 Data 0x80 0x04 0x01 0x?? 0x04 Plaintext (4-byte) P2: P2 0x00 0x01 0x02 0x03 Algorithm RSA RSA (equal timing) RSA-CRT RSA-CRT (equal timing) Response: SW1 SW2 Description 0x9F 0x04 Successfully executed (4-byte ciphertext is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 23
24 4.4. Other Common Commands GET_RESPONSE The GET_RESPONSE command returns the response of the last executed command. This command always returns the P3 byte whether or not an error occurred. When an error did occur, the values of the response data are undefined. Command: CLA INS P1 P2 P3 0x80 0xC0 0x00 0x00 0x?? Response: Data SW1 SW2 Description Data (0x?? byte) 0x90 0x00 Successfully executed Undefined Data (0x?? byte) 0x6A 0x86 Bad P1 or P2 Undefined Data (0x?? byte) 0x67 0x00 Bad P3 24
25 NOP The NOP command does nothing. Command: CLA INS P1 P2 P3 0x80 0x80 0x00 0x00 0x00 Response: SW1 SW2 Description 0x90 0x00 Successfully executed 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 25
26 ECHO The ECHO command sets the size of the data made available in GET_RESPONSE. Command: CLA INS P1 P2 P3 Data 0x80 0x82 0x00 0x00 0x?? Data (0x?? byte) Response: SW1 SW2 Description 0x9F 0x?? Successfully executed (0x?? byte data is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 26
27 ATR The ATR command enables GET_RESPONSE to receive the ATR. Command: CLA INS P1 P2 P3 0x80 0x84 0x00 0x00 0x00 Response: SW1 SW2 Description 0x9F 0x?? Successfully executed (0x?? byte ATR is available) 0x6A 0x86 Bad P1 or P2 0x67 0x00 Bad P3 27
28 5. Command Sequences The command sequences for each encryption and decryption algorithm are given below AES Encryption Terminal (Smart Card Reader) Smart Card MAKE_AES_KEY, Key OK (0x9000) ENCRYPT_AES, Plaintext AES Encryption OK (0x9F10) GET_RESPONSE Ciphertext, OK (0x9000) Figure 4 : AES Encryption Sequence 28
29 5.2. AES Decryption Terminal (Smart Card Reader) Smart Card MAKE_AES_KEY, Key OK (0x9000) DECRYPT_AES, Ciphertext AES Decryption OK (0x9F10) GET_RESPONSE Plaintext, OK (0x9000) Figure 5 : AES Decryption Sequence 29
30 5.3. DES Encryption Terminal (Smart Card Reader) Smart Card MAKE_DES_KEY, Key OK (0x9000) ENCRYPT_DES, Plaintext DES Encryption OK (0x9F08) GET_RESPONSE Ciphertext, OK (0x9000) Figure 6 : DES Encryption Sequence 30
31 5.4. DES Decryption Terminal (Smart Card Reader) Smart Card MAKE_DES_KEY, Key OK (0x9000) DECRYPT_DES, Ciphertext DES Decryption OK (0x9F08) GET_RESPONSE Plaintext, OK (0x9000) Figure 7 : DES Decryption Sequence 31
32 5.5. RSA Encryption Terminal (Smart Card Reader) Smart Card LOAD_RSA_MOD, Modulus OK (0x9000) LOAD_RSA_EXP, Exponent OK (0x9000) MAKE_RSA_KEY OK (0x9000) ENCRYPT_RSA, Plaintext RSA Encryption OK (0x9F04) GET_RESPONSE Ciphertext, OK (0x9000) Figure 8 : RSA Encryption Sequence 32
33 5.6. RSA-CRT Decryption Terminal (Smart Card Reader) Smart Card LOAD_RSA_CRT_PRM1, Prime1 OK (0x9000) LOAD_RSA_CRT_PRM2, Prime2 OK (0x9000) LOAD_RSA_CRT_EXP1, Exponent1 OK (0x9000) LOAD_RSA_CRT_EXP2, Exponent2 OK (0x9000) LOAD_RSA_CRT_COEF, Coefficient OK (0x9000) MAKE_RSA_KEY OK (0x9000) ENCRYPT_RSA, Ciphertext OK (0x9F04) RSA-CRT Decryption GET_RESPONSE Plaintext, OK (0x9000) Figure 9 : RSA-CRT Decryption Sequence 33
34 6. Test Sequences This command does nothing NOP Terminal (Smart Card Reader) Smart Card (1) NOP (2) OK (0x9000) Figure 10 : Test Sequence for NOP Command Table 6 : Sequence Data for NOP Command Test Index Data (hexadecimal) (1) (2)
35 6.2. ECHO Terminal (Smart Card Reader) Smart Card (1) ECHO, 0xA5 0x43 (2) OK (0x9F02) (3) GET_RESPONSE (4) 0xA5, 0x43 OK (0x9000) Figure 11 : Test Sequence for ECHO Command Table 7 : Sequence Data of ECHO Command Test Index Data (hexadecimal) (1) A5 43 (2) 9F 02 (3) 80 C (4) A
36 6.3. AES Encryption Terminal (Smart Card Reader) Smart Card (1) MAKE_AES_KEY, Key (2) OK (0x9000) (3) ENCRYPT_AES, Plaintext (4) OK (0x9F10) AES Encryption (5) GET_RESPONSE (6) Ciphertext, OK (0x9000) Figure 12 : Test Sequence for AES Encryption Table 8 : Sequence Data for AES Encryption Test Index Data (hexadecimal) (1) A 0B 0C 0D 0E 0F (2) (3) A 5A B C EF DB AA D8 (4) 9F 10 (5) 80 C (6) AA BB CC DD EE FF
37 6.4. AES Decryption Terminal (Smart Card Reader) Smart Card (1) MAKE_AES_KEY, Key (2) OK (0x9000) (3) DECRYPT_AES, Ciphertext (4) OK (0x9F10) AES Decryption (5) GET_RESPONSE (6) Plaintext, OK (0x9000) Figure 13 : Test Sequence for AES Decryption Table 9 : Sequence Data for AES Decryption Test Index Data (hexadecimal) (1) A 0B 0C 0D 0E 0F (2) (3) B F 4F FD FC 87 CA 96 4D (4) 9F 10 (5) 80 C (6) FF EE DD CC BB AA
38 6.5. DES Encryption Terminal (Smart Card Reader) Smart Card (1) MAKE_DES_KEY, Key (2) OK (0x9000) (3) ENCRYPT_DES, Plaintext (4) OK (0x9F08) DES Encryption (5) GET_RESPONSE (6) Ciphertext, OK (0x9000) Figure 14 : Test Sequence for DES Encryption Table 10 : Sequence Data for DES Encryption Test Index Data (hexadecimal) (1) 80 0A A 0B 0C 0D 0E 0F (2) (3) B ED 22 B9 FE (4) 9F 08 (5) 80 C (6)
39 6.6. DES Decryption Terminal (Smart Card Reader) Smart Card (1) MAKE_DES_KEY, Key (2) OK (0x9000) (3) DECRYPT_DES, Ciphertext (4) OK (0x9F08) DES Decryption (5) GET_RESPONSE (6) Plaintext, OK (0x9000) Figure 15 : Test Sequence for DES Decryption Table 11 : Sequence Data for DES Decryption Test Index Data (hexadecimal) (1) 80 0A A 0B 0C 0D 0E 0F (2) (3) F7 C C9 AF E5 CB (4) 9F 08 (5) 80 C (6) AA BB CC DD EE FF
40 6.7. RSA Encryption Terminal (Smart Card Reader) Smart Card (1) LOAD_RSA_MOD, Modulus (2) OK (0x9000) (3) LOAD_RSA_EXP, Exponent (4) OK (0x9000) (5) MAKE_RSA_KEY (6) OK (0x9000) (7) ENCRYPT_RSA, Plaintext (8) OK (0x9F04) RSA Encryption (9) GET_RESPONSE (10) Ciphertext, OK (0x9000) Figure 16 : Test Sequence for RSA Encryption Table 12 : Sequence Data for RSA Encryption Test Index Data (hexadecimal) (1) C E9 (2) (3) (4) (5) (6) (7) B 21 (8) 9F 04 (9) 80 C (10) 89 AB CD EF
41 6.8. RSA Decryption Terminal (Smart Card Reader) Smart Card (1) LOAD_RSA_MOD, Modulus (2) OK (0x9000) (3) LOAD_RSA_EXP, Exponent (4) OK (0x9000) (5) MAKE_RSA_KEY (6) OK (0x9000) (7) ENCRYPT_RSA, Ciphertext (8) OK (0x9F04) RSA Decryption (9) GET_RESPONSE (10) Plaintext, OK (0x9000) Figure 17 : Test Sequence for RSA Decryption Table 13 : Sequence Data for RSA Decryption Test Index Data (hexadecimal) (1) C E9 (2) (3) B9 B1 AE 25 (4) (5) (6) (7) F1 64 F2 (8) 9F 04 (9) 80 C (10)
42 6.9. RSA-CRT Decryption Terminal (Smart Card Reader) Smart Card (1) LOAD_RSA_CRT_PRM1, Prime1 (2) OK (0x9000) (3) LOAD_RSA_CRT_PRM2, Prime2 (4) OK (0x9000) (5) LOAD_RSA_CRT_EXP1, Exponent1 (6) OK (0x9000) (7) LOAD_RSA_CRT_EXP2, Exponent2 (8) OK (0x9000) (9) LOAD_RSA_CRT_COEF, Coefficient (10) OK (0x9000) (11) MAKE_RSA_KEY (12) OK (0x9000) (13) ENCRYPT_RSA, Ciphertext (14) OK (0x9F04) RSA-CRT Decryption (15) GET_RESPONSE (16) Plaintext, OK (0x9000) Figure 18 : Test Sequence for RSA-CRT Decryption 42
43 Table 14 : Sequence Data for RSA-CRT Decryption Test Index Data (hexadecimal) (1) E6 57 (2) (3) D8 BF (4) (5) D 39 (6) (7) CD (8) (9) C0 26 (10) (11) (12) (13) F1 64 F2 (14) 9F 04 (15) 80 C (16)
44 7. Cryptographic Algorithms Flowcharts for the cryptographic algorithms are shown below AES Encryption (Byte-oriented) Start I = 1 I < 10 No Yes Add Round Key & Sub Byte & Shift Row (Byte Order) Mix Column Key Expansion I = I + 1 Add Round Key & Sub Byte & Shift Row (Byte Order) Key Expansion Add Round Key End Figure 19 : AES Encryption Flowchart (Byte-oriented) 44
45 7.2. AES Decryption (Byte-oriented) Start Add Round Key Inverse Key Expansion I = 1 I < 10 No Yes Inverse Shift Row & Inverse Sub Byte & Add Round Key (Byte Order) Inverse Key Expansion Inverse Mix Column I = I + 1 Inverse Shift Row & Inverse Sub Byte & Add Round Key (Byte Order) End Figure 20 : AES Decryption Flowchart (Byte-oriented) 45
46 7.3. AES Encryption (Hardware-like) Start Add Round Key I = 1 I < 10 No Yes Sub Byte Shift Row Mix Column Key Expansion Add Round Key I = I + 1 Sub Byte Shift Row Key Expansion Add Round Key End Figure 21 : AES Encryption Flowchart (Hardware-like) 46
47 7.4. AES Decryption (Hardware-like) Start Add Round Key Inverse Key Expansion Inverse Shift Row Inverse Sub Byte I = 1 I < 10 No Yes Add Round Key Inverse Key Expansion Inverse Mix Column Inverse Shift Row Inverse Sub Byte I = I + 1 Add Round Key End Figure 22 : AES Decryption Flowchart (Hardware-like) 47
48 7.5. DES Encryption and Decryption Start PC1 IP I = 1 PC2 E Add Round Key F Function S-Box P XOR I < 16 Yes No Swap L and R I = I + 1 FP End Figure 23 : DES Encryption and Decryption Flowchart 48
49 7.6. RSA Encryption and Decryption Start C = M E mod N "Left-To-Right" Modular Exponentiation C = 1 I = 31 I > 0 No Yes C == 1 Yes No C = C 2 mod N EI == 1 No Yes C = (M C) mod N I = I - 1 End Figure 24 : RSA Encryption and Decryption Flowchart 49
50 7.7. RSA Encryption and Decryption (Equal Timing) Start C = M E mod N "Left-To-Right" Modular Exponentiation C = 1 I = 31 I > 0 Yes No C = C 2 mod N EI == 1 No Yes C = (M C) mod N Dummy = (M C) mod N I = I - 1 End Figure 25 : RSA Encryption and Decryption Flowchart (Equal Timing) 50
51 7.8. RSA-CRT Decryption Start CP2 = C mod PRM2 CP1 = C mod PRM1 M2 = CP2 EXP2 mod PRM2 M1 = CP1 EXP1 mod PRM1 H = (COEF (M1 - M2)) mod PRM1 M = PRM2 H + M2 End Figure 26 : RSA-CRT Decryption Flowchart 51
52 The SASEBO-W Smart Card OS was developed by AIST while undertaking projects sponsored by the Japan Science and Technology Agency (JST) 1. The copyright of this product belongs to the National Institute of Advanced Industrial Science and Technology (AIST). 2. Copying of this document and product, in whole or in part, is prohibited without written permission from the copyright holders. 3. This document and product may be used for only personal or research purposes. Any other use of this document and product is not allowed without written permission from the copyright holders. 4. Specifications of this product are subject to revision without notice. Contact Us Please send technical inquiries to: National Institute of Advanced Industrial Science and Technology (AIST) AIST Tsukuba Central 2 Room Umezono, Tsukuba-shi, Ibaraki , Japan TEL: FAX:
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design:
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design: Secret Key Systems (block encoding) Encrypting a small block of text (say 64
C1098 JPEG Module User Manual
C1098 JPEG Module User Manual General Description C1098 is VGA camera module performs as a JPEG compressed still camera that can be attached to a wireless or PDA host. Users can send out a snapshot command
CIS-331 Spring 2016 Exam 1 Name: Total of 109 Points Version 1
Version 1 Instructions Write your name on the exam paper. Write your name and version number on the top of the yellow paper. Answer Question 1 on the exam paper. Answer Questions 2-4 on the yellow paper.
CIS-331 Exam 2 Fall 2015 Total of 105 Points Version 1
Version 1 1. (20 Points) Given the class A network address 117.0.0.0 will be divided into multiple subnets. a. (5 Points) How many bits will be necessary to address 4,000 subnets? b. (5 Points) What is
CIS-331 Fall 2013 Exam 1 Name: Total of 120 Points Version 1
Version 1 1. (24 Points) Show the routing tables for routers A, B, C, and D. Make sure you account for traffic to the Internet. NOTE: Router E should only be used for Internet traffic. Router A Router
CIS-331 Exam 2 Fall 2014 Total of 105 Points. Version 1
Version 1 1. (20 Points) Given the class A network address 119.0.0.0 will be divided into a maximum of 15,900 subnets. a. (5 Points) How many bits will be necessary to address the 15,900 subnets? b. (5
ENGI 8868/9877 Computer and Communications Security III. BLOCK CIPHERS. Symmetric Key Cryptography. insecure channel
(a) Introduction - recall symmetric key cipher: III. BLOCK CIPHERS k Symmetric Key Cryptography k x e k y yʹ d k xʹ insecure channel Symmetric Key Ciphers same key used for encryption and decryption two
4. Specifications and Additional Information
4. Specifications and Additional Information AGX52004-1.0 8B/10B Code This section provides information about the data and control codes for Arria GX devices. Code Notation The 8B/10B data and control
How to write a SECA CAM by JF Version 1.00 April 2003
How to write a SECA CAM by JF Version 1.00 April 2003 Page 1 of 14 Table of contents 1) Starting (Reading the smartcard)...3 1.1) ATR (Answer To Reset)... 3 1.2) Providers in the smartcard... 3 1.3) Smart
Fundamentals of Cryptography
Fundamentals of Cryptography Topics in Quantum-Safe Cryptography June 23, 2016 Part III Data Encryption Standard The Feistel network design m m 0 m 1 f k 1 1 m m 1 2 f k 2 2 DES uses a Feistel network
CIS-331 Final Exam Spring 2015 Total of 115 Points. Version 1
Version 1 1. (25 Points) Given that a frame is formatted as follows: And given that a datagram is formatted as follows: And given that a TCP segment is formatted as follows: Assuming no options are present
The cache is 4-way set associative, with 4-byte blocks, and 16 total lines
Sample Problem 1 Assume the following memory setup: Virtual addresses are 20 bits wide Physical addresses are 15 bits wide The page size if 1KB (2 10 bytes) The TLB is 2-way set associative, with 8 total
CSCI 454/554 Computer and Network Security. Topic 3.1 Secret Key Cryptography Algorithms
CSCI 454/554 Computer and Network Security Topic 3.1 Secret Key Cryptography Algorithms Outline Introductory Remarks Feistel Cipher DES AES 2 Introduction Secret Keys or Secret Algorithms? Security by
AIT 682: Network and Systems Security
AIT 682: Network and Systems Security Topic 3.1 Secret Key Cryptography Algorithms Instructor: Dr. Kun Sun Outline Introductory Remarks Feistel Cipher DES AES 2 Introduction Secret Keys or Secret Algorithms?
CIS-331 Final Exam Spring 2018 Total of 120 Points. Version 1
Version 1 Instructions 1. Write your name and version number on the top of the yellow paper and the routing tables sheet. 2. Answer Question 2 on the routing tables sheet. 3. Answer Questions 1, 3, 4,
CIS-331 Fall 2014 Exam 1 Name: Total of 109 Points Version 1
Version 1 1. (24 Points) Show the routing tables for routers A, B, C, and D. Make sure you account for traffic to the Internet. Router A Router B Router C Router D Network Next Hop Next Hop Next Hop Next
Technical Specification. Third Party Control Protocol. AV Revolution
Technical Specification Third Party Control Protocol AV Revolution Document AM-TS-120308 Version 1.0 Page 1 of 31 DOCUMENT DETAILS Document Title: Technical Specification, Third Party Control Protocol,
RS 232 PINOUTS. 1. We use RJ12 for all of our RS232 interfaces (Link-2-Modbus & Link-2-PC- Serial/RS232). The diagram below shows our pin out.
RS 232 PINOUTS 1. We use RJ12 for all of our RS232 interfaces (Link-2-Modbus & Link-2-PC- Serial/RS232). The diagram below shows our pin out. 2. A DB9 Female to RJ12 Female Serial/Terminal Modular Adaptor
Digital Lighting Systems, Inc. CD400-DMX DMX512 Four Channel Dimmer and Switch module
, Inc. DMX512 Four Channel Dimmer and Switch module Input: 5 Amps @ 6-24 VDC Outputs: 5 Amps Maximum each, total 4 outputs 8 Amps Maximum. FRONT BACK USER'S MANUAL -UM User's Manual - Page 1 GENERAL DESCRIPTION
Implementation of the AES as a Hash Function for Confirming the Identity of Software on a Computer System
PNNL-1417 Implementation of the AES as a Hash Function for Confirming the Identity of Software on a Computer System R.R. Hansen R.. ass R.T. Kouzes N.D. Mileson January 23 Prepared for the U.S. Department
ACR122S Serial NFC Reader
ACR122S Serial NFC Reader Communication Protocol Subject to change without prior notice Table of Contents 1.0. Introduction... 4 1.1. Serial Interface... 4 1.2. Bi-Color LED... 4 1.3. Buzzer... 4 1.4.
YHY502CTG++ DATASHEET MHz RFID Mifare Read/Write Module. YHY502CTG++ Datasheet Revision 2.0 Oct, 2009 Page 1 of 21
YHY5CTG++ Datasheet Revision 2.0 Oct, 29 Page 1 of 21 YHY5CTG++ 13.56MHz RFID Mifare Read/Write Module DATASHEET Complete Read/Write module with built-in transceiver antenna Auto checks for presence of
CIS-331 Exam 2 Spring 2016 Total of 110 Points Version 1
Version 1 1. (20 Points) Given the class A network address 121.0.0.0 will be divided into multiple subnets. a. (5 Points) How many bits will be necessary to address 8,100 subnets? b. (5 Points) What is
Gateway Ascii Command Protocol
Gateway Ascii Command Protocol Table Of Contents Introduction....2 Ascii Commands.....3 Messages Received From The Gateway....3 Button Down Message.....3 Button Up Message....3 Button Maintain Message....4
UNH-IOL MIPI Alliance Test Program
DSI Receiver Protocol Conformance Test Report UNH-IOL 121 Technology Drive, Suite 2 Durham, NH 03824 +1-603-862-0090 mipilab@iol.unh.edu +1-603-862-0701 Engineer Name engineer@company.com Panel Company
ECHO Process Instrumentation, Inc. Modbus RS485 Module. Operating Instructions. Version 1.0 June 2010
ECHO Process Instrumentation, Inc. Modbus RS485 Module Operating Instructions Version 1.0 June 2010 ECHO Process Instrumentation, Inc. PO Box 800 Shalimar, FL 32579 PH: 850-609-1300 FX: 850-651-4777 EM:
A Specification for Rijndael, the AES Algorithm
A Specification for Rijndael, the AES Algorithm. Notation and Conventions. Rijndael Inputs and Outputs The input, output and cipher key for Rijndael are sequences containing 28, 6, 92, 224 or 256 bits
Digital Lighting Systems, Inc.
Digital Lighting Systems, Inc. Four Channel Dry Contacts Relays Switch Pack DMX512 compatible USER'S MANUAL -UM User's Manual - Page 1 GENERAL DESCRIPTION The is a 4-channel DMX-512 compatible electro-mechanical
First Data DCC Test Card Set. Version 1.30
First Data DCC Test Card Set.30 April, 2018 Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information available from industry
DBK24. Isolated Digital Output Chassis. Overview
DBK24 Isolated Digital Output Chassis Overview 1 Power Requirements 2 Hardware Setup 2 Card Connection 2 Card Configuration 3 DaqBook and DaqBoard Connection 4 DaqBoard/2000 Series Board Connection 5 DaqBook
Acquirer JCB EMV Test Card Set
Acquirer JCB EMV Test Card Set July, 2017 Powered by Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information available
JMY607H User's Manual
JMY607H User's Manual (Revision 3.42) Jinmuyu Electronics Co. LTD 2011/6/27 Please read this manual carefully before using. If any problem, please mail to: Jinmuyu@vip.sina.com Contents 1 Product introduction...
Modbus Module. Data sheet. Communication module for MULTICAL 403 and MULTICAL 603
Data sheet Modbus Module Communication module for MULTICAL 403 and MULTICAL 603 Modbus RTU communication Communication speed up to 115200 bits/s Programmable data, communication speed and parity settings
One subset of FEAL, called FEAL-NX, is N round FEAL using a 128-bit key without key parity.
FEAL-NX SPECIFICATIONS 1 Introduction 1.1 Outline of the FEAL-NX cipher FEAL, the Fast Data Encipherment Algorithm, is a 64-bit block cipher algorithm that enciphers 64-bit plaintexts into 64-bit ciphertexts
Device: MOD This document Version: 1.0. Matches module version: v1. Date: 24 February Description: MP3 Audio Module
Device: MOD-1021 This document Version: 1.0 Matches module version: v1 Date: 24 February 2014 Description: MP3 Audio Module MOD-1021 v1 datasheet Page 2 Contents Introduction... 3 Features... 3 Connections...
TLS 1.2 Protocol Execution Transcript
Appendix C TLS 1.2 Protocol Execution Transcript In Section 2.3, we overviewed a relatively simple protocol execution transcript for SSL 3.0. In this appendix, we do something similar for TLS 1.2. Since
A Specification for Rijndael, the AES Algorithm
A Specification for Rijndael, the AES Algorithm 1. Notation and Conventions 1.1 Rijndael Inputs and Outputs The input, output and cipher key for Rijndael are sequences containing 128, 160, 192, 224 or
Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices
Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices Kostas Papagiannopoulos Aram Verstegen July 11, 2013 Papagiannopoulos and Verstegen July 11, 2013 Speed and Size-Optimized
Stream Ciphers and Block Ciphers
Stream Ciphers and Block Ciphers Ruben Niederhagen September 18th, 2013 Introduction 2/22 Recall from last lecture: Public-key crypto: Pair of keys: public key for encryption, private key for decryption.
Here is a C function that will print a selected block of bytes from such a memory block, using an array-based view of the necessary logic:
Pointer Manipulations Pointer Casts and Data Accesses Viewing Memory The contents of a block of memory may be viewed as a collection of hex nybbles indicating the contents of the byte in the memory region;
SASEBO-GII Quick Start Guide
SASEBO-GII Quick Start Guide [Version 1.0] September 3, 2009 Research Center for Information Security, National Institute of Advanced Industrial Science and Technology 1. Equipment preparation Before setting
SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017
SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017 WHAT WE DO What we do Robust and Efficient Cryptographic Protocols Research in Cryptography and
6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals
Device: EDR B. This document Version: 1c. Date: 11 November Matches module version: v3 [25 Aug 2016]
![Device: EDR B. This document Version: 1c. Date: 11 November Matches module version: v3 [25 Aug 2016]](/thumbs/77/74847383.jpg "Device: EDR B. This document Version: 1c. Date: 11 November Matches module version: v3 [25 Aug 2016]")
Device: EDR-200200B This document Version: 1c Date: 11 November 2016 Matches module version: v3 [25 Aug 2016] Description: e-paper Display Driver and 200x200 e-paper Display EDR-200200B v1 datasheet Page
MM23SC8128RM Flash Security Turbo Microcontroller Smart Card Chip With 1024 bit RSA & Maths Co-processor
Flash Security Turbo Microcontroller Smart Card Chip With 1024 bit RSA & Maths Co-processor 08 September 2009 This document is property of My-MS and My-MS has the right to make any changes to the contents
First Data EMV Test Card Set. Version 1.30
First Data EMV Test Card Set.30 January, 2018 Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information available from industry
JMY504M User's Manual
JMY504M User's Manual (Revision 3.42) Jinmuyu Electronics Co. LTD 2011/6/28 Please read this manual carefully before using. If any problem, please mail to: Jinmuyu@vip.sina.com Contents 1 Product introduction...
First Data EMV Test Card Set. Version 2.00
First Data EMV Test Card Set.00 February, 2018 Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information available from industry
CRT-603-CZ1 Contactless Card Reader Module. User Manual
Page 1/39 CRT-603-CZ1 Contactless Card Reader Module (V1.0.0.0) CREATOR (CHINA) TECH CO., LTD ADD: 2/F, M-10 Building, Center Area, High-tech Industrial Park Shenzhen, Guangdong, China. Tel: +86-755-26710345
CS 537: Introduction to Operating Systems Fall 2015: Midterm Exam #1
CS 537: Introduction to Operating Systems Fall 2015: Midterm Exam #1 This exam is closed book, closed notes. All cell phones must be turned off. No calculators may be used. You have two hours to complete
RSA (material drawn from Avi Kak Lecture 12, Lecture Notes on "Computer and Network Security" Used in asymmetric crypto.
RSA (material drawn from Avi Kak (kak@purdue.edu) Lecture 12, Lecture Notes on "Computer and Network Security" Used in asymmetric crypto. protocols The RSA algorithm is based on the following property
LynX-10 Legacy Protocol Specification Version 1.01
LynX-10 Legacy Protocol Specification Version 1.01 Marrick Limited LynX-10 TM Legacy Protocol Specification Manual revision 1.01 Marrick Limited, Incorporated P.O. Box 950940 Lake Mary, FL 32795 (407)
APDU-Test Card Functional Requirements
Autor Andreas Schwier Version V1.1 Datum 03. January 2012 Copyright 2012 CardContact Software & System Consulting The authors of this documentation make no representation or warranty regarding whether
M/Chip Advance V1.1 Personalization Guide
M/Chip Advance V1.1 Personalization Guide v01.71 (November, 2017) All copyrights are reserved by KONA I Co., Ltd. This manual can be revised without any notification. Unauthorized copying is strictly prohibited
Logosol Joystick Node LS-731
Features 2 and 3 axis models Travel ±20 deg Non contact hall effect joystick Mechanical MTBF 15,000,000 cycles 3 pushbuttons Up to 2 stick pushbuttons 8 LEDs Member of Logosol s distributed motion control
Enhanced Play Fair Cipher
P Enhanced Play Fair Cipher 1 1 Naveen KMP P, PDepartment of Information Technology, Velammal Engineering College, Chennai, Tamil Nadu, India. Abstract The theme of this research work is to design and
Modbus Module. Data sheet. Communication module for MULTICAL 403 and MULTICAL 603
Data sheet Modbus Module Communication module for MULTICAL 403 and MULTICAL 603 Modbus RTU communication Communication speed up to 115200 bits/s Programmable data, communication speed and parity settings
Encryption Details COMP620
Encryption Details COMP620 Encryption is a powerful defensive weapon for free people. It offers a technical guarantee of privacy, regardless of who is running the government It s hard to think of a more
Secure Microcontrollers for Smart Cards. AT90SC Summary
Features High-performance, Low-power 8-bit AVR RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution Up to 64K Bytes Flash Program Memory Endurance: 10K Write/Erase Cycles Up to
Interac USA Interoperability EMV Test Card Set
Interac USA Interoperability EMV Test Card Set.00 April, 2018 Powered by Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information
JMY505G User's Manual
JMY505G User's Manual (Revision 3.42) Jinmuyu Electronics Co. LTD 2011/6/28 Please read this manual carefully before using. If any problem, please mail to: jinmuyu@vip.sina.com Contents 1 Product introduction...
JMY501H User's Manual
JMY501H User's Manual (Revision 3.42) Jinmuyu Electronics Co. LTD 2011/6/27 Please read this manual carefully before using. If any problem, please mail to: Jinmuyu@vip.sina.com Contents 1 Product introduction...
!,,-!1!,*& (*+ ( / (? $ &,.,,/&++0 $3. 4 5$ 5.&&++0 $3 (9 33 (*. >&(!?@3@,,/&++0 >& >& >& / (? (!&,1*&B C(!?@3@ 5.5@@??(? A>( $ 4.,+(,1,( ((9 & (1? (9?? $?E3?@E$?$33?@$ ( $?E3@3E $?$33@3$ > ( (& (*+ (&
Stream Ciphers and Block Ciphers
Stream Ciphers and Block Ciphers 2MMC10 Cryptology Fall 2015 Ruben Niederhagen October 6th, 2015 Introduction 2/32 Recall: Public-key crypto: Pair of keys: public key for encryption, private key for decryption.
Secret Key Cryptography
Secret Key Cryptography General Block Encryption: The general way of encrypting a 64-bit block is to take each of the: 2 64 input values and map it to a unique one of the 2 64 output values. This would
CMOS TYPE CAMERA JC406M-W01
CMOS TYPE CAMERA JC406M-W01 Deqing Jiahe Electronic Technology Co., Ltd. TEL: +86-572-7812102 FAX: +86-572-8885779 sales@jiahe-electronic.com 1 Application The JC406M-W01 JPEG compression module performs
Acquirer JCB Dual Interface EMV Test Card Set
Acquirer JCB Dual Interface EMV Test Card Set.00 July, 2018 Powered by Disclaimer Information provided in this document describes capabilities available at the time of developing and delivering this document
10. RS-232C communication
10. RS-232C communication PB9200(P5XMLA) Connecting the cable (1) Turn off the projector and the computer power supplies. (2) Connect the CONTROL port of the projector with a RS-232C port of the computer
USB-ASC232. ASCII RS-232 Controlled USB Keyboard and Mouse Cable. User Manual
USB-ASC232 ASCII RS-232 Controlled USB Keyboard and Mouse Cable User Manual Thank you for purchasing the model USB-ASC232 Cable HAGSTROM ELECTRONICS, INC. is pleased that you have selected this product
ZN-DN312XE-M Quick User Guide
ZN-DN312XE-M Quick User Guide This manual provides instructions for quick installation and basic configuration of your IP device. Step1. Connect cables to IP device Connect required cables to the device
Chapter 9. Public Key Cryptography, RSA And Key Management
Chapter 9 Public Key Cryptography, RSA And Key Management RSA by Rivest, Shamir & Adleman of MIT in 1977 The most widely used public-key cryptosystem is RSA. The difficulty of attacking RSA is based on
A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.9, September 2009 305 A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box Muhammad
QBridge. I2C, SPI, CAN Control Software User s Manual. Date: Rev 1.3
QBridge I2C, SPI, CAN Control Software User s Manual Date: 9-10-2005 Rev 1.3 1. Introduction...1 1.1. What QBridge can do?... 1 1.2. Disclaimer... 1 1.3. Operational Format... 1 1.4. QBridge-V2... 1 2.
Channel Coding and Cryptography Part II: Introduction to Cryptography
Channel Coding and Cryptography Part II: Introduction to Cryptography Prof. Dr.-Ing. habil. Andreas Ahrens Communications Signal Processing Group, University of Technology, Business and Design Email: andreas.ahrens@hs-wismar.de
Custom Installation Notes: Serial programming interface for Arcam A/V processors & receivers
Custom Installation Notes: Serial programming interface for Arcam A/V processors & receivers Models covered: AVP700, AVR250, AVR300, AVR350 Contents Applicability... 2 Controlling Arcam A/V processors
Public Key Algorithms
Public Key Algorithms 1 Public Key Algorithms It is necessary to know some number theory to really understand how and why public key algorithms work Most of the public key algorithms are based on modular
I²C GLCD Adapter for KS x64 Manual (1.4)
I²C GLCD Adapter for KS0108 128x64 Manual (1.4) Luxemburger Str. 31 D 13353 Berlin Phone: +49 (0)30 617 412 48 Fax: +49 (0)30 617 412 47 www.channaa.com 2 1. General discription... 3 2. Pinning Information...
Research Article A Student Information Management System Based on Fingerprint Identification and Data Security Transmission
Hindawi Electrical and Computer Engineering Volume 27, Article ID 9598581, 6 pages https://doi.org/10.1155/27/9598581 Research Article A Student Information Management System Based on Fingerprint Identification
Computer Security. 08. Cryptography Part II. Paul Krzyzanowski. Rutgers University. Spring 2018
Computer Security 08. Cryptography Part II Paul Krzyzanowski Rutgers University Spring 2018 March 23, 2018 CS 419 2018 Paul Krzyzanowski 1 Block ciphers Block ciphers encrypt a block of plaintext at a
Communications guide. Line Distance Protection System * F1* GE Digital Energy. Title page
Title page GE Digital Energy D90 Plus Line Distance Protection System Communications guide D90 Plus firmware revision:.9x GE publication code: 60-9070-F (GEK-3469) GE Digital Energy 650 Markland Street
Digital Lighting Systems, Inc.
, Inc. PD402-DMX Four Channel Dimmer and Switch Packs 4 x 2.5 Amps @ 6VDC to 24 VDC DMX52 compatible DMX52 4 x 2.5 Amps Dimmer Pack C UL US LISTED Digital Lighting Systems, Inc. USER'S MANUAL User's Manual
Smart cards are made of plastic, usually polyvinyl chloride. The card may embed a hologram to prevent counterfeiting. Smart cards provide strong
Smart Cards By: Definition Smart cards, chip card, or integrated circuit card (ICC) are card with embedded integrated circuits that contain a computer chip capable of carrying out a cryptographic protocol.
ACR1281U-C1 USB Dual Interface Reader Application Programming Interface V1.08 Subject to change without prior notice
ACR1281U-C1 USB Dual Interface Reader Application Programming Interface V1.08 Subject to change without prior notice Revision History Release Date Revision Description Version Number 2011-08-19 Initial
Functional Specification of the OpenPGP application on ISO Smart Card Operating Systems
Functional Specification of the OpenPGP application on ISO Smart Card Operating Systems Version 2.2 Author: Achim Pietig 2016 January 10th Author: Achim Pietig Lippstädter Weg 14 32756 Detmold Germany
Introduction to Cryptography and Security Mechanisms: Unit 5. Public-Key Encryption
Introduction to Cryptography and Security Mechanisms: Unit 5 Public-Key Encryption Learning Outcomes Explain the basic principles behind public-key cryptography Recognise the fundamental problems that
EFFICIENT HARDWARE IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM
EFFICIENT HARDWARE IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM by Issam Mahdi Hammad Submitted in partial fulfilment of the requirements for the degree of Master of Applied Science
First Data Dual Interface EMV Test Card Set. Version 1.20
First Data Dual Interface EMV Test Card Set August, 2016 Disclaimer Information provided in this document describes capabilities available at the time of developing this document and information available
Digital Lighting Systems, Inc. PD405-DMX. Four Channel Dimmer and Switch Packs. DMX512 compatible. PD405-DMX-24DC DMX512 4 x 5 Amps Dimmer Pack
Digital Lighting Systems, Inc. PD405DMX Four Channel Dimmer and Switch Packs DMX52 compatible PD405DMX24DC DMX52 4 x 5 Amps Dimmer Pack C UL US LISTED www.digitallighting.com Digital Lighting Systems,
How to Digital Sign a PDF document With Nexus Personal software
How to Digital Sign a PDF document With Nexus Personal software Version 1.1 Page 1 from 11 1. Introduction This document describes the procedure must be followed to digitally sign a PDF document using
Advanced Encryption Standard and Modes of Operation. Foundations of Cryptography - AES pp. 1 / 50
Advanced Encryption Standard and Modes of Operation Foundations of Cryptography - AES pp. 1 / 50 AES Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm AES has been originally requested
C628 Enhanced JPEG Module. User Manual
C628 Enhanced JPEG User Manual v1.1 Release Note: 1. May 2, 2006 official released v1.0 2. Dec 27, 2006 revise electrical characteristics Table of Contents Part I - Hardware Overview 1 Features.. 1 Specifications
Public Key Encryption
Public Key Encryption A case study THE RSA CRYPTOSYSTEM Public 31/05/14 Key Encryption 2 Rivest Shamir Adleman (1978) Key generation 1. Generate two large, distinct primes p, q (100 200 decimal digits)
Hash Constant C Determinants leading to collisionfree
Hash Constant C Determinants leading to collisionfree (Ernst Erich Schnoor) eschnoor@multi-matrix.de Addendum to article: Core of the CypherMatrix Method http://www.telecypher.net/corecyph.htm#z6 Object
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 884 FPGA Implementation of Cryptographic Algorithms: A Survey Ambika R 1 Sahana Devanathan 2 1Associate Professor,
TPMC816. Two Independent Channels Extended CAN Bus PMC Module. Version 2.2. User Manual. Issue August 2014
The Embedded I/O Company TPMC816 Two Independent Channels Extended CAN Bus PMC Module Version 2.2 User Manual Issue 2.2.1 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone:
Virtual Memory (2) 1
Virtual Memory (2) 1 Changelog 1 Changes made in this version not seen in first lecture: 21 November 2017: 1-level example: added final answer of memory value, not just location 21 November 2017: two-level
AES Core Specification. Author: Homer Hsing
AES Core Specification Author: Homer Hsing homer.hsing@gmail.com Rev. 0.1.1 October 30, 2012 This page has been intentionally left blank. www.opencores.org Rev 0.1.1 ii Revision History Rev. Date Author
Supports ISO14443A Mifare Classic 1K, Mifare Classic 4K, Mifare Ultralight. Fast data transfer - Contactless communication up to 106 KHz
SM132-USB 13.56 MHz RFID Mifare Read / Write USB Module DATA SHEET Complete Read/Write module including antenna Supports ISO14443A Mifare Classic 1K, Mifare Classic 4K, Mifare Ultralight USB Interface
LP-WU9100B User's Manual (detailed) Operating Guide Technical
DLP Projector LP-WU9100B User's Manual (detailed) Operating Guide Technical Supported Signal Input Modes Signal Format PC Apple MAC SDTV EDTV Resolution H Freq. KHz Frame Rate Hz PCLK MHz 5 B N C VGA RGB
TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO.
vii TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATION iii xii xiv xvii 1 INTRODUCTION 1 1.1 GENERAL 1 1.2 TYPES OF WIRELESS COMMUNICATION