SPEED2000 Examples 1. Product Version 16.6 December 2012

Transcription

1 SPEED2000 Examples 1 Product Version 16.6 December 2012

2 2012 Cadence Design Systems, Inc. All rights reserved. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence s trademarks, contact the corporate legal department at the address shown above or call All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modified in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR and DFAR et seq. or its successor

3 Table of Contents SPEED2000 Eamples Table of Contents 1 Introduction...1 System Requirements...1 How to Use This Guide... 1 Additional Documentation... 1 Conventions Used in This Guide... 1 How to Contact Technical Support Examples1...3 Introduction... 3 Translation Procedures... 3 Translation Steps... 4 Using a New Circuit: Vsource... 8 Specify Observations Run Simulation Using Model Type, Edge Term LowFrequency Effective Power / Ground Inductance Using Model Definition, Decap Low Frequency Effective Power / Ground Inductance Using Model Definition: Driver Set Curves Using the Model Definition: VCC Set Curves Using s2k_demovcr_1drv.spd Using s2k_demoibis_1drv.spd I

4 II SPEED2000 Eamples1 16.6

5 System Requirements SPEED2000 Examples Introduction This document contains some advanced examples that will help you work with SPEED2000 in further detail. SYSTEM REQUIREMENTS HOW TO USE THIS GUIDE The following system requirements are necessary for SPEED2000. Microsoft Windows XP and Windows 7 RedHat Enterprise Linux AS/ES/WS Release 4, x86_64 RedHat Enterprise Linux AS/ES/WS Release 5, x86_64 SUSE Linux Enterprise Server 10, x86_64 Minimum 2GB Memory The SPEED2000 Examples1 provides demonstration examples and step-by-step instructions on how to get the desired results. ADDITIONAL DOCUMENTATION In addition to this document, refer to the following documentation for additional information. Translators User s Guide describes translations from various types of board and package file formats to Sigrity s SPD format. SPEED2000 User s Guide describes in detail the features and functionality of SPEED2000. SPEED2000 Getting Started Guide shows you how to start using the functionality in SPEED2000. CONVENTIONS USED IN THIS GUIDE CONVENTION Bold USE GUI text, special names, terms (window names, buttons, menus, etc.) INTRODUCTION 1

6 How to Contact Technical Support SPEED2000 Examples CONVENTION Arial USE Examples > Menu hierarchy HOW TO CONTACT TECHNICAL SUPPORT If you have questions about SPEED2000, contact the Cadence Online Support. INTRODUCTION 2

7 Introduction SPEED2000 Examples Examples1 This document contains some advanced examples that will help you work with SPEED2000 in further detail. INTRODUCTION We will work with a sample Allegro file, demo.brd, that will show you how to use the Cadence translator, SPDLinks.exe, to convert an Allegro layout file to a SPEED2000 spd file. The resulting.spd file will be used in the following case studies: 1. Study the resonance properties of the power / ground planes of the board. 2. Shift the resonant frequencies of the board by adding decoupling capacitors on the board. 3. Study the voltage fluctuations between the power and ground planes of the board during driver switching using the behavioral model of the driver. 4. Study the signal skew introduced by Simultaneous Switching Noise (SSN). TRANSLATION PROCEDURES The translation is done in two steps: 1. Demo.brd (in binary brd format) is converted to a text file, demo.txt, using Cadence extract.exe. See Translators User s Guide for details of converting a binary brd file to text format using the Cadence utility program, extract.exe. 2. The Cadence translator, SPDLinks.exe, converts an Allegro layout file to a SPEED2000 spd file. EXAMPLES1 3

8 Translation Steps We assume the text file, demo.txt, has already been built in Step 1. Each net has the following color assignment: Net D2 in GREEN Net D3 in BLUE Net D4 in MAGENTA Net GND in YELLOW Net VCC in RED 1. Launch SPDLinks.exe. 2. Select the Cadence Allegro input file: demo.brd The file is located in the Samples folder. 3. Click on Settings... button. The Settings dialog appears. EXAMPLES1 4

9 4. Click OK to accept all the default settings.. 5. Click on Nets... button. The Net Choice window appears. EXAMPLES1 5

10 The Net Choiceion window shows the available nets in the BRD file for translation and the default color assigned to each net. By default all nets are selected to translate. 6. Click on Clear all button to deselect all nets. 7. Select the following five nets: D2, D3, D4, GND and VCC. In the left pane of the Net Choice window, you can select multiple nets by holding down the CTRL key while clicking on the net names, or use the SHIFT key to select a range of nets. 8. Click. The selected nets are listed in the right pane. EXAMPLES1 6

11 9. Click OK to close Net Choice window. 10. Click on Translate button. The.spd file is generated. 11. Click on Exit button or click to close the SPDLinks dialog. EXAMPLES1 7

12 Using a New Circuit: Vsource 1. Launch SPDGEN.exe to load the SPD file, demo.spd. 2. To load the circuit library prepared for this exercise, select: Setup > Circuit/Linkage Manager 3. Click Load. 4. In the Open dialog, go to: <INSTALL_DIR>\Translators\Samples\BRDExtractor Samples\ 5. Load the file circuits.ckt 6. Click OK. 7. Select the Model Name source in the Circuit/Linkage Manager window. Source Vs 2 0 Gaussian( n 0.7n 1) Rs EXAMPLES1 8

13 8. Click on the New button. The New window pops up 9. Select New Circuit. 10. Click OK. It automatically creates a new circuit using the circuit prototype source. 11. Name this new circuit Vsource in the New Circuits dialog. EXAMPLES1 9

14 12. Click OK. 13. Connect circuit node 0 of Vsource to a GND package node. 14. Connect circuit node 1 of Vsource to a VCC package node. EXAMPLES1 10

15 15. Select: Setup > Mesh 16. Click on the Automatically Generate Mesh button. 17. Select Specify Simulation Time in workflow or select Setup > Transient 18. Set Transient simulation time to be 50ns. 19. Click OK to accept the default settings. EXAMPLES1 11

16 Specify Observations Observations setting contains two parts: Voltage and Current. Specify Observations (Voltage) Follow the steps below to set one Circuit Voltage curve for the voltage between the VCC (node 1) and GND (node 0) of the Vsource. 1. Select Specify Observations (Voltage) in workflow. The Circuit Voltage View window opens. 2. Select Vsource. 3. Left-click on VCC and right-click on GND. 4. Click on the Add button. 5. Click OK to accept all settings. Specify Observations (Current). 1. Select Specify Observations (Current) in workflow. The Current View window opens. 2. Select Rs under Vsource. 3. Click on the Add button. EXAMPLES1 12

17 4. Click OK to accept all settings. After observations(voltage) and obeservation(current) are both specified, you can: 1. Save the file as: s2k_demoopen.spd 2. Check the error log file s2k_demoopen_generator.err 3. Make sure there are no errors. 4. Select Start Simulation in workflow. Or Load the s2k_demoopen.spd file into SPDSIM. EXAMPLES1 13

18 Run Simulation 1. Obtain the power and ground plane input impedance through Fourier transforms of transient voltage and current. An example is shown in the next figure. NOTE! 1. Should select Amplitude mode. 2. Use FD Cacl...->Simple Calculation to caculate V1/C1. Using Model Type, Edge Term 1. Launch SPDGEN. 2. Open demo.spd 3. Create a circuit, Redge, using the Model type, Edge Term. 4. Activate the Signal$BOTTOM layer. 5. Connect the resister, Redge, at the edge of the board between all VCC and GND pins. EXAMPLES1 14

19 EXAMPLES1 15

20 6. Change the simulation time to 20ns. 7. Save the file as s2k_demoshort.spd. 8. Check for errors. 9. Run the simulation in SPDSIM. With the resister, Redge, the computed input impedance of the power and ground systems looks like the curve shown in the next figure. EXAMPLES1 16

21 LowFrequency Effective Power / Ground Inductance Obtain low-frequency effective power / ground inductance. Impedance is divided by Omega. EXAMPLES1 17

22 Using Model Definition, Decap 1. In SPDGEN, open s2k_demoshort.spd 2. Create the following circuits using the Model definition: Decap: cap1, cap2, cap3, cap4, cap5, cap6 EXAMPLES1 18

23 3. Connect six decap circuits between VCC and GND at the locations indicated. EXAMPLES1 19

24 4. Save the file as s2k_demodecaps.spd. 5. Re-run the simulation in SPDSIM in order to get the power / ground input impedance with six decaps. EXAMPLES1 20

25 Low Frequency Effective Power / Ground Inductance Obtain low-frequency effective power / ground inductance. Below 400 MHz, impedance is divided by Omega. EXAMPLES1 21

26 Using Model Definition: Driver 1. Return to SPDGEN. 2. Close the current project. 3. Opens s2k_demoopen.spd. 4. Delete the circuit, Vsource. 5. Create a circuit, Vcc1, using the VCC model definition. 6. Connect Vcc1, the DC supply at the edge (the VCC and GND pins), at Signal$BOTTOM. 7. Create a circuit, drv1, using the model definition, Driver. 8. Activate Signal$TOP. 9. Connect: Ground node (node Nvss) of the driver to a nearby GND pin. Output node (node out) of the driver to trace D2. Power node (node Pvdd) of the driver to a nearby VCC pin. EXAMPLES1 22

27 Driver Gpmos Pvdd Out VCR PWL(1) IC=0 Gnmos Nvss Out VCR PWL(1) IC=0 Vvcr sinesquar( p 300p 300p 600p 2n ) rvcr Rlarge 1001 Out Create a circuit, Rpd1, using the model definition, Term. 11. Activate Signal$TOP. 12. Connect: Node 1 of the pull-down resister to Trace, D2. Node 2 of the resistor to the nearby GND pin. Rterm Rterm EXAMPLES1 23

28 13. Open the Transient dialog. 14. Select: Enable the Initial DC Analysis EXAMPLES1 24

29 Set Curves 1. Open the Circuit Voltage View dialog. 2. Set one Circuit View curve for output voltage of the driver, drv1. 3. Set another Circuit View curve for voltage across the pull-down resister at the receiving end. 4. Save the file as s2k_demovcr_1drv.spd. 5. Save the file again for error checking. 6. Re-run the simulation in SPDSIM. 7. Save the driving end and receiving end voltage waveforms of net D2. EXAMPLES1 25

30 Using the Model Definition: VCC 1. Return to SPDGEN. 2. Load the file, s2k_demodecap.spd. 3. Open the Circuit Manager. 4. Delete the circuits: Vsource and Redge. 5. Create a new circuit, Vcc1, using the model definition, VCC. 6. Activate Signal$BOTTOM 7. Link Vcc1 to the VCC and GND pins. 8. Create a circuit, drv1, based on the model definition, ibisdrv. 9. Activate Signal$TOP 10. Connect nd_out (the output node) of the driver to Trace D2. nd_pu (the pullout node) and nd_pc (the power clamp node) to a nearby VCC pin. nd_pd (the pull-down node), the GND node, and nd_gc (ground clamp node) to a nearby GND pin Driver B_output nd_pu nd_pd nd_out nd_in gnd nd_pc nd_gc + file='demo.ibs' model='output_demo' V_in nd_in gnd pulse ( 0V 1.0V 0n 0.1n 0.1n 3.65n 7.5n) EXAMPLES1 26

31 11. Create a circuit, Rpd1, using the model definition Rterm. 12. Activate Signal$TOP 13. Connect Node 1 of the pull-down resister to trace D2. Node 2 to a nearby GND pin. 14. Open the Transient dialog. 15. Select Enable Initial DC analysis 16. Set the simulation time to 15 ns. EXAMPLES1 27

32 Set Curves 1. Open the View Circuit Voltage dialog. 2. Set different curves for: Voltage between nd_out and gnd of the driver. Between nd_pu and gnd of the driver. Between nodes 1 and 2 of the pull-down resistor. 3. Save the file as s2k_demoibs_1drv.spd. 4. Save the file again for error checking. 5. Re-run the simulation in SPDSIM. Observe the voltage at the driving and receiving ends of net D2. Note the power / gnd noise between the supply and gnd, as well as at the receiving location. 6. Save all three curves. EXAMPLES1 28

33 Curve Example EXAMPLES1 29

34 Using s2k_demovcr_1drv.spd 1. Return to the SPDGEN application to the file. 2. Open the file s2k_demovcr_1drv.spd 3. Create the following drivers and termination resistors: drv2, drv3 using the model definition, Driver Rpd2, Rpd3 using the model definition, Rterm. 4. Connect the following drv2, Rpd2 to net D3 drv3, Rpd3 to net D4 5. Add observation points at the driving and receiving end of net D3 and D4. EXAMPLES1 30

35 6. Save the file as s2k_demovcr_3drv.spd 7. Save the file again. The program checks for errors. 8. Re-run the simulation. 9. Compare the waveforms on net, D2, with multiple switching and single switching. 10. Notice the extra delay that is introduced by the SSO even mode push-out. EXAMPLES1 31

36 Using s2k_demoibis_1drv.spd 1. Return to the SPDGEN application to the file. 2. Open the file s2k_demoibis_1drv.spd 3. Create the following drivers and termination resistors: drv2, drv3 using the model definition, Driver, connect to D3. Rpd2, Rpd3 using the model definition, Rterm, connect to D4. 4. Connect drv2, Rpd2 to net D3. 5. Connect drv3, Rpd3 to net D4. EXAMPLES1 32

37 6. Add observation points at the driving and receiving end of net D3 and D4. 7. Save the file as s2k_demoibs_3drv.spd 8. Save the file again to check for errors. 9. Compare the waveforms on net, D2, with multiple switching and single switching. 10. Notice the extra delay that is introduced by the SSO even mode push-out. 11. Note additional power / gnd noise with three drivers switching instead of one driver. EXAMPLES1 33

38 EXAMPLES1 34

39 SPEED2000 Examples Index A Allegro file 3 Allegro layout file 3 B behavioral model of the driver 3 binary brd file to text 3 binary brd format 3 brd2spd.exe 3, 4 C Cadence Allegro input file 4 Cadence translator 3 check for errors 16, 33 circuit definition source 8 circuit view curve 25 circuit voltage view 25 color assignment 4 compare the waveforms 31, 33 computed input impedance 16 connect circuit node 0 10 connect circuit node 1 10 connect nodes 22 conventions 1 create a circuit 26 D DC supply at the edge 22 decap 20 decap circuits 19 default settings 5 demo.brd 3 demo.spd 8, 14 demo.txt 3, 4 driver 23 driver, drv1 25 drivers and termination resistors 30 driving and receiving end of net 30, 33 driving end and receiving end voltage waveforms 25 drv1 22 E Edge Term 14 enable the initial DC analysis 24 error checking 25, 28 error log file 13 extra delay 33 extract.exe 3 F fourier transforms 14 fourier transforms of transient voltage and current 8 G GND 19, 28 GND package node 10 GND pin 22 J ibisdrv 26 impedance is divided by Omega 17 input impedance 20 L launch SPDGEN.exe 8 load the circuit library 8 low-frequency effective power / ground inductance 17 low-frequency effective power/ground inductance 21 M mesh 11 mode push-out 31 model definition box 8 model definition, decap 18 model definition, term 23 model type, edge term 14 multiple switching and single switching 31 multiple switching and single switching. 33 N nd_out 26 nd_pd 26 nd_pu 26 net D2 28 O observation points 30, 33 obtain the power and ground plane input impedance 14 oltage across the pulldown resister 25 Omega 21

40 SPEED2000 Examples output voltage 25 P power and ground planes 3 power and ground systems 16 power/ground inductance 21 power/ground input impedance 20 power/ground noise 33 R Redge 14, 16 re-run the simulation 20, 25, 28 resonance properties 3 Rpd1 23 Rterm 27 run the simulation 14 transient dialog box 24, 27 translation procedures 3 W VCC 26 VCC and GND 19 VCC and GND pins 14 VCC package node 10 VCC pin 22 VCC1 22 view circuit voltage 28 voltage 28 voltage fluctuations 3 Vsource 22, 26 S save curves 28 set curves 28 settings dialog box 4 signal skew 3 Signal$BOTTOM 22, 26 Signal$BOTTOM layer 14 Signal$TOP 22, 23 simulation time 16 simultaneous switching noise 3 SPDGEN 14, 18, 26 SPDSIM 13, 16, 20, 28 SSN 3 SSO 31 T three drivers switching 33