CAD Interfaces Translator Notes. Product Version Sigrity 2017 December 2016

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1 Product Version Sigrity 2017 December 2016

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3 Table of Contents Contents 1 Introduction 2 CAD Interfaces Translator Notes ODB++ for Most PCB Design Tools Package/Board/SIP Design - Cadence PCB Design - Zuken, Visula CR-5000 and CR-8000 Board Designer Visula PCB Design - Altium P-CAD (ODB++ Recommended) PCB Design - Mentor Graphics - Boardstation Option1: Direct.SPD link Option2: Manual.SPD Generation from Board Station Files PCB Design - Mentor Graphics - Expedition PCB Design - YDC Cadvance αiii Design PCB Design - Mentor Graphics - PADS (Formerly PowerPCB, Padslayout) PCB Design - Mentor Graphics General Tips for Successful Translation Specific NDD* Related Tips 3 Q & A Zuken FAQ Translator FAQ 4 Appendix December Product Version Sigrity 2017

4 Table of Contents Appendix: Mentor Board Station Translation Installation of the Direct SPD Interface Manual Database Translation Appendix: Free Layout Viewers December Product Version Sigrity 2017

5 Introduction 1 Introduction This chapter introduces the CAD tools. IC Package Design tools: Cadence - APD, SIP PCB Design tools: ODB++ - All CAD tools that support ODB++ output (Expedition, Boardstation, Altium) Cadence - Allegro, PCB SI, Specctra Router Mentor - Board Station, Expedition, Padslayout, ICX Zuken - CR-5000/8000, Visula Altium - Altium Designer pre-version 10 only (Protel), P-CAD YDC - Cadvance αiii Design December Product Version Sigrity 2017

6 CAD Interfaces Translator Notes 2 CAD Interfaces Translator Notes ODB++ for Most PCB Design Tools The most PCB design tools mentioned here include Altium, Mentor Boardstation, Expedition, Zuken, PCAD. Most CAD tools now support ODB++. To translate the ODB++ file to.spd file, follow the steps below: 1. In the CAD Design tool's menu, select File - Export ODB++ to create the ODB++ file. Be sure to enable all options so that you get the most complete data set possible. 2. View the ODB++ database using Mentor's ODB++ viewer to be sure your design is in the desired state. If it is not, update the design in the CAD tool, and regenerate the ODB++. ODB++ output should be written to a compressed archive with these typical extensions:.zip.tgz.tar.z.gz.7z 3. Run SPDLinks.exe, and select the ODB++ file browser filter. 4. Browse to the ODB++ file. 5. Modify your settings as needed. 6. Modify the net set if applicable. 7. Press the Translate button. Sigrity modules: SPDLinks.exe, ODBExtractor.dll December Product Version Sigrity 2017

7 CAD Interfaces Translator Notes Package/Board/SIP Design - Cadence To translate the MCM,.SIP, or.brd file to.spd file, follow the instructions below: A working Cadence environment is required. Contact Cadence support for help setting one up Cadence.mcm/.sip/.brd files are binary. Cadence Extracta.exe will output ASCII format which Sigrity translators uses to generate our SPD file SPDLinks BRDExtractor runs Extracta.exe and generates the SPD. Specify the extracta and env paths using SPDLinks > settings > environment tab To determine the design file version: On Allegro Package Designer installed machine, in command prompt: dbstat filename.mcm System will return the version To prevent unknown problem by incorrect.mcm database: On Allegro Package Designer installed machine, DOS command prompt type: >dbdoctor filename.brd Sigrity module: SPDLinks.exe, BRDExtractor.dll PCB Design - Zuken, Visula CR-5000 and CR-8000 Board Designer To translate the.pcf,.ftf,.dsgf, or.mrf file into.spd file, follow the instructions below: These files are the Zuken database in a non-compressed ASCII format Licensed Board Designer software is required To generate.pcf and.ftf files: 1. Open a command window. 2. Change to design directory. >pcout filename (no file suffix) will create filename.pcf. December Product Version Sigrity 2017

8 CAD Interfaces Translator Notes >fcout filename (no file suffix) will create filename.ftf. Refer to Zuken documentation on how to generate dsgf and mrf CR-8000 files 3. Place the two files in the same folder. Filename.mrf is optional. 4. Launch SPDLinks and select CR5000 (*.pcf;*.ftf;*.mrf) as the file format to be translated. 5. Choose any of the.pcf,.ftf or.mcf file, and the design will be translated. Sigrity modules: SPDLinks.exe, CR5000Extractor.dll Visula To translate the.rif file into.spd file, follow the steps below: 1. Generate a.rif file from Visula. 2. Use rif2spd.exe to translate RIF to SPD. Sigrity modules: RIF2SPD.exe PCB Design - Altium For the recommended flow, refer to the section ODB++ for Most PCB Design Tools. P-CAD (ODB++ Recommended) To translate the.pcb file into.spd file, follow the steps below: 1. Export ODB++ with all entities enabled. 2. Use SPDLinks to translate DesignName.zip or.tgz to DesignName.SPD. Sigrity modules: SPDLinks.exe, ODBExtractor.dll PCB Design - Mentor Graphics - Boardstation To translate the ODB++ file into SPD file, two options are recommended: Use SPDLinks with ODBExtractor December Product Version Sigrity 2017

9 CAD Interfaces Translator Notes Generate ODB++ from Boardstation Sigrity modules: SPDLinks.exe, ODBExtractor.dll Option1: Direct.SPD link This is an integrated flow, requiring working licensed seat of Mentor Boardstation. 1. Direct export of SPD file from the Mentor Board Station Interface (installation instructions in appendix). 2. After installation, choose Export to Sigrity SPD file from the Boardstation menu. Option2: Manual.SPD Generation from Board Station Files If you have access to the Mentor Board Station database, but not to Mentor Board Station itself, this procedure can be used. The method uses the Sigrity SpdLinks program and 4 files from the layout database: "geoms.geoms_nn", "neutral_file", "tech.tech_nn" and"traces.traces_nn". More information in appendix. Sigrity modules: SPDLinks.exe, BoardStationExtractor.dll PCB Design - Mentor Graphics - Expedition December Product Version Sigrity 2017

10 CAD Interfaces Translator Notes This section is not continued with the previous one. Generate an ODB++ file and use SPDLinks instead. Sigrity modules: SPDLinks.exe, ExpeditionExtractor.dll PCB Design - YDC Cadvance αiii Design The SPD file is generated using SpdLinks and the DBR, DBG and NET output from Cadvance. To translate the.dbr,.dbg, or.net file to.spd file, follow the procedure below: 1. In Cadvance, output the Design.dbr and Design.dbg files. 2. In output connection data, select the output property text option, and write the netlist to Design.net in the same directory. 3. Open SpdLinks. 4. Choose the Cadvance dbr files file type, and open the Design.dbr file. 5. Click Translate. The SPD output will be written to Design.spd. Sigrity modules: SPDLinks.exe, CadvanceExtractor.dll PCB Design - Mentor Graphics - PADS (Formerly PowerPCB, Padslayout) PADS2SPD does not support negative plane layers. Plane layers must be split/mixed and poured prior to exporting ASCII. To pour: 1. Choose Tools > Pour Manager. 2. In the Plane Connect tab, select All, and then start. 3. Answer Yes to OK to connect planes. 4. In the Hatch tab, choose Hatch All and press Start 5. In the Flood tab, choose Flood All and press Start. To export ASCII in PADS: 1. In Setup > Preferences > Split/Mixed Plane, set Save to PCB to All Plane Data, and set Mixed December Product Version Sigrity 2017

11 CAD Interfaces Translator Notes Plane Display to Generated Plane Data. 2. In File > Export, set file type to ASCII (.asc), and click Save. 3. In the ASCII Output window, click the Select All button to choose all sections. 4. Set Units to Basic. 5. Select the Expand attributes boxes for Parts and Nets. 6. Click OK. 7. Translate the ASC file to SPD using Pads2SPD.exe. Sigrity modules: PADS2SPD.exe PCB Design - Mentor Graphics To translate the.icx file to.spd file, follow the instructions below: Not a direct export from within ICX, instead, the translation relies on a bat file included with ICX that allow bidirectional translation between ICX and NDD files Use the xform.bat utility to convert from.icx to.ndd Usage: xform -extract_ndd -icx <FileName.icx> -ndd <FileName.ndd> -log <FileName.log> Location: %MGC_HOME%\bin\xForm.bat Use the Ndd2Spd translator to generate the.spd file Refer to the NDD related tips in the section Specific NDD* Related Tips. Sigrity modules: NDD2SPD.exe General Tips for Successful Translation If your CAD tool can generate ODB++ please try the SPDLinks ODB++ translator, view the file in the ODB viewer to be sure it is analysis-ready Make sure planes are poured before export (in case you have static pour) Do Not pour using stroked lines, they cause problems and lead to unmanageable file sizes and node count Define as much of the stackup as possible in the layout tool (i.e. thickness, conductivity, December Product Version Sigrity 2017

12 CAD Interfaces Translator Notes dielectric constant and loss tangents). This will make the most efficient translation flow Alternatively, it is possible to keep one master.spd file for each stackup type, and then use the "Import" button in the stackup editor in the Sigrity tools to reuse it Make sure all vias are assigned a padstack. If antipads are defined as part of the planes and not the padstack the simulation results will be less accurate or manual correction will be required after translation Specific NDD* Related Tips Output ODB++ and use the ODB++ SPDLinks translator instead for best results If you insist on NDD be warned that the NDD format is incomplete for describing a PCB layout. This implies that some conducting areas / copper shapes are not included. The Sigrity NDD2SPD translator allows you to link to an ascii file that contains the relevant data - this is the Layout.hkp file which is typically included when using an ICX export from a layout tool If NDD file comes from Mentor Board Station thermal ties can be included by linking to a trace.trace_nn file (see ref [1,39pp]) The IBIS files used in the ICX project can be automatically included in the translation if a subfolder named "IBISModles" is placed in the main directory with the.ndd file. All the models can automatically be exported from within the IS tool from the menu File > Export > Models NDD is an abbreviation for Neutral Design Data. Sigrity modules used: ndd2spd.exe December Product Version Sigrity 2017

13 Q & A 3 Q & A Zuken FAQ Q: What are the Zuken CR5000 ascii file output anyway? A: The files represent the Zuken database in a non-compressed ASCII format that allows them to be read by 3rd party software. The ASCII output consists of four (4) files: name.pkf (Footprint Referrences) name.prf (Parts File) name.ftf (Footprint File) name.pcf (PCB Layout File) name.mrf (Material Definition File) Q: How to generate ASCII output (.pcf and.ftf) from Zuken CR5000 (Zuken Redac Board Designer)? A: Two Board Designer command-line de-compile utilities, pcout and ftout, must be run against the design in order to produce the required.ftf and.pcf files. This procedure should be run on a system that has the Board Designer software installed and Licensed and also has access to the design data to be worked with. 1. Open a Command Prompt (DOS shell). 2. Change Directory to the design directory. 3. Execute the following command: pcout BASENAME. BASENAME refers to the basename of the pcb and pcf (without file suffix). There are many other options which can be specified with the pcout command. To get a list of these options and usage instructions simply run "pcout" at the command prompt. This will produce a file 'basename.pcf'. This is the.pcf file. 4. Execute the following command: ftout BASENAME. December Product Version Sigrity 2017

14 Q & A BASENAME refers to the basename of the ftp (or pcb, pnl) and tft (without file suffix). There are many other options which can be specified with the ftout command. To get a list of these options and usage instructions simply run "ftout" at the command prompt. This will produce a file 'basename.tft'. This is the.tft file. If running these commands produces the message: 'pcout' is not recognized as an internal or external command, operable program or batch file, or 'ftout' is not recognized as an internal or external command, operable program or batch file, there are two possibilities: One - The de-compilers or the Board Designer software is not installed on your workstation and will need to be installed Two - The location of the de-compilers is not part of the workstations 'PATH' variable and this location will need to be added to the 'PATH' variable or the full path and executable will need to be specified at the Command Prompt Translator FAQ Q: For the NDD translator I see possibility to include a "Layout.hkp" file. What is that used for? A: We now recommend you generate ODB++ from Mentor and use SPDLinks ODB++ option. But if you insist, the NDD format unfortunately has some inherent flaws that cannot be accommodated for in the format. This implies that some conducting areas / copper shapes are not included. The Sigrity NDD2SPD translator thus allows you to link to another layout description which can include these missing shapes. The translator uses the ASCII HKP output that were generated from Expedition but have since been discontinued by Mentor. Use ODB++ flow instead. Q: I am translating a package layout from APD / Allegro Package Designer and the wirebond layers are not converted correctly. What could be wrong? A1: The automatic conversion of wirebond layers by our SPDLinks BRDExtractor requires each die have the "COMP_WIRE_BOND" flag set in APD. This normally occurs by default if the design has been created according to Cadence standard procedures. A2: If you have the a special XML file describing the wirebond models rename it so it has the same name as the design. So for a DesignName.sip you should have a DesignName.xml so SPDLinks knows to get the actual wirebond models. If not found it will creates generic December Product Version Sigrity 2017

15 Q & A wirebond profiles which you can modify using the "Wirebond Model Library" in the Sigrity analysis tool. Q: How to set the COMP_WIRE_BOND flag in APD in very old designs (not needed in a properly defined design) A: Please follow below procedure: 1. Set up Property Definitions. 2. In the Name box, enter COMP_WIRE_BOND, and click the tab key. 3. Uncheck all Data Elements except Comps. 4. Set Data Type as BOOLEAN, and click OK to exit the form. 5. Edit Properties, and set Find box Comps only. 6. Click a die pin. 7. When the form pops-up, select COMP_WIRE_BOND from available properties. 8. Make sure the Value is TRUE, and click OK to close the form. 9. Now the COMP_WIRE_BOND flag should be set: REFDES COMP_CLASS COMP_PACKAGE COMP_DEVICE_TYPE COMP_WIRE_BOND BGA IO BGA BGA DIE IC DIE DIE YES Q: Some interconnect is missing in a layout that was translated, Why? A1: If an object has no net it will be ignored if the "Include elements with no net names" setting is disabled. Q: How do I translate a.sip,.mcm, or.brd file? A: First install the Cadence free viewer (follow the link at the end of the appendix) then run SPDLinks and use the environment tab of the settings section. Browse to the env and extracta.exe found in your company's Cadence installation. If you still have difficulty, contact si-support@cadence.com for assistance. Q: The translated SPD file only shows some component values and others are completely empty. Did something go wrong in the translation? A: Typical design databases have only capacitors, inductors and coils defined with default values - i.e. no parasitics. We suggest you maintain a circuit library with the appropriate model definitions, which can quickly be merged with the SPD file after translation. December Product Version Sigrity 2017

16 Q & A Q: My design contains negative plane layers. When I translate the board they are not handled correctly, what could be wrong? A1: We suggest trying ODB++ because the manufacturing ready plane data is stored in ODB++. A2 If the design comes from Mentor Board Station and you insist on using that interface, please make sure that all split-plane layer information is defined on power layers within Mentor Board Station. A3: If the design comes from PADS we do not support negative planes. Have your CAD department convert them to positive or use ODB++ if available. December Product Version Sigrity 2017

17 Appendix 4 Appendix Appendix: Mentor Board Station Translation Installation of the Direct SPD Interface 1. Download the integration scripts from Cadence website: 2. Unzip the sigrity_interface directory to the <MGC_HOME>/pkgs directory. 3. Setup the AMPLE_PATH environment variable to point to the <MGC_HOME>/pkgs/sigrity_interface/userware/En_na directory. 4. Export the design from the Top Menu as shown in the following figure (Export to Sigrity SPD File). For the details, refer to the appendix of Translators User Guide. Sigrity modules used: SPDLinks.exe, BoardStationExtractor.dll Manual Database Translation December Product Version Sigrity 2017

18 Appendix Manual Database Translation 1. Create a new directory. 2. Locate the latest geometry, neutral, tech, and traces file in the Mentor Board Station directory, and place them in the newly created directory. The latest files are typically indicated by a number suffix. The file that has the highest suffix is the latest files The files must be ASCII - sometimes the geometry file is appended with _ascii The neutral file is often found in the mfg directory, and the rest of the files are in the main pcb directory 3. Rename the four files as MentorGeometryFile, MentorNeutralFile, MentorTechFile, and MentorTracesFile respectively. 4. Open SpdLinks. 5. Select file type as Mentor Boardstation Files (Folder). 6. Navigate to the directory in Step Click Open Folder. 8. Type a name for the translated file, and click OK. Sigrity modules: SPDLinks.exe, BoardStationExtractor.dll Appendix: Free Layout Viewers Some free layout viewers are listed in this section. You can refer to them when you do not have access to the layout software. Altium: Cadence viewers: Mentor Board Station / Expedition: ODB++ Viewer: December Product Version Sigrity 2017

19 Appendix Zuken Board Designer Viewer (CR5000): Zuken CADSTAR Design Viewer: Cadvance Design Viewer: Links updated on May 18, 2010 December Product Version Sigrity 2017