Allegro PCB PDN Analysis User Guide

Transcription

1 Product Version 16.6 October 2012 Document Last Updated On: November 20, 2012

2 Cadence Design Systems, Inc. All rights reserved. Portions Apache Software Foundation, Sun Microsystems, Free Software Foundation, Inc., Regents of the University of California, Massachusetts Institute of Technology, University of Florida. Used by permission. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Allegro PCB PDN Analysis contains technology licensed from, and copyrighted by: Apache Software Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA , Apache Software Foundation. Sun Microsystems, 4150 Network Circle, Santa Clara, CA USA , Sun Microsystems, Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA USA 1989, 1991, Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, 2001, Regents of the University of California. Daniel Stenberg, , Daniel Stenberg. UMFPACK 2005, Timothy A. Davis, University of Florida, Ken Martin, Will Schroeder, Bill Lorensen , Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts, USA 2003, the Board of Trustees of Massachusetts Institute of Technology. All rights reserved. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence s trademarks, contact the corporate legal department at the address shown above or call Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modified in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR and DFAR et seq. or its successor.

3 Contents 1 Introduction The Challenge: Power Integrity in High Speed PCB Design The Solution: Allegro PCB PDN Analysis Overview The PDN Analysis Flow Tasks Involved in PDN Flow Use Model and Methodology PDN Analysis Prerequisite Tasks Launching the PDN Analysis GUI Assigning Voltage Selecting Nets for Analysis Calculating Target Impedance Managing Decoupling Capacitors Specifying Ports Information Specifying Excitation Single Node Analysis Overview Voltage Regulator Modules Running a Single-Node Simulation Static IR Drop Analysis Overview Performing Static IR Drop Analysis October Product Version 16.6

4 5 Model Extraction Analysis Model Extraction Running Model Extraction Analysis Power Integrity Analysis Overview Power Integrity Analysis PDN Analysis GUI Reference PDN Analysis Power and Ground Decoupling Capacitor Management Components and Ports Parameters Setting Target Impedance Editor Power/Ground Nets Selection Decoupling Capacitor Library Management Decoupling Capacitor Model Editor Intrinsic Inductance (ESL) Estimator Create/Browse Decoupling Capacitor Signal Model Histogram Port Group Configuration Return Path Configuration Return ground pin selection Virtual Excitation Browser Virtual Excitation Management VRM Model Cadence-Standard VRM Editor VRM Input Inductance Calculation Layer Management October Product Version 16.6

5 Padstack Plating Parameters Virtual VRM Management Virtual VRM Virtual Noise Management Virtual Noise Virtual Probe Management Virtual Probe Editing in Context Using PDN EMViewer Overview The 3D EMViewer Interface Menus Toolbars Windows Working with PDN EMViewer Launching PDN EMViewer Opening.emv Files Analyzing PDN Analysis Results Co-Analysis Capabilities Overview Adding Power Supply from Other Boards Settings for Die-Package-Board Co-Analysis Plotting Probe Ports on Die Pads October Product Version 16.6

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7 1 Introduction Topics in this chapter include The Challenge: Power Integrity in High Speed PCB Design on page 8. The Solution: Allegro PCB PDN Analysis on page 9. Overview on page 9 The PDN Analysis Flow on page 11. October Product Version 16.6

8 Introduction The Challenge: Power Integrity in High Speed PCB Design As clock and data frequencies increase and high-speed systems become more densely populated, noise-free power delivery becomes a major challenge for PCB design. When fast switching devices change state simultaneously, power flow ripple propagates through the power delivery system as noise that varies with frequency. This noise can, in turn, disturb surrounding high-speed devices. Important Without adequate power, highspeed components behave unpredictably. To ensure that high-speed systems continue to deliver the required performance at these new levels, power delivery impedance has to be controlled over a wider range of frequencies. This is accomplished through careful consideration of the design of the switching power supply, bulk capacitance, ceramic capacitance, and power and ground plane-pairs over the frequencies of interest. Figure 1-1 shows where, in the frequency spectrum, each component in the power delivery system is most effective at controlling target impedance. Important Capacitors provide (1), a local source of voltage for nearby active devices and (2), a low impedance path to ground for noise. Figure 1-1 Components in a Power Delivery System Impedance Switching Power Supply Electrolytic (bulk) Capacitors Ceramic Capacitors Powerplane Pairs 1 Hz 1 khz 1 MHz 1 GHz October Product Version 16.6

9 Introduction Decoupling capacitors provide a local source of charge for drivers requiring a significant amount of supply current in response to logic switching. Tip Capacitors exhibit parasitic inductance that limits their effective frequency range; therefore, you should explore mounting methods that help to minimize inductance. The Solution: Allegro PCB PDN Analysis The Allegro PCB Power Delivery Network (PDN) Analysis solution provides a new unified use model to the erstwhile Allegro Power Integrity solution. The new solution performs exploration, design and verification functions for power distribution system design. It helps maintain low power distribution system impedance across a wide band of frequencies eliminating several EMI issues. In addition, this solution provides a powerful method of identifying and eliminating potential EMI problems. The main objectives of the PDN Analysis solution are: To locate hot spots of current and temperature To guide stack-up design and plane / shape split scheme To optimize decoupling capacitors selection and placement to avoid over- and underdesign To quickly check the resonant frequencies of power network system To accurately verify power nets with full wave technology Overview This is an overview of the Power Delivery Network Analysis solution. Detailed information about these are covered in the subsequent chapters of this user guide. Uniform environment for all PDN-related setup and analysis Mesh Analysis Single Node Static IR Drop Voltage drop October Product Version 16.6

10 Introduction Current distribution Current density Temperature Power Integrity Model Extraction Net-based analysis No longer plane-pair based No requirements on overlapping power and ground shapes Multiple DC Nets are allowed with coupling Full wave solving Optional equivalent model Debye model, frequency dependent materials, support MoM algorithm with adaptive meshing Multi-board and Die-Package-Board configurations VRM on same board or through connected card subcircuit board - package - die - load setup with port groups and pin mapping Shape editing capabilities added to PCB SI editors - The new Allegro shape editing commands add to the what-if capability as well as enhance overall integration. Choose the Shape Select Shape or Void menu command. 3D visualization along with reports and standard waveforms Virtual elements (VRM, Noise, Probe) October Product Version 16.6

11 Introduction The PDN Analysis Flow The following flowchart depicts the basic PDN analysis flow: October Product Version 16.6

12 Introduction Tasks Involved in PDN Flow The high-level flow requires following tasks to be performed: 1. Prepare for cross section/stackup, identify DC net, board outline, route keep in and keep out, and so on. 2. Create power ground plane/shapes initially. 3. Add virtual VRMs and virtual noise sources. 4. Place some decoupling capacitors initially. 5. Perform frequency domain impedance analysis to adjust stackup, plane shapes, to add more decoupling capacitors, to refine placement of decoupling capacitors, and to refine placement of virtual VRMs and virtual noise sources. 6. Perform static IR drop analysis, to continue optimizing stackup, plane shapes, decoupling capacitors, virtual VRMs and virtual noise sources. 7. Replace virtual VRMs with actual power supply modules and assistant circuit like rectifier circuit. Power supply modules can be switching power source, IC components like DC/ DC converter, or even IO connectors. 8. Assign VRM models to power supply modules. 9. Replace virtual noise sources with actual IC components or IO connectors. 10. Configure those IC components or IO connectors including sink current profile, port group, chip/package model and chip-package-board pin mapping if need to do cosimulation. 11. Route the whole PDN. 12. Optimize components placement, plane shapes and routing by doing frequency domain impedance analysis and IR drop analysis again. 13. Place and route signal network, do SI analysis and SSN analysis, do some small changes on PDN, if needed. 14. Do post-layout verification using the four types of PDN analysis. October Product Version 16.6

13 2 Use Model and Methodology October Product Version 16.6

14 Use Model and Methodology PDN Analysis Prerequisite Tasks As with any SI, PI, or electrical constraint related tasks, setting up the database is an essential prerequisite task in PDN Analysis as well. The new unified PDN Analysis GUI guides you through the tasks involved in setting up the database. Note: You can optionally run through the complete SI setup process using the Setup SI Design Setup command. For information on this command, see signal setup in the Allegro PCB and Layout Command Reference: S Commands. The prerequisite tasks include: Launching the PDN Analysis GUI Assigning Voltage Selecting Nets for Analysis Calculating Target Impedance Managing Decoupling Capacitors Launching the PDN Analysis GUI 1. To start the PDN Analysis application, choose Analyze PDN Analysis. October Product Version 16.6

15 Use Model and Methodology The main PDN Analysis form displays the Power and Ground tab. This form lists the mandatory and recommended prerequisite tasks and how to perform them. For information on this form, see Power and Ground on page 59. Assigning Voltage Before you select nets for analyzing, you need to ensure that the power and ground nets in the design have VOLTAGE property associated with them. You can assign appropriate VOLTAGE property to the power and ground nets in the Identify DC Nets dialog box: 1. Click Identify DC Nets. October Product Version 16.6

16 Use Model and Methodology A warning message pops-up if the design contains DC nets which do not contain any power or ground pins. For detailed information on this dialog box, see identify nets. Selecting Nets for Analysis 1. Click Select DC Nets. October Product Version 16.6

17 Use Model and Methodology If there are no nets in the design with the VOLTAGE property, this form appears blank. At this stage, you can click the Identify DC Nets button to assign appropriate VOLTAGE property to the power and ground nets: 2. Select the net(s) you wish to analyze and move them from the Available power/ground nets list to the Selected power/ground nets list. 3. Click OK to confirm. The selected nets appear on the main form. Calculating Target Impedance Target impedance is a key parameter in a power delivery system. PDN accurately models the VRM, capacitors, and system power and ground planes to determine the impedance of the power delivery system. PDN must deliver current at or near the target impedance at all frequencies from DC to the highest frequency of concern. Target impedance (Ztarget) is October Product Version 16.6

18 Use Model and Methodology calculated based on the bias voltage, tolerable ripple, and worst-case dynamic current. The target impedance Ztarget is defined as illustrated by the following formula: Using SigWave, a family of curves is created, which describes impedance as a function of frequency at each cell on the PCB. These curves are plotted along with the power delivery system s target impedance. Those areas on the board where the power delivery system impedance exceeds the target impedance can be corrected by placing decoupling capacitors whose resonant frequencies effectively lower the system impedance to within the allowable target impedance or by decreasing the inter-plane dielectric thickness for frequencies too high for decoupling capacitors to be effective. To define the target impedance curve at concerned frequency range, you can review and modify these parameters in the Target Impedance Editor. To access Target Impedance Editor: 1. Select a net from the list of power and ground nets. 2. Click the Target Impedance column. 3. Click Edit. October Product Version 16.6

19 Use Model and Methodology The Target Impedance Editor appears. Use this dialog to adjust the settings for a sloped target impedance curve at higher frequencies or to plot the target impedance curve in SigWave. For detailed information on Target Impedance Editor, see Target Impedance Editor on page 89. October Product Version 16.6

20 Use Model and Methodology Managing Decoupling Capacitors The Decoupling Capacitors Management UI helps you manage decoupling capacitors and their models. You can import and export part table, excel, and dcl files, assign part numbers, attach, delete, or change models, and place or un-place capacitors. October Product Version 16.6

21 Use Model and Methodology Note: Currently,.csv file is the only export mechanism. This file can be leveraged in other designs or used to update the existing design. The decoupling capacitor information contains a worksheet with corresponding parameters for analysis. The capacitors that are displayed have the CLASS defined as DISCRETE. The list of capacitors is further filtered by the net selected in the Net Filter drop-down. For detailed information on this form, see Decoupling Capacitor Management on page 63 Specifying Ports Information After you have specified the required values for the decoupling capacitors, you need to specify port information for devices in the design. Source(s) and noise (sink) current settings can both be virtual devices if they are not set here. October Product Version 16.6

22 Use Model and Methodology 1. Select the Components and Ports tab. The display you see in this tab will depend on whether or not you have any nets highlighted in the Power and Ground tab. Notice that the default setting for all component pins is Open. All discrete devices should have this port setting. For information on this form, see Components and Ports on page If required, set the Net filter to the desired DC net 3. Use the Filter or drag and select in the Components section to select components that will serve as the VRM (Source) location. October Product Version 16.6

23 Use Model and Methodology 4. Right-click the column headers and use the pop-up menu commands to simultaneously set values on multiple rows in the Ports section. 5. Choose Change All. 6. Select Source in the Port Type dialog and click OK. Note: In general, only the pins from IC or connector are set as sink or source. However, for some special case, you can also set the pins of a capacitor as the sink or source. Specifying Excitation You can optionally change the Excitation settings or the model used in the Excitation column. However, the default pq_vrm model is sufficient for most applications. If you want to change the VRM model, click the Browse button, and specify a new model in the resulting VRM Model dialog box. 1. In the Components section, select all the reference designators that correspond to IC noise sources for the selected net. October Product Version 16.6

24 Use Model and Methodology 2. Right-click on the Port Type column header and choose the Change All command from the pop-up menu. 3. Select Sink in the Port Type dialog and click OK. Notice that the default Excitation setting for each Sink port is 0 A. 4. In the Components section, select one or more of the components you just identified with a Sink Port Type that share the same current setting. 5. Right-click on the Excitation column header and choose the Change All Sink command from the pop-up menu. 6. Specify a new value for Sink current and click OK. Notice that the value is distributed across all of the pins for each device. October Product Version 16.6

25 Use Model and Methodology >>>some meaningful example to be added per CCMPR Note: Port Management for Model Extraction requires settings which are different from those required for the other three types of analysis. 7. Next click Return Path. The Return Path Configuration dialog box is displayed. October Product Version 16.6

26 Use Model and Methodology 8. Select a power net in the list on the left hand side to populate the right hand portion of the dialog box. PDN Analysis automatically determines the return path or ground net associated with each power net. Use this dialog box to verify or change the return path settings. 9. Close the dialog box. 10. Repeat steps 4 through 7 for each set of Sink components with a different current value. This completes the minimum required settings you need to specify to run PDN Analysis. You can also perform the following optional steps to perform a more accurate analysis: Defining Cross-Section Configuring Library Paths Assigning Models Defining Pins/Via Padstacks Defining Cross-Section Define design cross-section with the requisite thickness, conductivities, dielectric constant, and loss tangent. To do this, click Cross-Section. Use the Layout Cross Section dialog box to view and alter the characteristics of a selected board layer. You can view and edit the layout cross-section. Configuring Library Paths Configure library paths to include all the required models. Use the DML Library Management dialog box. You can access this dialog box without exiting the PDN Analysis dialog box. Click the Library Manage button on the main form to open the dialog box. Assigning Models Assign proper models to all the related components in the Signal Model Assignment dialog box, which you can access by clicking the Model Assignment button on the main form. Defining Pins/Via Padstacks It is also recommended that you define all pin or via padstacks with correct drill, thermal, or antipad parameters. October Product Version 16.6

27 Use Model and Methodology After performing the prerequisite tasks, you can proceed with the following analysis supported by the PDN Analysis Solution: Single Node Analysis Static IR Drop Analysis Model Extraction Analysis Power Integrity Analysis October Product Version 16.6

28 Use Model and Methodology October Product Version 16.6

29 3 Single Node Analysis October Product Version 16.6

30 Single Node Analysis Overview A single-node simulation is used to validate how well a capacitor selection maintains the target impedance over the specified frequency band. Single-node simulation entails subcircuit extraction from a single point on the board. Decoupling capacitors are considered, but their placement is not important for a single node analysis. In a single-node simulation, Allegro PDN wires all the decoupling capacitors in the board, and the Voltage Regulator Modules (VRM) in parallel with a 1 amp AC current source. The equivalent circuit is represented in the following figure. The results appear as impedance versus frequency graph showing a composite impedance profile as shown in the following figure. October Product Version 16.6

31 Single Node Analysis Voltage Regulator Modules Voltage Regulator Modules (VRM) in a board layout act as supply points from which power is delivered to the plane and regulated. A VRM converts one DC voltage to another DC voltage. The VRM uses a reference voltage and feedback loop to sense the voltage near the load, and adjusts the current accordingly. PDN models the behavior of the VRM as a four-element SPICE model. However, it also supports user-defined, multi-phase VRMs, as well as those provided by Cadence. The Cadence-provided VRM is a 4-element SPICE model named pq_vrm, and it is the default VRM model. You can add multiple VRMs to a plane-pair and vary their individual parameters for each selected plane-pair. VRMs appear in the board layout as a graphic on the analysis layer and disappear when you close the PDN Analysis dialog box. You can create or edit a VRM model using the VRM Model dialog box. To set the parameters of your VRMs, use the Cadence-Standard VRM Editor. October Product Version 16.6

32 Single Node Analysis Running a Single-Node Simulation You set up and run simulations from the main PDN Analysis GUI. To specify various options, parameters, and preferences for a Single Node simulation, perform the following steps: 1. In the Analysis section, select the Single Node option. 2. Select the required Power and Ground nets. 3. Select the Decoupling Capacitor Management tab. Select and specify the required settings on this page. 4. Select the Components and Portstab. Select and specify the required setting on this page. 5. Select the Parameters Setting tab. 6. Specify whether you want all the voids which have a size less than the specified size to be ignored during analysis. 7. Click the Analyze button at the bottom of the PDN Analysis UI. October Product Version 16.6

33 Single Node Analysis The Single Node analysis process begins. A progress dialog appears. Followed by the PDN Audit Result report as shown in the following figure. October Product Version 16.6

34 Single Node Analysis The results appear as impedance versus frequency graph as shown in the following figure. need a better waveform October Product Version 16.6

35 4 Static IR Drop Analysis October Product Version 16.6

36 Static IR Drop Analysis Overview Static IR-drop describes the DC voltage that develops across a conductor as a result of its electrical resistance. This voltage is proportional to the current that flows though the conductor (V=I*R) and results in a drop in voltage available at the load devices (Vload = Vsupply Vdrop). Allegro PCB PDN highlights potential problems in power delivery paths, providing visibility for both IR-drop and hot-spotting issues. The tools helps accurately design high-current power connections by quantifying the amount of voltage drop and temperature rise that are to be expected. The Static IRDrop analysis helps you assess the following: Voltage drop at any location of the selected nets - When maximum current is drawn, is the voltage at the load within specification? Temperature rise is the power path capable of delivering the maximum supply current without excessive temperature rise? The analysis reveals local pockets of high currentdensity, where a risk of excessive heating exists. The temperature analysis helps you ensure that a sufficient number of parallel vias have been used in power paths. The IR-Drop analysis functionality obtains voltage drop data by analyzing the nets to calculate the resistance of each meshed cell, via, and cline on one or more selected nets. With a simple mouse click you can then view accurate voltage drops across power planes; on the clines, vias, and pins of the simulated net. You can also view current on clines vias, and shapes as well as temperatures rises on clines and shapes. As an additional aid to setting up your design for analysis, you can select specific material types for padstack plating. Performing Static IR Drop Analysis The DC voltage (IR) drop is calculated based on the excitation and source settings for the component pins, the resistance model for meshed cells, clines, and the drill platting info for vias. The analysis results can be displayed as voltage drop, current, current density, or temperature rise. By default, nets are audited before the analysis is performed and a report is generated after the analysis completes. You can choose to skip these options. October Product Version 16.6

37 Static IR Drop Analysis To specify various options, parameters, and preferences for Static IR Drop analysis, perform the following steps: 1. Select the Static IRDrop options button on the main PDN Analysis GUI. 2. Select the required Power and Ground nets. 3. Specify the following values: Voltage THold: The maximum voltage drop over the entire net. Current THold: The maximum current flowing through the entire net. Density THold: The maximum current density flow through the entire net Note: The maximum temperature rise threshold value is set in the preference form and is common for all nets in the board. 4. Select the Decoupling Capacitor Management tab. Select and specify the required setting on this page. October Product Version 16.6

38 Static IR Drop Analysis 5. Select the Components and Ports tab. Select and specify the required setting on this page. 6. Select the Parameters Setting tab and specify the required parameter settings and preferences in the Preferences dialog box. Note: Ensure that you specify source and sink current information on a per-device or per-pin basis before you run the analysis on the selected power nets. 7. Right-click on the canvas and choose Quick Utilities Padstack. The Padstack Plating Parameters dialog box is displayed. 8. Specify plating thickness and material information. 9. Click OK. 10. In the Parameters Setting tab, click Preferences. 11. In the General tab, specify delta current, voltage ripple, voltage (DC) IR drop, current threshold, density threshold, and temperature rise threshold values. 12. Click OK. 13. Click the Analyze button at the bottom of the PDN Analysis UI. October Product Version 16.6

39 Static IR Drop Analysis The IR Drop analysis begins. A progress dialog appears. Followed by the PDN Analysis Result report as shown in the following figure. You can review the result of the analysis and the associated voltages, currents, or temperature rises in the Options tab in the Options window panes in the Allegro canvas. October Product Version 16.6

40 Static IR Drop Analysis Notice that the Options pane appears slightly different from when the Mesh was generated. The default layer to Review is Top. This layer may or may not have any shapes on it for the DC Nets that are being analyzed. Selecting a point on a net that was analyzed will display the value at that location in the Options pane. October Product Version 16.6

41 Static IR Drop Analysis Use the pop-up menu on the canvas to display analysis results in the Options tab. select the other Display options for IRDrop analysis, such as Display Mesh, Display Current, Display Density, and Display TempRise Use the Set reference command to pick a reference point in the design which is graphically displayed on the canvas. October Product Version 16.6

42 Static IR Drop Analysis Subsequent probe points will be displayed in the Options pane with the actual drop value at that point and the relative value to the reference point. 14. In the Options pane, select the Color Legend option button. 15. Click the Custom button. October Product Version 16.6

43 Static IR Drop Analysis 16. Choose Voltage from the Format drop-down list. Tip You can also access the Color legend dialog from within the Preferences dialog in the Simulation tab and from the right-click shortcut menu on the canvas by choosing Quick Utilities Color Legend. 17. Click OK. 18. Right-click on the canvas and choose Done to return to the main form. October Product Version 16.6

44 Static IR Drop Analysis October Product Version 16.6

45 5 Model Extraction Analysis October Product Version 16.6

46 Model Extraction Analysis Model Extraction In the Model Extraction flow, PDN extracts the S-param model for the selected power/ground nets. This model can be used for further SSN analysis, and the PDN co-design analysis with other boards. You can specify various control parameters for the model extraction flow in the Parameters Setting UI. Running Model Extraction Analysis You set up and run simulations from the main PDN Analysis GUI. To start a Single Node simulation do the following steps: 1. In the Analysis section, select the Model Extraction option. 2. Select the required Power and Ground. 3. For the Model Extraction analysis, you only need net name and voltage values on the main form. October Product Version 16.6

47 Model Extraction Analysis 4. Select the Decoupling Capacitor Management tab. Select and specify the required setting on this page. 5. Select the Components and Ports tab. 6. Add a port: a. Click Add Port. b. Select a power net or a ground net name in the positive terminal of the port as a Positive Net. c. Browse to select a positive terminal of the port or pick from the canvas. d. Select a power net or a ground net name in the negative terminal of the port as a Negative Net. e. Browse to select a negative terminal of the port or pick from the canvas. Note: See Port Management for Model Extraction for more information. 7. Select the Parameters Setting tab and specify the required parameter settings. 8. Specify the Model Extraction parameters. 9. Click the Extract button at the bottom of the PDN Analysis UI to run model extraction and generate S parameters. The Power Network Impedance analysis begins. A progress dialog appears and the analysis report is generated. October Product Version 16.6

48 Model Extraction Analysis October Product Version 16.6

49 6 Power Integrity Analysis October Product Version 16.6

50 Power Integrity Analysis Overview The Power Integrity analysis helps you perform layer stack-up and floor plan optimization for IC components, the power network verification analysis in the frequency domain for the entire selected power and ground network. This analysis is intended for performing AC analysis for pre-routing and post-routing board. Note: The PDN Analysis solution supports routed power nets with reference planes. The design without a reference plane are not supported by the PDN solution. Power Integrity Analysis The Power Integrity analysis also helps you perform layer stack-up and floor plan optimization for IC components. For the excitation source and VRM model information that you specify, frequency-dependent impedance value is calculated using shapes, pins, and vias on the selected DC nets. Based on the result of this analysis, you can select, place, or remove decoupling capacitor models. You can also modify the layer stack-up and utilize shape edit functions. All the elements, such as traces, shapes, pins, fan-outs, clines, and vias connected to the power ground planes in the design are included in the power network verification analysis. These are combined with the excitation sources set for the IC components and VRM models for the power supply. You can use the analysis results to refine decoupling capacitors in the design. To specify various options, parameters, and preferences for Power Integrity analysis, perform the following steps: 1. Select the Power Integrity options button on the main PDN Analysis GUI. 2. Select the required DC nets in the Power and Ground tab. 3. Specify the following values: Ripple: The maximum voltage ripple tolerance allowed over the entire net Max Delta Current: The maximum dynamic current flowing through the entire net. Target Impedance: The power delivery target impedance for the net. Note: Determine the target impedance in the Target Impedance Editor. 4. Configure libraries and decoupling capacitors in the Decoupling Capacitor Management. 5. Define source and sink ports in the Components and Ports tab. October Product Version 16.6

51 Power Integrity Analysis 6. Select the Parameters Setting tab and specify the required parameter settings. 7. If you want to ignore existing routing in the board, select Ignore routed traces in the design option. 8. Click Preferences to open the Preferences dialog box. 9. Click the Field Solver tab.\ 10. Select the Ignore all shapes/clines in the specific layers option and click the Specify Layers button. This will launch the Layer Management dialog. Use this dialog to improve simulation time. You can ignore layers which have small shapes on them without significantly impacting accuracy. 11. If required, choose a layer to ignore and click OK. 12. Make any other desired changes to the simulation preferences and click OK in the Preferences dialog. October Product Version 16.6

52 Power Integrity Analysis 13. Right-click on the canvas and choose Virtual VRM Place. If you have multiple VRMs, choose the Virtual VRM Manage command. It provides the Virtual VRM Management dialog to list, edit, and delete VRMs. From this dialog, you can launch the Cadence-Standard VRM Editor. October Product Version 16.6

53 Power Integrity Analysis The Options tab shows the options necessary to select the model for the VRM, the nets it attaches to, and some placement options. 14. Click on the appropriate location on the canvas and place the Virtual VRM. 15. Right-click and choose Done. 16. Right-click on the canvas and choose Virtual Noise Place. October Product Version 16.6

54 Power Integrity Analysis The Options tab contains all the necessary settings. 17. Make the necessary adjustments to the Net assignments and Sink current value in the Options pane. 18. Click in the canvas to place the virtual noise source and repeat, adjusting the Sink value in the Options pane as necessary until all your Virtual Noise sources are placed. 19. Right-click and choose Done. 20. Click the Analyze button at the bottom of the PDN Analysis UI. The Power Network Impedance analysis begins. A progress dialog appears. October Product Version 16.6

55 Power Integrity Analysis Followed by the PDN Analysis Result report as shown in the following figure: October Product Version 16.6

56 Power Integrity Analysis Sigwave shows the target impedance curve for the analysis. 21. Close SigWave. Tip You can recall SigWave any time by right-clicking on the canvas and choosing Cross Probe from the pop-up menu. As with other types of analysis, you can use the Review drop-down list in the Options pane to see the desired layer in the design and selections on a DC Net will display Impedance and Frequency values. You can also access the Color Legend to make changes. October Product Version 16.6

57 7 PDN Analysis GUI Reference This chapter covers: PDN Analysis Power and Ground Decoupling Capacitor Management Components and Ports Parameters Setting Target Impedance Editor Power/Ground Nets Selection Decoupling Capacitor Library Management Decoupling Capacitor Model Editor Intrinsic Inductance (ESL) Estimator Create/Browse Decoupling Capacitor Port Group Configuration Return Path Configuration Return ground pin selection Virtual Excitation Browser Virtual Excitation Management VRM Model Cadence-Standard VRM Editor VRM Input Inductance Calculation Preferences October Product Version 16.6

58 PDN Analysis GUI Reference General Field Solver Color Legend Layer Management Padstack Plating Parameters Signal Model Histogram Virtual VRM Management Virtual VRM Virtual Noise Management Virtual Noise Virtual Probe Management Virtual Probe Editing in Context October Product Version 16.6

59 PDN Analysis GUI Reference PDN Analysis Use this form to perform Mesh, Static IR Drop, PI Plane, and PI Network analysis. Power and Ground In this section of the main PDN Analysis form, you select the DC nets to be analyzed and define the net information, such as voltage, ripple, max delta current, target impedance, maximum DC IRDrop, and current density threshold. October Product Version 16.6

60 PDN Analysis GUI Reference Initially, you need to configure the power and ground net information for analysis. Field Analysis Select DC Nets Net Name Voltage Ripple Max. Delta Current Target Impedance Identify DC Nets Cross-Section Manage Library Description Provides the following four options to facilitate four types of analysis for the selected power and ground nets: Static IRDrop Single Node Model Extraction Power Integrity Displays the Power/Ground Nets Selection dialog to select the power and ground nets to be analyzed. Lists the net name of the DC nets. Lists the voltage of the selected power net. The maximum voltage drop or spike that the design can tolerate (expressed as a percentage of voltage between 1 and 5%). The maximum amount of current that the design can tolerate in a three-phase circuit. You can set the value in the field or in the Target Impedance Editor. Lists the target impedance computed based on the supply voltage, tolerable ripple, and the worst-case dynamic current you specify. Click Edit to review and modify target impedance parameters in the Target Impedance Editor. Opens the Identify DC Nets dialog box, where you can assign correct voltage to power and ground nets in the design. Opens the Layout Cross Section dialog box to view and alter the characteristics of a selected board layer. You can define design cross-section with the requisite thickness, conductivities, dielectric constant, and loss tangent. Opens the DML Library Management dialog box where you can configure library paths to include all the required models. October Product Version 16.6

61 PDN Analysis GUI Reference Field Hide Refresh Exit Description Hides the main PDN Analysis form. All the PDN applications continue to be accessible from the context-sensitive menus available on right-click action on the canvas. To restore the main form to view, right-click in the design canvas and select Show Form from the pop-up menu. Refreshes the data if you have made any changes, such as adding, deleting, or moving on layer stack, probes, and so on. Closes the PDN Analysis form and exits the application. To restart the PDN Analysis, choose Analyze PDN Analysis. October Product Version 16.6

62 PDN Analysis GUI Reference Field Description Advanced PDN Import: Import PDN parameters stored in a.csv file. PDN Export: Export one or all of the following parameters to a.csv file: October Product Version 16.6

63 PDN Analysis GUI Reference Decoupling Capacitor Management The main window for Decoupling Capacitors Management solution is divided into three groups: Device Capacitor Model In this form, when you select a device in the Device group, the capacitors that are connected with the selected DC net (in Net filter) are highlighted in the Capacitor group, and the models associated with the capacitors are listed in the Model group. October Product Version 16.6

64 PDN Analysis GUI Reference Device All the decoupling capacitors on the board are automatically listed in Device section. If there is no part number associated with a decoupling capacitor, it is auto-assigned for each device. When you select a row of the worksheet, one device is selected and all the capacitor instances of this device are listed in the Capacitor group. Field Part No. Filter JEDEC Filter Value Filter Import/Export ESR Plot Part No. JEDEC Default Signal Model Description Displays the device details for a specific part or part(s) matching the filtering criteria. Use this filter to display a shortened list of part numbers. Displays the device details based on the specified JEDEC_TYPE. Displays the device details based on the specified value. Imports the devices from part tables (.ptf),.csv, or.dcl library to the current design or export the devices in the current design to a.csv file. Launches the Device Import dialog. Show the log-esr/log-frequency graph. This button launches the Signal Model Histogram dialog. The graph in this dialog displays the log-esr/log-frequency for models of all the devices listed in the Device group list. The part number of the decoupling capacitor. The JEDEC_TYPE of the decoupling capacitor. The default signal model will be automatically assigned to any newly placed decoupling capacitors. October Product Version 16.6

65 PDN Analysis GUI Reference Field Value Tol Price Vendor Material MaxVoltage Description The capacitance value of the capacitor. The tolerance level of the capacitor. The cost price of the capacitor. The vendor information about the part. The materials available to plate the padstack The maximum amount of voltage that the capacitor can store. In the worksheet, when you right-click a part number, a context pop-up menu appears. As the decoupling capacitor s symbol attaches to your cursor, the following operations (a second right-click) are available. Pop-up Menu Options Add Device Description Launches the Device Editor to add a new device to the design. Edit Device Edits the selected device. Opens the Device Editor where you can update any properties, except for the part number and JEDEC. Delete Device Deletes a device from the design. All the capacitor instances of this device are deleted from design. October Product Version 16.6

66 PDN Analysis GUI Reference Pop-up Menu Options Assign Default Model Description Assigns a default model to the selected device. When you assign a model to the selected device, we will be informed whether we want to assign this model to all the capacitor instances of this device or not. October Product Version 16.6

67 PDN Analysis GUI Reference Pop-up Menu Options Place Capacitors Description Places decoupling capacitors for the selected device and its corresponding parameters. When you select a capacitor, you can place it as shown in the following image: If you change the settings here, the changes apply to each subsequent capacitor that you place in the context of the given session. The default settings re-apply at the beginning of the next placement session. When placing the decoupling capacitors into the design, all the spacing and position conflicts are ignored. The decoupling capacitor package is placed on the top or bottom layer. Note: If the decoupling capacitor package has fan-out with vias, the package will be connected to its power and ground net automatically. They will, however, be flagged as DRC updates. October Product Version 16.6

68 PDN Analysis GUI Reference Pop-up Menu Options Sort Ascending/Sort Descending Description Sorts the device list in the ascending or descending order. Device Editor Use this dialog to add or modify a device. When you select the Add Device command, the Device Editor opens with an automatically-generated part number. Clicking the Assign button on this form invokes the Create/Browse Decoupling Capacitor dialog box, where you can create a new decap model or browse an existing model via SI Model Browser or directly specify an existing model name to assign. A new model with default parameters is created and stored in the default dml model file, devices.dml, if the input model does not exist. October Product Version 16.6

69 PDN Analysis GUI Reference Capacitor The model information of all the instances listed is displayed in the model information grid. Fields Net Filter Name Filter Model Name Capacitance ESL ESR Description Filters decoupling capacitors for a specific power net matching the filtering criteria. Filters instances of decoupling capacitors with names matching the filtering criteria. The dml model (ESpice or S-Parameter) used for the decoupling capacitor. The capacitance value of the decoupling capacitor as specified in the Param section of the signal model. The equivalent series inductance value of the decoupling capacitor as specified in the Param section of the signal model. The equivalent series resistance value of the decoupling capacitor as specified in the Param section of the signal model. Frequency The resonant frequency of the model which is calculated based on the capacitance, intrinsic inductance (ESL), and mounted inductance. October Product Version 16.6

70 PDN Analysis GUI Reference Fields More Description Click to perform more operations on the selected capacitors. Assign Model: Assigns a model to the selected capacitors or removes the model property from the selected capacitors. Graph Response: Generates a capacitor response waveform for the selected capacitors. Inactivate: Inactivates the selected capacitors. The inactive capacitors are ignored for analysis and simulation. Such capacitors are marked Inactive. PDN uses this function to perform the what-if analysis. For capacitors marked as Inactive, the assigned decoupling models are also ignored during analysis. Activate: Activates the inactive components. The active components are considered for analysis and simulation. Delete: Deletes the selected capacitor instances from design. October Product Version 16.6

71 PDN Analysis GUI Reference Model When you select a device, the model information of all the capacitors of the selected device are displayed in the Model information worksheet. When you select a decoupling capacitor, only the selected capacitor's model is displayed in this worksheet Field Net Filter Model Name Capacitance ESR ESL Description Use net filter to display and configure decoupling capacitors for a specific power net. The dml model (ESpice or S-Parameter) used for the decoupling capacitor. The capacitance value of the decoupling capacitor as specified in the Param section of the signal model. The equivalent series resistance value of the decoupling capacitor as specified in the Param section of the signal model. The equivalent series inductance value of the decoupling capacitor as specified in the Param section of the signal model. Frequency The computed resonant frequency (in Hz) for ESpice and S- Parameter model. Placed Suggested This field represents the recommended number of capacitors required to be placed at a location to meet the target impedance. This field is applicable for only single node analysis flow. The formula used here is ESR (of the capacitor) / Target Impedance. The formula results in a float number, which is truncated and 1 is added to it to generate the value of the suggested number of capacitors to be placed. For example, 1.1 will get 2, 2.9 will get 3. Based on the analysis conditions that you specified (ripple tolerance and max delta current), PDN suggests how many decoupling capacitors of each type are required to maintain the target impedance. If you change any of the analysis conditions, the target impedance will change; in turn, the number of capacitors suggested to be placed will be updated accordingly. October Product Version 16.6

72 PDN Analysis GUI Reference Device Import You can also import devices from existing Allegro part table files (.ptf),.dcl files or.csv files and display the details in the Device information grid. Tip You can add a capacitor back from the power_integrity.dml library in the installation hierarchy if it does not exist in the design. October Product Version 16.6

73 PDN Analysis GUI Reference The device information grid displays the device information from the imported file after the part table or.csv file is loaded. Field PartNo Filter JEDEC Filter Value Filter Load Description Filters device information based on the specified part number or the pattern. Filters device information based on the specified JEDEC type or the pattern. Filters device information based on the specified value of a decoupling capacitor or the pattern. Launches the Part table File Selection dialog where you select the.ptf,.csv, or.dcl files to load. When a part table file is loaded, the device information in the file is listed in the Device information grid. You can select a device from this list by clicking the check box to its left and add the device to the design. October Product Version 16.6

74 PDN Analysis GUI Reference Field View Map Description Shows the mapping file. Default content of this file is displayed here: As the format of part table files may differ, using the mapping helps in identifying the actual property name in different part table files. For example, for the following mapping: PartNo=part_number, the property name in the part table file is part_number. In the equation, the left side is the column name of the table in the Device Import form, and the right side is the column name of the table in the.ptf,.csv, or.tcl file. The default mapping file is located at: <install_dir>/share/pcb/signal/power_integrity. You can copy this file to the working directory and modify it with the actual property names in the.ptf files. October Product Version 16.6

75 PDN Analysis GUI Reference Components and Ports You need to configure the package and on-die information for IC component, including the current profile, series capacitance and resistance, or sub-circuit, before you perform extraction and analysis. This information is typically provided by the IC manufacturer or the IC simulation tool and the package power model extracted by package tools. Components Section In the Component section, you select the IC component to display corresponding pin/port information on the right pane. By default, all the IO/IC components placed on the board are displayed in the component list. As you select a component, the related port information is displayed in the Ports grid on the right. Field Filter Select All Edit Profile Net filter Pin Group Return Path Description Lets you display component names based on the specified pattern. Selects all the components. Helps you define additional package and/or die profile for codesign flow for chip-package-board and board-board. Lets you display power/ground net names based on the specified filtering pattern. Assigns pin group information for selected components. See Port Group Configuration for more information. Opens the Return Path Configuration dialog box where you specify the return path for each power pin in selected power nets. October Product Version 16.6

76 PDN Analysis GUI Reference Ports Section In the Ports section, you assign pin group information, such as port type, excitation, and group for the pins connected to the selected power net. You can right-click column headers to control sorting and to make changes or reset all items simultaneously. Field Pin Name Port Type Excitation Group Description Lists all the pins in the selected power net. Lists the port types for each pin. Port type can be Open, Sink, and Source. The default value is Open. If you have not selected a current profile, all port types default to Sink for die components and can be edited. If a BGA is the selected component, all port types default to Source and cannot be edited. If a current profile is selected, it is listed as the excitation source for all pins and cannot be edited. Note: If the sink excitation current of sink pins is zero, they act as Open type. Lists the excitation source or a constant current value for each pin. If your component selection is a die and you have selected a current profile, the excitation source for all pins defaults to the profile and cannot be edited. If you do not select a current profile and you select a port type of Sink for any pin, the Excitation field becomes active and lets you select a Gaussian or pulse excitation source from the drop-down or lets you enter a constant current value. If your component selection is a BGA, no excitation source or current profile is selectable. Lets you group the sink and source pins on your packages and dies as a multi-port net to improve extraction and simulation performance. You group sink and source pins in the Port Group dialog box. October Product Version 16.6

77 PDN Analysis GUI Reference Port Management for Model Extraction Port management for Model Extraction requires settings which are different from those required for the other three types of analysis. The following columns in the grid are inserted for model extraction flow: Field Index Description The port index used in model extraction. This is also the port index in the generated S-param model. Positive Net The net name in the positive terminal of the port. It can either be power net or a ground net. October Product Version 16.6

78 PDN Analysis GUI Reference Field Positive Term Description The positive terminal of the port. It can either be the pin name or the net group name. You can also choose a terminal from the Allegro canvas directly from the drop-down list. Negative Net The net name in the negative terminal of the port. It can either be power net or a ground net. Negative Term The negative terminal of the port. It can either be the pin name or the net group name. You can also choose a terminal from the Allegro canvas directly from the drop-down list. Active Indicates whether this port is active or not. If it is inactive, PDN ignores it while performing model extraction. Add Port Adds a new port in the grid. Del Port Deletes the selected port from the grid. Delete ALL Deletes all the ports in the list. October Product Version 16.6

79 PDN Analysis GUI Reference Parameters Setting The parameters on this tab are used to configure various meshing and simulation parameters for various flows The contents of this tab are dynamically populated based on the flow you select on the main form. Frequency Domain The fields and values in the Frequency Domain are valid for all analysis flows except for Static IRDrop. This section is disabled for the Static IRDrop flow: Field Lower Frequency Upper Frequency Sweep Scale Sweep Num Description The lower frequency range of the simulation. The upper frequency range of the simulation. Select a frequency sweeping type from the pulldown menu for frequency point distribution. You can select from Linear and Log. The default value is Linear. Specify the number of frequency points required to run the analysis/ simulation. October Product Version 16.6

80 PDN Analysis GUI Reference Shape Mesh Information Rectangle The Shape Mesh Information Rectangle group is valid for all analysis flows except for the Single Node analysis. The X Size and Y Size value for Fine, Regular, and Coarse fields are calculated and displayed automatically with the upper frequency value in AC analysis. Field Mesh Information ---- Rectangle Description You can choose from the following mesh types: Fine Regular Coarse Custom The formula for calculating the mesh size is: The X and Y sizes of the mesh for fine, regular, and coarse are pre-defined. X Size: This field is enabled when you select the Custom button. You can specify an X value for the design's shape mesh cell size. Y Size: This field is enabled when you select the Custom button. You can specify a Y value for the design's shape mesh cell size. October Product Version 16.6

81 PDN Analysis GUI Reference Model Extraction Field Model Name Description Specify the model name for the generated dml file. By default, it takes the names of the selected power and ground nets. Model Type Specify the model type of the generated model embedded in the.dml file. It can be in Y-Param, Z-Param, or S-Param. The default value is S-Param. File Type By default, DML format is created. If this option is selected, the Touchstone format is created additionally. Reference Impedance Specify the reference impedance value for the generated S- param model. The default value is 50 ohm. October Product Version 16.6

82 PDN Analysis GUI Reference Additional Settings Field Print waveforms for pins on all components Description Prints waveforms for pins on all components instead of pins of source/sink or virtual probes only. This field is used in the Power integrity and Single Node Analysis flows only to print and export waveforms for all the pins in the selected power and ground nets. By default, PDN only prints waveforms for source/sink and virtual probes pins on the IC components. Ignore routed traces in the design This field is used in the Power integrity and Model Extraction flows only to ignore the routed traces in the design for prerouting analysis. If this option is selected, all the existing routing in the board is ignored, so that you can perform the prerouting analysis if you have a fully or partially routed board. Ignore shape/voids less than Ignores all the voids which have a size less than the specified size. October Product Version 16.6

83 PDN Analysis GUI Reference Field Print reports for pins on all components Description Prints reports for pins on all components instead of instead of pins of source/sink or virtual probes only. This field is used in the Static IRDrop flow only to report analysis result for all pins in the selected power and ground nets. By default, PDN only prints waveforms for source/sink and virtual probes pins on the IC components. Generate via IRDrop report Generates and IRDrop report for all vias. This field is used in the Static IRDrop flow only. Skip audit before analysis Select this option if you do not want an audit to be performed on the design before running the analysis. Skip report after analysis Session Name Preferences Select this option if you do not want a report to be created on the design after running the analysis. Specify the session name which is used to organize various analysis results of PDN analysis done in a specific session. The intermediate and final analysis files are named and stored with the session name. Launches the Preferences dialog box where you can edit various default values and specify advanced field solver options for analysis. Preferences General Field Solver Color Legend October Product Version 16.6

84 PDN Analysis GUI Reference General Field Delta current Voltage ripple Voltage (DC) IR drop Current threshold Density threshold Temp. rise threshold Corner frequency Slope (db/decade) Multiplier Description The maximum amount of current that the power net will potentially suffer in a worst-case scenario. The maximum voltage drop or spike that the design can tolerate, expressed as a percentage of voltage. The potential drop in voltage. The threshold value of current for the selected net. The threshold value of current density for the selected net. Maximum allowed temperature rise for the net you are analyzing. If high current or current density on any signal traces or shapes cause a violation of the threshold setting, a warning is generated in the result report. The default value is 5 degrees Celsius. The frequency up to which the target impedance is constant. The ramp-up of target impedance after the corner frequency A constant value that helps you define the design margin. A multiplier value of 2 calculates the target impedance using the following equation: Note: If you want to specify a more coarse target impedance, you can set the value of multiplier to a higher value. October Product Version 16.6

85 PDN Analysis GUI Reference Field Mounted Inductance Description PCB PDN can estimate the mounted inductance of a surface mounted capacitor based on the parameters that you supply. You specify a designated powerplane-pair, a package, and the side of the board on which to mount the capacitor. Tip Effective radius Mounted inductance is the external loop inductance from the plane-pair including the 3-D path effects of etch length, via size, and loop area. When you place a decoupling capacitor on the canvas, an enveloping circle represents its effective radius. This radius is based on a fraction of the resonant frequency's wavelength for the decoupling capacitor, which you set in the control panel. This lets you quickly determine how close to place high frequency capacitors to noise sources. Field Solver Field Shape Mesh Information Rectangle Description Ignore - Mesh will not include void in shapes for pins/ vias. Voids are the anti-pads from the pin/vias objects. When you choose this option, the regular pads of the pin/vias objects are also ignored. Ignore all shapes/voids less than meshing size: Ignores all the voids which have a size less than the specified size. October Product Version 16.6

86 PDN Analysis GUI Reference Field Description Scope - Defines the scope of the nets to be considered for mesh analysis. You can choose between Power Net and Whole Design. The ability to narrow the analysis scope to selected power nets only improves the performance of the analysis. If you choose the Power Net scope, the selected power nets are enclosed within a rectangle, which is usually smaller than the ground plane. Mesh analysis is performed on all the power and ground nets selected in the Power and Ground tab of the PDN Analysis GUI within this rectangular area. With the Whole Design scope, all the power and ground nets selected in the Power and Ground tab of the PDN Analysis GUI are enclosed in a rectangle and the mesh analysis is performed on all the power and ground nets. Extend - The distance to which the surrounding rectangle extends away from the power net. If you choose to extend to 0 cell size, the surrounding rectangle touches the power nets. if you choose the extend to 1 cell size, the surrounding rectangular will extend 1 cell size away from the edge of the power nets. October Product Version 16.6

87 PDN Analysis GUI Reference Field Field Solver Option Color Legend Custom Description Use debye model for causality enforcement on dielectric material: Choose this option to ensure that the generated model is causal and can be used in time-domain simulation. Ignore all shapes/clines in the specific layers: Ignores shapes in the selected layers for simulation. Select the Ignore Layer button to activate the Specific Layers button. Clicking this button opens the Layer Management dialog box where you select the layers, which you want to ignore for a simulation. When you ignore a layer, all the shapes and paths in the selected layer are ignored in the simulation. Ignoring a layer helps improve analysis performance without losing accuracy. Ambient Temperature: Specify the ambient temperature in degrees Celsius. Ambient temperature is considered in IR- Drop analysis to calculate resistance. Surface Roughness: Specify the roughness parameters for the solver. Opens the Color Legend dialog box. Color Legend Field Format Description Choose from: Impedance Voltage Current Density TempRise October Product Version 16.6

88 PDN Analysis GUI Reference Field Method Description Choose from: Linear Log Sqrt Sqrt4 Exact October Product Version 16.6

89 PDN Analysis GUI Reference Target Impedance Editor Target impedance is a key parameter in a power deliver system. The power deliver network must deliver current at or near the target impedance at all frequencies from DC to the highest frequency of concern. The target impedance, Z target, is defined as illustrated by the following equation: To define the target impedance curve at the concerned frequency range, you can review and modify the following parameters in the Target Impedance Editor. Field Lower Frequency Upper Frequency Power Net Voltage Ripple Tolerance Max Delta Current Corner Frequency Slope (db/decade) Multiplier Description The lower frequency range for the analysis. The upper frequency range for the analysis. The power net you selected for analysis. The supplied voltage from the selected power net. The maximum voltage drop or spike noise that the design can tolerate. This value is expressed as a percentage of voltage. The Max Delta Current value can be obtained from data sheet or from Power_consumption/Voltage. The frequency up to which the target impedance is constant. The ramp-up of target impedance after the corner frequency A constant value that helps you define the design margin. A multiplier value of 2 calculates the target impedance using the following equation: Note: If you want to specify a more coarse target impedance, you can set the value of multiplier to a higher value. October Product Version 16.6

90 PDN Analysis GUI Reference Field Target Impedance Plot Description The target impedance computed based on the supply voltage, tolerable ripple, and the worst-case dynamic current. Generates a plot of the target impedance profile and display it in Sigwave tool. October Product Version 16.6

91 PDN Analysis GUI Reference Power/Ground Nets Selection When you place a decoupling capacitor into a design, you need to specify to which ground net the pin of decoupling capacitors connects. Else, the direct connection to the closest ground net pin is used for simulation. Therefore, it is suggested to include at least one ground net into analysis list. In the Power/Ground Nets Selection dialog box, you can manually review and modify the power and ground nets list. All the available power and ground nets appear in the Available power/ground nets list. When you move the nets to the Selected power/ground nets list, the selected item is moved to the grid on the main form. Field Available power/ground nets Selected power/ground nets Identify DC Nets Description Lists all the power/ground nets in the design. Lists the power/ground nets in the design made available for the analysis. Opens the Identify DC Nets dialog box, where you can assign correct voltage to power and ground nets in the design. October Product Version 16.6

92 PDN Analysis GUI Reference Decoupling Capacitor Library Management Use this dialog box to add capacitors to the design from external libraries or to enable/disable capacitors already in the Board file. Selecting external capacitors from the DCL libraries in the tree structure helps to ensure that the capacitors you place have all the necessary information. This dialog box displays the decoupling capacitors already on the board (inside the Board directory in the tree structure) and the external Decoupling Capacitor Libraries available for placement. For more information on libraries, see Developing Model Libraries in the Allegro PCB SI User Guide. PCB PDN requires access to both ceramic and bulk decoupling capacitor models before analyzing for power delivery problems. A decoupling capacitor is represented as a device. The device file includes the package model that describes the capacitor s layout and pin escapes, the capacitor s part number, a signal model that specifies the capacitor s value as well as its intrinsic inductance (ESL), and its equivalent series resistance (ESR) and frequency. Capacitor families are categorized by operating characteristics, such as capacitance value, physical size and durability, mounting type, and temperature and humidity factors. The.dcl file specifies capacitor family grouping. ESR, ESL, and resonant frequency are optional properties that can be accessed or calculated from the DML model referenced by the signal model property. Capacitors in the board file are listed under the Board folder in this dialog. To enable the capacitors in the board file, you first need to assign models for the capacitors. If you have assigned models for capacitors in the logic design tool, you can browse to the.cpm file to load the capacitor models to Allegro folder in this dialog. Field Power net Description Lists all the power nets in the design. October Product Version 16.6

93 PDN Analysis GUI Reference Field Select decoupling capacitor libraries Description Displays the Capacitor library tree. Capacitors with a check mark are considered in analysis. You can click on a capacitor and then right-click to invoke the context pop-up menu from which you can choose to graph the impedance versus frequency curves of a single capacitor or a group of capacitors. You can also edit a capacitor that represents your specific design requirements. Tip Rather than working with capacitors one-by-one, you can right-click on a folder to quickly enable (select) or disable (deselect) all capacitors in the library tree. You can also use this technique to create capacitors. Details of selected decoupling capacitor The frequency versus impedance curves depict the capacitive effects (upward slope of the curve) and the inductive effects (downward slope of the curve). The knee of the curve depicts the equivalent series resistance, or the resonant frequency of the capacitor. Effective capacitance, effective ESR, mounted inductance, and frequency. October Product Version 16.6

94 PDN Analysis GUI Reference Decoupling Capacitor Model Editor You use the Decoupling Capacitor Editor to view or modify the characteristics of the selected decoupling capacitor. Any changes that you make in the Decoupling Capacitor Editor are saved to the component model file that is associated with the selected capacitor. All capacitors that reference the device model, in turn, are refreshed with the new values. Important If the device model file is write-protected, your edits are saved to the devices.dml file in the current working directory. Field Model Name Text Edit Capacitance Description Name of the device file that is associated with the capacitor. Opens the selected decoupling capacitor model for editing in an ASCII editor. Default nominal capacitance value as specified in the signal model. You can leave this field blank or enter an estimated value if the capacitance for some complex decoupling capacitor model is not available, such as n-terminal or S- parameter model. Intrinsic Inductance (ESL) Estimated Intrinsic inductance of a surface mounted capacitor computed from its height parameters. Intrinsic inductance computations do not account for the capacitor s mounting characteristics. Estimate Mounted Inductance Intrinsic Resistance (ESR) Opens Intrinsic Inductance (ESL) Estimator, which helps you calculate ESL based on the supplied capacitor thickness. Mounted inductance of a surface mounted capacitor computed from its fanout and the distance of power and ground pin to power and ground planes. This is an estimated value to calculate resonant frequency. Signal model s impedance value at resonance. October Product Version 16.6

95 PDN Analysis GUI Reference Field Resonant Frequency Plot Graph Pin count Description Computed resonant frequency based on capacitance and intrinsic inductance value for the decoupling capacitor model. The capacitor s resonant frequency is the point of least impedance and, therefore, the point at which the capacitor is most effective at replenishing current to the board. Below the resonant frequency, the capacitor s impedance is predominantly capacitive; above the resonant frequency, the capacitor s impedance is predominantly inductive. Generates a single capacitor response wave and displays it in Sigwave. After plotting the graph, ESR and resonant frequency value is calculated and displayed in the GUI. Displays the pin count of the selected device. Intrinsic Inductance (ESL) Estimator In this dialog box you can experiment with different capacitor thickness settings. The intrinsic inductance estimation does not consider the capacitor s mounting characteristics. Field Capacitor thickness Description The intrinsic inductance of a surface mounted capacitor is estimated based on the thickness (height) value that you supply. Intrinsic inductance (ESL) The computed Estimated Intrinsic inductance. October Product Version 16.6

96 PDN Analysis GUI Reference Create/Browse Decoupling Capacitor You can create a new decoupling capacitor model or browse an existing model using SI Model Browser and add it into the worksheet on the main form Field Model name Browse Edit Model Description The decoupling capacitor model name to be added into worksheet. If you specify a new name in the Model name field, a new decoupling capacitor model with default parameters is created and stored in the default dml model file, devices.dml. Opens SI Model Browser to select an existing model. Opens Model Editor. You can change the operating parameters of new and existing models in Model Editor. October Product Version 16.6

97 PDN Analysis GUI Reference Signal Model Histogram The models listed in the Device list of the Decoupling Capacitors tab of the main PDN analysis GUI are considered for constructing this graph. If you change the models on an instance of a decoupling capacitor, the model is not considered in the graph. This graph is used to display the log-esr/log-frequency for the device (model) selection and not for real placement in the board. October Product Version 16.6

98 PDN Analysis GUI Reference Port Group Configuration In order to improve the extraction and simulation performance, you need to group the sink pins and source pins on PCB and IC component as a Multi-port net. Use the Port Group dialog box to group source pins and sink pins in a multiport net. Port grouping gives you the capability of setting up a partition-based extraction by enclosing ports of source and sink pins in a specified portion of your design. This eliminates the limitation of having to extract the entire design with each pin identified. Note: For purposes of simulation, you must designate at least one source pin and one sink pin to each net. Other than that requirement, you can designate any pin (port) as either source or sink. You can also include source and sink pins in a single group. In every instance, Open pins are ignored during simulation Field Selection area Component Net Name Port group assignment Description Displays a list of components in your design. Selection of a component (either from the list in the dialog box or from the design on the canvas) displays information associated with all the pins in that net. All pins belong to selected components in this list are considered to be grouped. Displays a list of nets in your design. Selection of a net (either from the list in the dialog box or from the design on the canvas) displays information associated with all the pins in that net. All pins connected to selected nets in this list are considered to be grouped. This section of the dialog box lets you select pins for grouping and assigning. You can also select individual pins directly from the design canvas. A selection that you make from the canvas has the effect of moving that pin name from the list box it is presently in, to the other list box. Selecting the pin again moves the pin name back to the other list. All pins belong to selected components and connected to selected nets and those names match the filter pattern will be listed on the left. All the selected pins are moved from the list of available pins for new grouping. October Product Version 16.6

99 PDN Analysis GUI Reference Field Group filter Pin name/pin group New group Description Determines which pins of a specified type are displayed in the list box. Choices are * (all), reference, open, sink, source, and unspecified. If you do not select one group of pins as a reference group, the highest group of pins acts as the reference group. Lists all the pins which match the filter. Assign new group name for selected pins. Determines the group type the selected pins will be converted to Return Path Configuration Specify return path for the selected power pin. Field Power Net Comp Name Power Pin Ground Pin Description Name of the power net for which return path is to be specified. Use this field to filter out the list of pins based on the specified component name or pattern. The power pin for which the return path is to be specified. The ground pin specified as the return path. Return ground pin selection Field Name Description Name of the component for which you need to select a return ground pin from the given list. October Product Version 16.6

100 PDN Analysis GUI Reference Virtual Excitation Browser Field Excitation type Edit Select excitation from list Description Choose from All, Gaussian, and Pulse. Opens the Virtual Excitation Management dialog box. Choose one of the listed excitations or create a new excitation in the Virtual Excitation Management dialog box. Virtual Excitation Management Use this dialog box to add or remove an excitation source into your design that will act as the sink current in a co-design flow of board to package to die. The supported formats for excitation sources are Gaussian, Pulse, and Current Profile. In this dialog box, you add, configure, and manage excitation sources in your design. Field Excitation name Add Remove Init value Final value Rise time Fall time Period time Description Lists the available excitations. Excitation name is the userdefined name of the excitation signal that you add to your design. The name must start with an alphabetic character. Opens a pop-up window for entering an excitation source. Specify a new name for the excitation and choose the excitation type from Gaussian or Pulse. Removes the selected excitation from the list of available excitations. Specify the initial pulse value. Valid only for Pulse type excitation. Specify the initial pulse amplitude value. Valid only for Pulse type excitation. Specify the pulse rise time. Valid only for Pulse type excitation. Specify the pulse fall time. Valid only for Pulse type excitation. Specify the pulse period time. Valid only for Pulse type excitation. October Product Version 16.6

101 PDN Analysis GUI Reference Field Amplitude Delay time Width Import Export Description Specify the pulse amplitude. Valid only for Gaussian type excitation. Specify the pulse delay time. Specify the pulse width. Lets you import an existing excitation source, formatted as a text file, from an external location. Lets you export a selected excitation source as a text file to an external location. VRM Model Create or browse to a VRM model. Field Model name Browse Model Edit Description User-specified name for the VRM model. Lets you add a VRM model from the SI Model Browser. Opens Cadence-Standard VRM Editor Cadence-Standard VRM Editor Use this dialog box to set the parameters of your VRMs. Field Model name Slew inductance (Lslew) Calculate Flat resistance (Rflat) Description VRM model name as specified in the VRM Model dialog box. Rate at which the VRM can react to changes in current. Example: a VRM may take 15 microseconds to slew the current from 8- to 20-amps. Opens the VRM Input Inductance Calculation dialog box Equivalent series resistance of the capacitor that is associated with the VRM. October Product Version 16.6

102 PDN Analysis GUI Reference Field Output inductance (Lout) Output resistance (RO) Text Edit Graph Response Description Cable or pin parasitic inductance of connecting the VRM to the board. Sense resistance between the VRM and the load. Opens a text editor for modifying the model content. Displays the impedance curve of the VRM in SigWave. VRM Input Inductance Calculation Use this dialog box to calculate input inductance for the 4-element SPICE model. Field Voltage Ripple Tolerance Ramp Time Ramp Current Description The potential difference between the plane pairs. The maximum voltage droop or spike noise that the design can tolerate (expressed as a percentage of voltage). The maximum time for the VRM to react to a transient current The maximum transient current. This value is usually the same as the delta current value that you specify in the Power and Ground dialog box. October Product Version 16.6

103 PDN Analysis GUI Reference Layer Management Use this dialog box to ignore shapes and paths in the selected layers in a simulation. Field Ignored Layer Type Description Select the layer to be ignored. List of all the layers in the design. The type of layer. October Product Version 16.6

104 PDN Analysis GUI Reference Padstack Plating Parameters Field Padstack Padstack name Drill size Current threshold Plating Thickness Description Lets you filter padstack names using alphabetic and wildcard combinations. Displays the padstacks used, either in the selected net only, or in the entire design. Displays the shape and size of the padstack The maximum current that can flow through 1 mm diameter piece of copper wire. Displays the plating thickness of the padstack. This field is inactive unless one or more padstacks are highlighted. October Product Version 16.6

105 PDN Analysis GUI Reference Field Material Description Displays the materials available to plate the padstack. October Product Version 16.6

106 PDN Analysis GUI Reference Virtual VRM Management Field Model Net Pin Mirror Add Edit Delete Delete All Zoom Edit Model Description The virtual VRM model you add to the design. The power/ground net name. The pin name on which the model is added. Lets you place a virtual VRM on the design canvas. Opens the Virtual VRM dialog box for the selected model. Deletes the selected model. Deletes all the models. Zooms into the selected model in the design canvas. Opens the Cadence-Standard VRM Editor dialog box. October Product Version 16.6

107 PDN Analysis GUI Reference Virtual VRM Field RefDes VRM Lslew (Slew inductance) Rflat (Flat resistance) Lout (Output inductance) RO (Output resistance) Description Reference designator of the virtual VRM. Select a VRM model from the list or browse to the VRM Model dialog box. Rate at which the VRM can react to changes in current. Example: a VRM may take 15 microseconds to slew the current from 8- to 20-amps. Equivalent series resistance of the capacitor that is associated with the VRM. Cable or pin parasitic inductance of connecting the VRM to the board. Sense resistance between the VRM and the load. October Product Version 16.6

108 PDN Analysis GUI Reference Virtual Noise Management Field Net Excitation Add Edit Delete Delete All Zoom Description The power net to which you add a virtual noise source. The default sink current value. Lets you place a noise source in the design. Opens the Virtual Noise dialog box for the selected virtual noise source. Deletes the selected virtual noise source. Deletes all the virtual noise sources. Zooms into the selected virtual noise in the design canvas. Virtual Noise Field RefDes Description Reference designator of the virtual noise source. October Product Version 16.6

109 PDN Analysis GUI Reference Field Sink Description Select the sink current value from he list or browse to the Virtual Excitation Browser dialog box. October Product Version 16.6

110 PDN Analysis GUI Reference Virtual Probe Management Field Net Add Edit Delete Delete All Zoom Description The net to which the virtual probe is added. Lets you place a virtual probe in the design. Opens the Virtual Probe dialog box for the selected virtual noise source. Deletes the selected virtual probe. Deletes all the virtual probes. Zooms into the selected virtual probe in the design canvas. Virtual Probe Field RefDes Package Description Reference designator of the virtual probe. Name of the package. October Product Version 16.6

111 PDN Analysis GUI Reference Editing in Context PDN Analysis supports right-click access to commands in the context or pop-up menu. Commands in this pop-up menu vary in context, depending on what is selected an element on the canvas, or the canvas itself. For example, the following image shows the pop-up menus, which appear when you right-click on the canvas. October Product Version 16.6

112 PDN Analysis GUI Reference October Product Version 16.6

113 8 Using PDN EMViewer October Product Version 16.6

114 Using PDN EMViewer Overview When you have completed running PDN analysis, you can view and analyze the results in the PDN EMViewer application. PDN EMViewer is a a standalone three-dimensional viewer that enables you to visualize and analyze EM simulation results for a layout design. It can display impedance in frequency domain or voltage, current, current density, or temperature rise in time domain. PDN EMViewer is also integrated with the PDN Analysis solution. Figure 8-1 The PDN EMViewer Graphical User Interface October Product Version 16.6

115 Using PDN EMViewer The 3D EMViewer Interface The PDN EMViewer environment consists of menus, toolbars, a status bar, the Visibility, Display, and Output windows. Menus Toolbars Windows Menus The following sections describe the command menus in the PDN EMViewer window. File View Camera Movie File File menu commands This command... Open Close Does this... Opens an existing EMViewer.emv file. Closes the currently open file. October Product Version 16.6

116 Using PDN EMViewer Close All Closes all the open.emv files. Export AVI File - Exports the current playing movie as a.avi file. BMP File - Exports the image that is currently displayed in the canvas. When you export the image, it is stored as a.bmp file. Exit Note: By default, the image and the movie are saved in the same directory location as the source.emv file. Closes the PDN EMViewer window. View View menu commands Windows Toggles between showing/hiding the following: Visibility Output Toolbar Status Bar Reset to Default - Resets the visibility settings to default. October Product Version 16.6

117 Using PDN EMViewer Zoom Fit - Fits the image to the 3D Viewer canvas In/Out - Zooms in or out of the currently displayed image on the canvas Window - Zooms in on a specific portion of the canvas Rotate Rotate X/Y/Z - Rotates the viewpoint of the graph along the X, Y, and Z axis, respectively. The X and Y coordinates represent the location of the board design. You can select one layer or multiple layers to show. The Z coordinate represents the magnitude of impedance, voltage, current, and so on. Refresh Format Note: You can also rotate the 3D image by holding the Ctrl key and using the left mouse button. Refreshes/Repaints the display on the canvas. Displays one of the following data types/formats on the canvas: Impedance Voltage Current Current Density Temperature Rise Pattern Mode Worst Case Show Legend Legend Display Customize Toggles between a Grid (default) and Fill pattern. Toggles between 2D and 3D display of data. Displays the worst case impedance and frequency on the board. Displays the color legend representing various values for impedance, voltage, current, current density, or rise in temperature. Displays the Color Legend dialog box used to show analysis result with different colors comparing with the threshold. You can change the values represented by various colors in this dialog box. Shows or hides the Display window where you can set the color, brightness, and contrast of the canvas background. Customizes toolbars and menu commands. October Product Version 16.6

118 Using PDN EMViewer Always on Top Puts the PDN EMViewer application on top of all the other running applications. Camera Use the menu options to view the image from different camera angles: Top Bottom Front Back Left Right October Product Version 16.6

119 Using PDN EMViewer Movie You can perform common navigation tasks on the movie with the Movie menu. Use the Play command to run the movie which shows the impedance contour changes over the frequency range. Play Pause Stop First Previous Next Last Goto Speed Speed Up Speed Down October Product Version 16.6

120 Using PDN EMViewer Toolbars In addition to the menus, you can use the following toolbars to perform common tasks in the PDN EMViewer environment. The names and icons are self-explanatory. File Open a file Close a file Close all files Refresh the display canvas Zoom Zoom Fit Zoom In Zoom Out Zoom By Window Rotation Rotate X Rotate Y Rotate Z October Product Version 16.6

121 Using PDN EMViewer Movie Play Pause Stop First Next Previous Last Goto (Frame no.) Pattern Grid Pattern Fill Pattern Format Impedance Voltage Current Current Density Temperature Rise Display 2D 3D Worst Case October Product Version 16.6

122 Using PDN EMViewer Windows Visibility Output Display Visibility This window controls the visibility of nets and layers on the canvas. You can change the threshold value Net Display the plane in canvas Format Net Threshold Displays the threshold plane in a solid color. Represents the result being displayed on the canvas, such as Impedance or Voltage. For multiple DC nets, select each net from the list. You can change the threshold value dynamically in this field or using the slider. By changing the threshold value, you can view the impedance plane above the threshold plane with yellow/ magenta colors or under the threshold plane with green/blue colors. October Product Version 16.6

123 Using PDN EMViewer Layer Controls the visibility of various layers on the canvas. Note: For Power analysis in the Frequency domain, each layer has two sides the upside and the downside. You can specify these layers separately as shown in the previous image. Output Net Information Stack up October Product Version 16.6

124 Using PDN EMViewer Display Use this window to set the color, brightness, and contrast of the canvas background. October Product Version 16.6

125 Using PDN EMViewer Working with PDN EMViewer PDN EMViewer is a simple but useful three-dimensional viewer that enables visualize and analyze PDN analysis results in three dimensions. Launching PDN EMViewer You can launch PDN EMViewer using any one of the following methods: From the Layout Tool From the Analysis Results Context Menu In Standalone Mode From the Layout Tool You can launch PDN EMViewer from within Allegro Designer, if you have launched the PDN Analysis main form. Right-click on the canvas and choose Display 3D EMViewer: October Product Version 16.6

126 Using PDN EMViewer A selection box appears prompting you to select the analysis result you want displayed in PDN EMViewer. Open: Launches the PDN EMViewer application with a blank window. Impedance/Irdrop: Opens an existing.emv file in the PDN EMViewer window. From the Analysis Results Context Menu Immediately after completing PI plane or PI network analysis or static IR Drop analysis, you can right-click on the canvas and choose 3D EMViewer from the pop-up menu to launch the PDN EMViewer. In Standalone Mode At the system command window, type emvviewer and press Enter. Note: Ensure that the appropriate paths are set to run the current release. The PDN EMViewer application launches with a blank window. October Product Version 16.6

127 Using PDN EMViewer Figure 8-2 PDN EMViewer launched from the command prompt Opening.emv Files When you launch the PDN EMViewer from within the PDN Analysis environment, the corresponding.emv file of the selected analysis result opens in the PDN EMViewer. In a standalone mode, use the following steps to open a.emv file: 1. Choose File Open and navigate to the directory where the.emv file is stored. October Product Version 16.6

128 Using PDN EMViewer The.emv file opens in the PDN EMViewer main window. Analyzing PDN Analysis Results Use the various Menus, Toolbars, and Windows of the PDN EMViewer application to view and manipulate PDN analysis results in a 3D environment. 1. Click the Layer tab on the Visibility window. 2. Select a layer of interest. 3. Rotate the X, Y, and Z coordinates to view the image in 3 dimensions. 4. Change the threshold values and view the results on the canvas. 5. Click the Play button to run the movie. 6. Export the currently displayed image to a.bmp file or save the movie as a.avi file. October Product Version 16.6

129 9 Co-Analysis Capabilities October Product Version 16.6

130 Co-Analysis Capabilities Overview Allegro PCB PDN Analysis support the co-simulation for multiple boards and die-packageboard through the electrical connections. Before you do the co-simulation, you need to prepare the power network model for the other board or die/package. To define the pin mapping relationship, you may need to create a PTMF (port terminal mapping file). The current profiles from IC tools such as VoltageStorm from Encounter can be consumed. Adding Power Supply from Other Boards To support two boards co-analysis say a daughter card and a mother board, the power is supplied by the mother board. So you need to get the power model for the mother board in advance and define the connection relationship between the daughter card and the mother board. For example, they are connected by a connector as depicted in the following image. October Product Version 16.6

131 Co-Analysis Capabilities 1. To create the connection, right click and choose Quick Utilities Power Supply. Note: Ensure that the PDN Analysis application is launched. The External Power Supplier Management displays. October Product Version 16.6

132 Co-Analysis Capabilities 2. Click the Add button to show a form where you can specify a name for the power supplier (mother_board): 3. Click OK. 4. Back in the External Supplier Management dialog, select File Load from the dropdown list of Power Supplier Model to browse the power model as below: The power supplier model can be in the DML or Spice sub-circuit formats. You also need to provide the port terminal mapping file (.ptmf). 5. Select the required power supplier model file and then select an appropriate model from the list. 6. Right-click on the Connection Pin column name and choose Auto Connect from the pop-up menu to automap the pin connections. October Product Version 16.6

133 Co-Analysis Capabilities This completes the multiple board connection settings. You can run PDN analysis as done in the previous sections. Settings for Die-Package-Board Co-Analysis To support die, package, or board co-analysis, you need to prepare the package and die power circuit in advance and then connect them with the board. In PDN Analysis main form, when you select an IC component, you can choose the Edit Profile option and add the package model and die model for the component: October Product Version 16.6

134 Co-Analysis Capabilities 1. Click Edit Profile, to browse the package and die models for this component. 2. Right-click on the Board Pin column name and choose Auto Connect from the pop-up menu to automap the pin connections or manually specify the connections. To remove the settings, you can select Reset from the drop-down list of Package Model and click the Del button for the Die model. When the connection is created, you can perform the co-analysis using the previously described method. October Product Version 16.6

135 Co-Analysis Capabilities Plotting Probe Ports on Die Pads The PDN Analysis solution facilitates the export of DC and AC analysis results for dies on the package and die model. It allows you to plot probe ports on the die pad for the PDN Co-design flow. You can specify VRM and Probe port settings for power-supplier board co-design in the External Power Supplier Management dialog as shown in Figure 9-1 on page 135. Figure 9-1 Power-Supplier Board Co-Design Setting on VRM and Probe Ports To access this dialog box, choose Quick Utilities Power Supply. Depending on the check box you select in the Print column, the corresponding port is included or ignored for plotting. October Product Version 16.6

136 Co-Analysis Capabilities To specify Sink current and Probe port settings for package/die co-design, use the PDN Package Profile Editor as shown in Figure 9-2 on page 136. Figure 9-2 Package/Die Co-Design Setting on Sink Current and Probe Ports To access this dialog, in the Components and Ports tab of the PDN Analysis UI, select a component and click the Edit Profile button. Depending on the check box you select in the Print column, the corresponding port is included or ignored for plotting. October Product Version 16.6

137 Co-Analysis Capabilities Figure 9-3 on page 137 shows the waveform generated after you run the analysis with probed package/die ports. Figure 9-3 AC Analysis Result with Probed Package/Die Ports Figure 9-4 on page 138 and Figure 9-5 on page 139 show analysis report file with probed package/die ports for Static IR Drop and Power Integrity analysis, respectively. October Product Version 16.6

138 Co-Analysis Capabilities Figure 9-4 Analysis Report File (Static IR Drop) with Probed Ports October Product Version 16.6

139 Co-Analysis Capabilities Figure 9-5 Analysis Report File (Power Integrity) with Probed Ports October Product Version 16.6