University of Kansas EECS Circuit Board Fabrication Tutorial for 212 Lab

Transcription

1 University of Kansas EECS Circuit Board Fabrication Tutorial for 212 Lab Preparing For Export... 1 Assigning Footprints... 1 Recommended Footprints... 2 No Connects... 3 Design Rules Check... 3 Create Blank PCB... 4 Create Netlist... 6 Place Components... 7 Modify the Padstack... 8 Shop s Standard Drill Sizes... 9 Routing the Board Gloss the Board...11 Print Design for Etching Other Resources...13 miscellaneous Note: It is the EECS 212 TA s job to update this document along with the version number. Any document updates should be given to the EECS shop manager at the end of every semester.

2 Making your schematic in Allegro Design Entry CIS to be Compatible with PCB Editor Create a new Analog or Mixed A/D blank project. Select and delete all libraries currently in the Libraries field. The only library left will be the Design Cache (because it may not be deleted), but do not use any of its parts. Add the libraries located in the following folder: P:\Cadence\SPB_16.3\tools\capture\library\pspice\EECS libs Create your schematic for simulation using the components in this folder. The recommended components are: Resistor R/ANALOG Capacitor C disc/analog OP Amp LM318 1

3 Preparing For Export Circuit Board Fabrication Tutorial for 212 All virtual components, such as voltage sources should be removed. These components should be replaced with test points. Be sure to assign at least one test point to ground. Test points are located in the connector library. Vac_+ V_DC_Supply _5Vdc_+ 1Vac 0Vdc 1 1 TEST POINT TEST POINT 5Vdc 1 1 TEST POINT TEST POINT V_DC_Supply _5Vdc_- Vac_- 2

4 Assigning Footprints Footprints for each part placed on the schematic must be defined. The only time a footprint requires changing is for unique components that may be used in EECS 501/502 or EECS 541/542. Select all the components by dragging the cursor. Do not select the title box. Next, select Edit > Properties. This brings up the property editor window. The properties should be filtered by Orcad-Layout Enter the footprint name for each component in the PCB Footprint box. 3

5 Recommended Footprints The libraries with working footprints are located in the following directory by default, P:\Cadence\SPB_16.3\tools\capture\library\pspice\EECS libs Resistors RES400 Capacitors CAPCK05 Diodes DO41 8 Pin DIP Sockets DIP8_3 14 Pin DIP Sockets DIP14_3 TO220 Package Transistors TO220AB TO92 Package Transistors TO92100 Variable Resistors VRES16 Test Points TP These footprints may not be the exact ones that you need for your project and should be checked before being used. They are meant to only be a starting point. Once each footprint is assigned, close the property editor. 4

6 No Connects When a component has pins that are not connected to anything, no connect symbols must be placed on that pin. The No Connect button is circled to the right. Unconnected pins are shown as boxes. When a No Connect is placed on the unconnected pin it is shown as a X, this is circled below. To remove a no connect click the X with the No Connect tool again. Design Rules Check To check for errors, run the Design Rules check. Click the Project Manager window and highlight your design. Select Tools > Design Rules Check Make sure Create DRC Markers, Report Identical Part References and Checked Unconnected Nets boxes are checked More info: - A Net is a logical construct that originates in a schematic and is transferred to a board to describe required electrical connections. Click OK. Any errors will show up as green circles. Double click the circle to get more information about the error. Correct all the errors before moving on. To remove the green error circles, select them and press Delete 5

7 Blank PCB boards were already created to save time. If you choose this option, the following section, Create Blank PCB, can be ignored. Blank boards can be found in P:\Cadence\Board_Templates. Their titles represent the dimensions of the board in inches. For example, if the board 2x3 is chosen, the board will be 2 by 3. To customize the board outline so it fits around your circuit, go to Setup >> Outlines >> Board Outline The figure to the right shows an example of this. Create Blank PCB A blank PCB is created in PCB Editor. Here the board size and other parameters will be defined. Start by opening PCB Editor by going to Cadence SPB 16.2 > PCB Editor. Create a new folder in your project directory called allegro. Choose File > New... from the menu. In the first dialogue box, set the Drawing Type to Board (wizard). Click Browse..., navigate to your new allegro directory and give the board a name such as bare.brd. Click Open then OK to bring up the new board wizard. This takes you through several screens to define the parameters of the PCB. Some of these are obvious, such as the size of the board, while others set up the design rules the width of tracks on the PCB, how much space must be left between them, and so on. 1. The first screen is purely descriptive. Read it, then click Next >. 2. This asks for a board template. Select No (probably the default) and click Next. 3. You are next asked for a tech file. This is short for a technology file, which specifies the design rules number of layers, widths and separation of tracks and so on. Select No and click Next. 4. This asks for a board symbol. Select No again and click Next. 5. Units should be set to Mils. The drawing size should be set to A. The At the lower left corner of the drawing radio button should be selected. Click Next. More info: - Mil unit is commonly used in PCB footprint and PCB board design. - 1 mill = inch 6

8 6. Set the grid spacing to be 25 mils. The Etch layer count is the number of copper layers on the board the number of layers of tracks for signals and power. This should be set at 1 for the 212 lab because the etching only occurs on one side. The Generate default artwork films radio button should be selected. Click Next. 7. Leave the names of the layers as Top and Bottom and their types as Routing Layer. Click Next. 8. Minimum line width is the minimum trace size. It is recommended that 40 mils is used for this value. The absolute minimum trace width is 12 mils. This value will propagate into the other boxes. For the Default via padstack, click on the button with... and choose Via. Click Next 9. Select the rectangular board radio button. Click Next. 10. Enter the size of the board. Remember that 1 inch is 1000 mils. Specify the Route keepin distance, a recommended size is 100 mils. A keepin means that objects must be kept inside the specified region. In this case it means that tracks cannot go any closer than 100 mils to the edge of the board. It gives a border around the PCB to aid handling and manufacture. The recommended Package keepin distance is 250 mils. Components must be placed within this keeping and therefore cannot be closer than 250 mils to the edge of the board. The gap between the two keepins allows you to run tracks around the outside of all the components, which is often helpful on a more complicated board. Click Finish. Save and close the board. 7

9 Create Netlist Go back to Design Entry CIS. Click the Project Manager window and highlight your design. Click Tools>Create Netlist. Check the Create or Update PCB Editor Board (Netrev) box and put the board previously created in the Input board file text box. Next choose an output file name (not including spaces) in the Output Board File text box. Click OK. There will be a warning saying the design will be saved. Click OK. The netlist has been exported and PCB editor should open again with the new design. The board will appear empty at first. If an error appears view the netlist log at the bottom of the Capture CIS window and correct all the errors, then run Create Netlist again. If no error appears, click Ok and continue. Warnings can be ignored. 8

10 Place Components In PCB Editor, click Place>Manually to place components. Circuit Board Fabrication Tutorial for 212 Check the box next the part that is to be placed. Click the area of the board where the component is to be placed. Repeat this for each component. Multiple components can be selected at one time. They are placed in the order they appear on the list. Components can also be placed automatically. To do this click Place>Quickplace then click Place. When complete click OK. The lines connecting the component pads are called the rats nest. They represent the logical connections of the components. After components are placed, they may need to be moved. To do this, first, mouse over the Find tab. Next, click All Off. Then, check the Symbols box. Now, only the component symbols can be selected. This prevents other parts of the component from inadvertently being selected and moved. To move the component, click it and drag the component to the desired location. To rotate a component, select it (left click), then right click and select Spin. Left click when the component has reached the desired orientation

11 Modify the Padstack Padstacks are the pad definition for each layer. Increasing the Padstack size will create a larger surface to solder components to. If the Padstack size is left to default, the pads will be extremely small and difficult to solder to. The recommended pad size for most projects is 90 mils. To change the pad size click Tools>Padstack>Modify Design Padstack Left click a pad to be changed, then right click and select Edit. When the Padstack Designer window appears, click the Layers tab. Circuit Board Fabrication Tutorial for 212 Click on the TOP layer, then change the Regular Pad width and height to the desired size. Next make the Anti Pad 10% larger than the regular pad. Repeat this process for the BOTTOM layer. 10

12 To change the drill size select the Parameters tab. The drill size should be one of the standard drill sizes. If a non-standard drill size is required notify the shop before completing your design. Shop s Standard Drill Sizes Mils Inch Millimeter Set the size in the Drill diameter box. Press Tab to update the image. When complete click File>Update to Design. A warning will appear. Close the warning box and click Yes when a second warning pops up. Continue this process until you can see that all the pad sizes have been changed. 11

13 Routing the Board First check that trace widths are set correctly. Click Setup>Constriants>Physical, this brings up the Allegro Constraint Manager. From here you can define trace widths for individual nets, layers, and regions or for the entire board. The Line Width minium should be the same as what was set when the blank board was created. If this step was skipped, trace width can be corrected here. Remember that the recommended trace size is 40 mils and the minimum is 12 mils. Circuit Board Fabrication Tutorial for 212 Once the trace width has been verified, the board can be routed. At this point Stop and save the design Click Route>Route Automatic, this will bring up the automatic router dialogue box. For routing on just one layer (single sided board) deselect the unwanted layer in the dialog box. Select the Use smart router radio button. 1 Click Route to route the board. Wait for this process to complete, it takes some time. Click Results and check that routing is 100% complete. Click Close to exit the automatic router di 12

14 Click Route>Gloss>Parameters. This opens the Glossing Controller window. Check Run for Via eliminate, Line smoothing, Center lines between pads, and Improve line entry into pads. Click Gloss. This cleans up the routed tracks and miters the corners. It also removes any extra vias. 13

15 Print Design for Etching Circuit Board Fabrication Tutorial for 212 This section can be skipped if the PCB is to be milled. If chemical etching is to be used, complete this section. For chemical etching, the layout is printed onto transfer paper using a laser printer. First a placement reference needs to be printed on plain paper. This reference will be used to aid in assembly. First click Display>Color/Visibility. This brings up the Color Dialog window. Click the Board Geometry folder on the left side of the window. Disable all subclasses. This can easily be accomplished by double clicking the All check box. Repeat this process for the Areas, Package Geometry and Components folders. Next, in the Components folder, enable Assembly_Top. Click the Package Geometry folder and enable Assembly_Top. Click Ok to close the color dialog window. Click File>Plot Setup and under Plot method click the Black and White radio button, then click Ok. Finally, click File>Plot and print the layout reference. To print the layout that is to be transferred on to the copper board, click Display>Color/Visibility. Click the Package Geometry folder and disable the Assembly_Top subclass. Click the Components folder uncheck Asembly_Top under the all column. Click File>Plot to print the layout. 14

16 Other Resources Electronic Design Project 2: Cadence OrCAD PCB Designer, Notes for demonstrators. Professor John H. Davies 15