Lab 9 PCB Design & Layout

Transcription

1 Lab 9 PCB Design & Layout ECT 224L Department of Engineering Technology

2 Lab 9 PCB Traces Size dependent upon electrical requirements, design constraints (routing space and clearance), and trace/space resolution of PCB manufacturer The larger the traces the lower their resistance and inductance Traces can be thinned when necessary to accommodate tight space limitations (i.e. between pins of an IC) Called necking or necking down

3 Lab 9 PCB Traces Electrical requirements Trace width dependant upon current requirements Current (A) Trace Width (inch) Proper trace spacing is important to ensure no shorts exist from manufacturing

4 Lab 9 PCB Pads Pad sizes and shapes are dependant on the components used and the manufacturing process used to assemble the boards Pad/hole ratio Each manufacturer has a minimum specification for this due to alignment tolerances between board layers Leaded components typically use round pads Pin one identified using a different shape pad (square/rectangle) with the same dimensions as the other pads

5 Lab 9 PCB Pads Surface mount components generally use square or rectangular pads (without holes) Pin one identified using marker in the silkscreen Through-hole pin 1 Surface mount pin 1

6 Lab 9 PCB Layers PCBs are comprised of copper layers, each able to contain traces PCB designs can also contain additional layers for the solder mask and silkscreen Solder mask is the colored layer on the top and bottom sides of the PCB that masks solder from bonding to traces and other copper surfaces not used for soldering Silkscreen is the information layer on the top and/or bottom sides of the PCB that provides labeling (refdes) and other useful information

7 Lab 9 PCB Layers Solder mask Silkscreen No solder mask

8 Lab 9 PCB Vias Vias are used to connect traces on different copper layers together using plated holes (filled through hole pads) Typically smaller holes than used for through hole pads (0.5mm 0.7mm) Vias are categorized by the layers they are connecting Blind via Buried via

9 Lab 9 PCB Fills/Planes Fills flood a designated area of a layer with copper which flows around other copper elements (pads, traces) Useful in creating ground planes Can be filled or hatched Filled plane Hatched plane

10 Lab 9 PCB Component Placement Good component placement is critical to proper electrical performance and can greatly reduce the time spent laying out the board There is no right way to place components but several key rules to follow Use snap-to-grid and set all default values before starting placement Break circuit into blocks according to connectivity Identify the critical signals and plan accordingly Printout component layout to verify all component footprints and placements

11 Lab 9 PCB Trace Routing With Components placed, routing starts from ratsnest connections Route critical signal traces first Power and ground traces are typically routed first on separate layer(s)

12 Lab 9 PCB Trace Routing Route signal traces between components is each block then between the blocks Trace layout rules Minimize trace lengths Only use 45 angles for traces Route traces to the center of pads Select trace width according to current requirements Utilize autoroute capabilities for routing non-critical traces Perform all testing possible with layout software used Printout routed layout to visually verify

13 Lab 9 PCB Design Files The finished board layout is captured in a series of design files (exact ones specified by manufacturer) Gerber photoplotter 274X or 274D DXF IPC-D-356A Netlists NC Drill SVG Additional files can also be generated depending on layout software used Board Statistics Bill of Materials

14 Lab 9 How a PCB is Fabricated

15 Lab 9 How a PCB is Fabricated

16 Lab 9 How a PCB is Fabricated