(SO-DIMM) 64 MB / 128 MB / 256 MB / 512 MB PC100

Transcription

1 Product Datasheet For Synchronous Dynamic Random Access Memory Dual In-line Memory Modules (SO-DIMM) 64 MB / 128 MB / 256 MB / 512 MB PC100 Rev 1.0 Hexon Technology Pte Ltd 35, Kallang Pudding Road, #09-04, Tong Lee Building Block A, Singapore TOTAL MEMORY SOLUTIONS NCP is a registered trademark of Hexon Technology Pte Ltd

2 NCP SDRAM DIMM NCP SDRAM DIMM modules are designed for today s desktop systems that demand performance at a low cost. All modules are manufactured and tested under stringent conditions to ensure the level of reliability that is expected of today s desktops. We test our SDRAM DIMM on system motherboard and with the application software and desktop operating system most commonly used in the system. Burn-in testing on system is conducted during qualifications of each new product to ensure every design is able to deliver the performance and reliability expected. Independent benchmark tests, such as Winstone, are used to thoroughly test the system. General Features 168 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-Line SDRAM Module for desktop systems main memory applications JEDEC standard Synchronous DRAMs (SDRAM) Single +3.3 V (± 0.3 V) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs, outputs are LVTTL compatible Serial Presence Detect with E 2 PROM Compliant to JEDEC PC100 DIMM Specifications Available in 64/128/256/512 MB module package Supports desktop motherboard with up to a maximum of 100 MHz FSB Refresh rate: 4K / 64ms Operating temperature: 0 to 70 o C Pg.2

3 Specifications General Standard : Fully compatible to Intel and JEDEC specifications for SDRAMDIMM Word length : 64 bit Configuration : 8M x 64 bit / 16M x 64 bit / 32M x 64 bit Power supply : 3.3 V +/- 0.3 V Interface : All inputs, outputs are LVTTL-compatible Burst length : Programmable to 1, 2, 4, 8 or full page Burst type : Linear / Interleave Serial Presence Detect (SPD) : 256-Byte EEPROM Clock and Clock Enable Clock frequency, f CK : 100 MHz (max.) Data access time, t AC : 6 ns (max.) Clock cycle time, t CK : 10 ns (min.) Clock high pulse width, t CH : 3 ns (min.) Clock low pulse width, t CL : 3 ns (min.) Transition time, t T : 0.5 ns (min.) to 10 ns (max.) Setup and Hold Times Input setup time, t IS : 2 ns (min.) Input hold time, t IH : 1 ns (min.) CKE setup time, t CKS : 2 ns (min.) CKE hold time, t CKH : 1 ns (min.) Mode register setup time, t RSC : 2 CLK (min.) Power down mode entry time, : 0 ns (min.) to 8 ns (max.) t SB Common Parameters RAS to CAS delay, t RCD : 20 ns (min.) Precharge time, t RP : 20 ns (min.) Row active period, t RAS : 48 ns (min.) Row cycle time, t RC : 70 ns (min.) Row active to row active delay, : 16 ns (min.) t RRD CAS to CAS delay (same bank), t CCD : 1 CLK Refresh Cycle Refresh period, t REF : 15.6 µs, 4K / 64 ms Self refresh exit time, t SREX : 1 CLK (min.) Read Cycle Data out hold time, t OH : 3 ns (min.) Data out to low impedance, t LZ : 0 ns (min.) Data out to high impedance, t HZ : 3 ns (min.) to 8 ns (max.) DQM data out disable latency : 2 CLK cycles (max.) Write Cycle Data input to precharge, t WR : 2 CLK cycles (min.) Data in to active/refresh, t DAL : 5 CLK cycles (min.) DQM write mask latency, t DQW : 0 CLK cycle (min.) Pg.3

4 All control and address signals are synchronized with the positive edge of externally supplied clocks. The SDRAM device lines (DQ) are connected directly to the DIMM tabs through 10 Ω series resistors. Pg.4

5 Clock Diagrams 1) Read Cycle Timing Diagram Pg.5

6 2) Write Cycle Timing Diagram Pg.6

7 3) Auto Refresh Mode Timing Diagram Pg.7

8 4) Power Down Mode Timing Diagram Pg.8

9 Pin Configuration PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 V SS 43 V SS 85 V SS 127 V SS 2 DQ0 44 DNU 86 DQ CKE0 3 DQ1 45 S2# 87 DQ S3#* 4 DQ2 46 DQMB2 88 DQ DQMB6 5 DQ3 47 DQMB3 89 DQ DQMB7 6 V DD 48 DNU 90 V DD 132 RFU 7 DQ4 49 V DD 91 DQ V DD 8 DQ5 50 NC 92 DQ NC 9 DQ6 51 NC 93 DQ NC 10 DQ7 52 NC 94 DQ NC 11 DQ8 53 NC 95 DQ NC 12 V SS 54 V SS 96 V SS 138 V SS 13 DQ9 55 DQ16 97 DQ DQ48 14 DQ10 56 DQ17 98 DQ DQ49 15 DQ11 57 DQ18 99 DQ DQ50 16 DQ12 58 DQ DQ DQ51 17 DQ13 59 V DD 101 DQ V DD 18 V DD 60 DQ V DD 144 DQ52 19 DQ14 61 NC 103 DQ NC 20 DQ15 62 NC 104 DQ NC 21 NC 63 CKE1* 105 NC 147 NC 22 NC 64 V SS 106 NC 148 V SS 23 V SS 65 DQ V SS 149 DQ53 24 NC 66 DQ NC 150 DQ54 25 NC 67 DQ NC 151 DQ55 26 V DD 68 V SS 110 V DD 152 V SS 27 WE# 69 DQ CAS# 153 DQ56 28 DQMBO 70 DQ DQMB4 154 DQ57 29 DQMB1 71 DQ DQMB5 155 DQ58 30 S0# 72 DQ S1#* 156 DQ59 31 DNU 73 V DD 115 RAS# 157 V DD 32 V SS 74 DQ V SS 158 DQ60 33 A0 75 DQ A1 159 DQ61 34 A2 76 DQ A3 160 DQ62 35 A4 77 DQ A5 161 DQ63 36 A6 78 V SS 120 A7 162 V SS 37 A8 79 CK2 121 A9 163 CK3 38 A10 80 NC 122 BA0 164 NC 39 BA1 81 NC/WP 123 A SA0 40 V DD 82 SDA 124 V DD 166 SA1 41 V DD 83 SCL 125 CK1 167 SA2 42 CKO 84 V DD 126 RFU 168 V DD Pin Name A0-A11 Address Inputs (Multiplexed) BA0-BA1 Bank Select Addresses DQ0-DQ63 Data Inputs/Outputs CK0-CK3 Clock Inputs RAS# Row Address Strobe CAS# Column Address Strobe CKE0-CKE1 Clock Enable DQMB0-DQMB7 DQ Mask Enables S0#-S3# Chip Selects WE# Write Enable SA0-SA2 Decode Inputs (EEPROM Address) WP Write Protect V DD Power Supply (3.3 V) Vss Ground NC No Connection Pg.9

10 Package Outlines Pg.10

11 Product Compatibility The product has been tested to be compatible to the following motherboards: Intel (810, 815) Gigabyte AOpen Asus Abit MSI ALi Chaintech The product has been tested to be compatible to the following PC systems: Dell Dimension & OptiPlex HP Brio & Pavilion IBM NetVista Gateway Sony Vaio Acer Datamini Hitachi NEC Ranger Digitek WhiteBox Creative Pg.11