The AT697F evaluation board provides the following features: On-board power supply circuitry

Transcription

1 APPLICATION NOTE AT697F Evaluation Kit USER GUIDE Features The AT697F evaluation board provides the following features: On-board power supply circuitry for external power supply sources connection for board powering by the CPCI interface On-board reset On-board memories FLASH (40-bit capability) SRAM (40-bit SRAM capability) SDRAM (40-bit SDRAM capability) Status indicators Power Processor Error + Run DSU activity Clock circuitry On board oscillator for clock generator External clock source connection RS232 hardware connector dedicated to the Debug Support Unit (DSU) RS232 hardware connector dedicated to a universal UART PCI interface Host / Satellite capability User defined push-buttons User defined LEDs Expansion connector 10-pin JTAG interface connector Description The AT697F Evaluation Kit is a development system for the ATMEL AT697F, 32-bit SPARC V8 processor based on LEON2 fault tolerant model. The kit is equipped with a rich set of peripherals that make the AT697F Evaluation Kit perfect evaluation platform to quickly and easily develop application on the AT697F processor. This guide shows the user how to quickly get started with this kit. 7540HAERO10/15

2 Table of Contents 1. Overview Scope Deliverables Features Hardware description Block diagram Evaluation board Manufacturing configuration Board power supply Processor Processor Package Processor Pin-out Memories Memory organization overview PROM (or Flash) PROM Overview PROM40 Configuration (SW37.7 is OFF) PROM8 Configuration (SW37.7 is ON) PROM Expansion RAM Overview SRAM Configuration SDRAM Configuration Board HMI Board press buttons Board LEDs Board display UART interface Serial link Serial link PCI interface Clock management Clock overview Internal clocks External clocks Processor clock configuration Evaluation Kit Reset Hardware reset Alternate reset Supply voltage supervisor Space Programmer (SPP) reset Watchdog reset Debug Support Unit JTAG connector Test Points Current measurement test points Clocks test points System and CPCI test points Expansion connector Mechanical drawing Board History Appendix A Getting Started AT697 Development Kit Content Handling System requirements

3 3.4 Installing software development package Hardware setup Default switches configuration: Power supply setup: Serial communication link: GRMON: Run your first application Appendix B Schematics Revision History

4 1. Overview Figure 1-1 AT697 Evaluation board v Scope The AT697F eveluation kit aims at protoyping easly applications running on an AT697F processor. This guide focuses on the description of the AT697F evlaluation kit. 1.2 Deliverables The AT697F evaluation kit package contains the following items: 1x AT697F Evaluation kit Rev 3.0 1x AT697F processor in MQFP256 package 1x Power supply cable with 2.1mm Jack connector 2x RS232 cables 1 CD Rom 4

5 1.3 Features Here is an overview of the main operational features embedded on the evaluation board: Table 1-1. AT697F V3.0 board features Characteristics Specifications MCU AT697F, powered in 3.3V and 1.8V Board Power Supply Clocks generator Connector Memory User Interface to AT697F Audio jack connector (3.5mm) 3x Terminal blocks (direct 5V, 3.3V and 1.8V) Compact-PCI powering 25MHz clock generator 100MHz with PLL 33MHz PCI 1x RS232 1x Clock Configuration Manager (SPP) 2x SMB Clock input 1x JTAG 1x RS232 Debug Interface 2x Expansion Connectors 1x Compact-PCI 1x SMB Analog input 2x Expansion connector 8 Mbits flash / 32-bits wide (40-bits capability) 8 Mbits flash / 8-bits wide 16 Mbits SRAM / 32-bits wide (40-bits capability) 256 Mbits SDRAM / 32-bits wide (40-bits capability) 1x RESET button 5x push buttons 3x LED 1x LCD display 1x DSU break button 1x DSU LED activity 1x Potentiometer 1x Temperature sensor 2x Current measurement 5

6 2. Hardware description 2.1 Block diagram Figure 2-1 AT697F Evaluation board block diagram AT697F Interger Unit (SPARC V8) I-Cache D-Cache SDRAM JTAG Connector RS232 serial link DSUACT LED DSUBRE Button FPU JTAG DSU AMBA Controller AMBA bridge Memory controller Buffer Flash conf EDAC configuration Flash 8 bits Flash 40 bits SRAM 40 bits SKEW 0 configuration PCI/AMBA bridge PCI PCI interface SKEW 1 configuration CLK EXT 1 connector SPP Connector Clock generator Clock configuration PLL configuration Clock ADC Current measurement AIN Connector Potentiometer Reset configuration Watchdog Timers Interrupt Controller Temperature Sensor PIO LEDs Alternate reset Reset control Reset LCD Display Reset button Push Buttons ALIM EXT Regulators RS232 RS232 serial link Direct 1V8 Direct 3V3 1V8 Reg / Ext 3V3 Reg / Ext UART Clock configuration CLK EXT 2 connector Direct 5V 5V Reg / Ext Expansion connectors Legend: Switch Connector 6

7 2.2 Evaluation board Figure 2-2 Evaluation board overview Configuration switches SRAM CPCI Connector Clocks generator Buffers DSU interface Expansion connector SDRAM Expansion connector 1V8 direct power 1V8 source selection 3V3 direct power Power Supply 3V3 source selection 5V direct power HMI LEDs 5V source selection EXT power 8-12V LCD 240x320 HMI Buttons 7

8 Figure 2-3. Front panel overview Processor state ADC Ch 1 (Unused) Reset Button SPP Connector UART Ext clock Power supply state JTAG Connector UART 1 DSU Connector Processor Ext clock 2.3 Manufacturing configuration The Evaluation kit embeds a DIP switch allowing the user to configure several parameters. During this application note, the switch is named SW37 and the switch number of the device is named with a.x. The following array describes the initial configuration: Figure 2-4. Configuration switches Table 2-1 Initial configuration state Name Initial state Function SW37.1 OFF Actives EDAC SW37.2 ON Actives the Bypass (thus disable the PLL) SW37.3 OFF SKEW 0 configuration SW37.4 OFF SKEW 1 configuration SW37.5 OFF Connect the processor watchdog to the RESET device SW37.6 OFF Select the processor clock. SW37.7 OFF This switch will select the PROM width. SW37.8 OFF Select PIO3 signal. SW37.9 OFF N.C. SW37.10 OFF N.C. 8

9 2.4 Board power supply With the default configuration, the AT697 board shall be powered from the 2.1mm Jack connector with a 8V up to 12V power supply source. A power supply source capable to deliver up to 10W shall be used (10W figure can be achieved when daughter boards are connected to the expansion connectors). It is strongly recommended that the power supply is current limited in order to prevent damage to the board or power supply in case of over-current. Evaluation board can be powered through different ways: Figure 2-5 Power supply diagram When PCI is used, 3V3 regulator and 5V regulator are automatically shut down to avoid conflict with CPCI power supplies. Important: when the board is powered from the CPCI connector, switch for 3.3V and 5V shall be placed in ext position whereas switch 1.8V shall be keep in reg position. Do not connect any power supply except the one coming from CPCI connector. 9

10 2.5 Processor Processor Package On the evaluation kit, the AT bit SPARC processor is embedded. The processor package is the MQFP-256 space qualified package. Figure 2-6 MQFP-256 package Processor Pin-out 10

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13 2.6 Memories The AT697 Evaluation kit implements a full set of memories representative of the processor memory controller capability. All three memories areas available are implemented, including PROM, SRAM and SDRAM memories Memory organization overview To able the usage of AT697F processor with SDRAM memories at 100 MHz, a set of buffer is implemented to isolate this kind of memory. Logic glue set the buffer to write direction when SDRAM is used to avoid interferences with others memories. Figure 2-7 Memory organization SDRAM 40 bits AT697F Logic to configure buffer operation Buffer Flash configuration SRAM 40 bits Flash 40 bits Flash 8 bits Legend: Fast memory Slow memory Switch PROM (or Flash) PROM Overview The AT697F is able to work with two bus widths: 8 bits or 32 bits. In both cases, the processor can use the EDAC mode. If EDAC is enabled on the PROM 40, the processor needs 8 more bits. The evaluation kit is delivered with 8 Mbit flash - 32-bits wide (40-bits capability). The ROM default configuration at delivery time is 32-bit mode (EDAC off). The Flash memories can be programmed using the DSU interface. To keep the same quantity of memory with or without the EDAC, the evaluation board embeds 3x 16bits flash memories: 2 chips are for data and 1 is for the EDAC capability. The following array summarizes the different cases. 13

14 Table 2-2 PROM code sizes ROM bus width EDAC Code size 8 bits Disabled 8 Mbits x1 8 Mbits available 8 bits (add a 5 th bit for EDAC) Enabled 8 Mbits x Mbits available 32 bits Disabled 8 Mbits x2 16 Mbits available 40 bits (32 bits data + 8 bits EDAC) Enabled 8 Mbits x3 16 Mbits available IMPORTANT: until now, PROM8 is not recognized by GRMON. The AT697 PROM bus width is configured at reset time according to PIO[1:0] value. Under reset the processor samples PIO[1:0] and reports its value to the memory configuration register PROM40 Configuration (SW37.7 is OFF) The 40-bit boot PROM is based on three M29W800D Flash memories (U19, U20 and U21). These chips are directly soldered on the board. PROM 40 is implemented on the bottom side of the board as shows the following picture: Figure 2-8. PROM40 implementation In order to use the 40-bit mode, the following configuration shall be respected: SW37.7 is OFF PROM8 Configuration (SW37.7 is ON) The 8-bit boot PROM is based on three M29W800D Flash memories (U22). The chip is directly soldered on the board. PROM8 is implemented on the bottom side of the board close to the PROM40. IMPORTANT: when EDAC is activated with PROM8, memory available is less than without EDAC. 14

15 PROM Expansion The AT697 processor can control up to 256Mbytes of PROM. The evaluation board can handle up to 2M bytes of PROM code. For applications that need more PROM capacity, it is possible to extend the total PROM capacity by connecting a daughter board to the expansion connectors. All PROM control signals are provided on these expansion connectors. Please refer to the Expansion Connectors - section 2.15 for details on signal assignment RAM Overview The evaluation kit allows the user to work with SRAM and SDRAM SRAM Configuration The evaluation kit implements one bank of SRAM which starts at memory address 0x There are 2 components for this function: 1x SRAM 32 bits for the data/code: AT68166F-YS18-E (U35) 1x SRAM 8 bits for the checkbit (EDAC protection): AT60142H-DS15M-E (U36) This provides an access to 16MBits of SRAM data/code. Figure 2-9. SRAM 40 implementation 1 1: SRAM 32bits for data 2: SRAM 8 bits for EDAC 2 Because of an inversion of write enable signals WE[3:0], the processor can t use SRAM in 8 bits mode without a patch. Since V3.0.2 a modification has been is done to allow the processor the use SRAM in 8 bits mode. Following picture illustrate the fixe in the schematic (p36): 15

16 SDRAM Configuration The evaluation kit implements one bank of SDRAM which starts at memory address 0x There are 2 components for this function: 2x SDRAM 16 bits for the data/code: MT48LC16M16A2P-6A (U25, U26) 1x SDRAM 16 bits (only 8 bits are used) for the checkbit (EDAC protection): MT48LC16M16A2P-6A (U27) This provides an access to 256MBits of SDRAM data/code Figure SDRAM implementation Top side 1 Bottom side 2 1: SDRAM for data 2: SDRAM for EDAC 16

17 2.7 Board HMI The user can interact with the board through 5 press buttons, 3 LEDs and 1 LCD display Board press buttons Press buttons are all pulled up to 3.3V with a 4.7KΩ resistor. Figure 2-9. Press button implantation Table 2-3 Press buttons mapping Name Function Processor connexion HMI_PB1 Press button left PIO 13 HMI_PB2 Press button right PIO 12 HMI_PB3 Press button up PIO 10 HMI_PB4 Press button down PIO 11 HMI_PB5 (1) Press button enter (1) PIO 3 (1): To use this function, SW37.8 must be OFF Board LEDs LEDs are driven by a NPN transistor. A hight level on a PIO put the LED on. Figure LEDs implantation Table 2-4 LEDs mapping 17

18 Name Function Processor connexion HMI_LED0 LED0 PIO 0 HMI_LED1 LED1 PIO 1 HMI_LED2 LED2 PIO Board display The LCD display reference is: ET024011DHU. It is connected to the processor in serial mode (BS0 = 0 and BS1 = 1). Parallel mode and tactil wires are accessible only thourgh the expension connector. Table 2-5 Display mapping Name Function Processor connexion HMI_LCD_SDA Display serial data PIO 5 HMI_LCD_NWR_SCL Display serial clock PIO 6 HMI_LCD_CS Display chip select PIO UART interface The AT697 evaluation board includes all the required hardware to manage a RS232 communication. Hardware flow control (CTS & RTS) are not implemented on this Evaluation Kit Serial link 1 Serial link 1 is available on the board through the connector UART 1 accessible on the front panel (see Figure 2-3. Front panel overview). Table 2-6 UART 1 mapping Serial link name Function Processor connexion UART1_RX Serial link receive data PIO 14 UART1_TX Serial link transmit data PIO 15 UART1_RTS Request to Send frame N.C. UART1_CTS Clear to Send frame N.C. 18

19 2.8.2 Serial link 2 Serial link 2 is available through the expansion connector only and is only 3.3V tolerant. If serial link 2 is connected to a RS232 interface on an expansion board, a line driver (like MAX3232) has to be implemented to adapt voltage. 2.9 PCI interface The AT697 evaluation board implements a PCI interface capable to manage host and satellite configuration. The PCI interface has been designed to be integrated in compact PCI back plane. Universal keying is implemented. The board form factor fits with the 6U standard. The HOST/SATELLITE mode is automatically configured through position of the board on the PCI rack.. 19

20 2.10 Clock management Clock overview Figure AT697F Clock distribution Figure Development kit clock management AT697F CLK EXT 1 connector SKEW 0 configuration SKEW 1 configuration 25 MHz PLL configuration Clock configuration Clock interface PIO interface UART Control Reg. UACn PB Enter UART Clock configuration CLK EXT 2 connector SPP Connector Clock generator 33 MHz PCI interface UART interface RS232 serial link connector Legend: Configuration switch Connector 20

21 Internal clocks The Development kit embeds 2 internal clocks provided by one integrated circuit U4: The main processor clock (25 MHz), used if SW37.6 = OFF. The PCI clock (33 MHz) External clocks Two SMB male connectors are accessible from the front panel of the Evaluation Kit (see Figure 2-3. Front panel overview): Clock EXT IN 1: alternate processor clock, used if SW37.6 = ON. Clock EXT IN 2: alternate UART clock, used if SW37.8 = ON Processor clock configuration Configuration switches SW37 allow the user to manage processor clock configuration. Table 2-7 Clock configuration Name Switch number Function Processor pin BYPASS 2 OFF: PLL enable, master clock frequency is equal to 4x CLK frequency. ON: PLL disabled, master clock frequency is equal to CLK frequency. SKEW 0 3 OFF: SKEW0 disabled ON: SKEW0 enable SKEW 1 4 OFF: SKEW1 disabled ON: SKEW1 enable CLK 6 OFF: processor use on-board 25MHz clock ON: processor use Clock EXT IN 1 UART CLK 8 OFF: PIO3 is connected to Press Button ENTER ON: PIO3 is connected to Clock EXT IN / N / M / M / P15 63 / F4 21

22 2.11 Evaluation Kit Reset A test pad TP_BOARD_RESET shows the Reset signal state. A low level reset the board. Figure 2-16 Reset overview AT697F Reset configuration Watchdog Timers SPP Connector Alternate reset PWR_5V Reset button AND gates Reset PWR_3V3 Supply voltage supervisor PWR_1V8 Legend: Configuration switch Connector Hardware reset The hardware reset operation of the board is performed pushing the embedded RESET push button implanted on the front panel (see Figure 2-3. Front panel overview). A pressure on the RESET button leads to the reset of both the processor core and the PCI interface Alternate reset An alternate reset is available on the expansion connector. Please refer to the Expansion Connectors - section 2.15 for detailed information on expansion connector assignments Supply voltage supervisor An integrated circuit measures PWR_5V, PWR_3V3 and PWR_1V8 signals on the board. If these voltages are out of range (+/- 10% nominal value), the circuit reset the board or keep the board under reset (during a power on for example). 22

23 Space Programmer (SPP) reset It is possible to reset the processor by driving low PIN 9 (CTRL_GEN5) of the SPP connector. If nothing is connected to the SPP connector, an internal pull up drive high the line Watchdog reset By using SW37.5, it s possible to connect processor Watchdog pin WDOG (pin 168 / M17) to the reset module. Table 2-8 Watchdog configuration Name Switch number Function Processor pin Watchdog 5 OFF: connect WDOG pin to reset module ON: disconnect WDOG pin to reset module 168 / M Debug Support Unit Debug Support Unit (DSU) includes several parts: - A DSU connector to communicate - A DSUACT LED to indicate if the processor is in debug mode - A DSUBRE Press button to allow the user to put the processor in debug mode. The AT697 Debug Support Unit is based on a RS232 serial link connected to a host platform. The AT697 evaluation board includes all the required hardware to manage the RS232 communication and the debug facilities. The debug connector is available on front panel. It s named DSU connector. Figure DSU implementation DSUBRE press button DSUACT DEL DSU Connector 23

24 2.13 JTAG connector A 10-pin HE10 connector (J8) is provided on board to enable connection of the JTAG interface. The JTAC connector is available on the front panel. The following table gives the pinout of the JTAG connector. Table 2-9 JTAG pinout J8- JTAG connector pin number Signal name 1 JTAG TCK 2 GND 3 JTAG TDO 4 VCC3V3 5 JTAG TMS 6 JTAG TRST 7 VCC3V3 8 N.C. 9 VCC3V3 TDI 10 GND 2.14 Test Points Current measurement test points Current measurement test points are arranged according to the following drawing: Figure Current probe footprint 2.54mm 2.54mm 2.54mm GND A R shunt 0.01R B, C GND 24

25 Figure Power test points TP_I_1V8 TP_I_1V8_PLL TP_DEVICE_1V8 TP_BOARD _1V8 TP_ DEVICE _3V3 TP_BOARD_3V3 TP_BOARD_5V Clocks test points Figure Clock test points CLK ext 2 CLK ext 1 25 MHz 33 MHz Processor clock input SDCLK 25

26 System and CPCI test points Figure System and CPCI test points PCI clock PCI reset BEXC Processor error Board reset 26

27 2.15 Expansion connector Expansion connector manufacturer: SAMTEC Expansion connector reference: QTH L-D-A Table 2-10 Expansion connector J100 pinout Connector J100 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 CLK_EXT_2_IN 2 N.C. 61 PCI_AD29 62 PCI_AD HMI_LCD_BS1 122 N.C. 181 GND 3 CLK_EXT_1_IN 4 N.C. 63 PCI_AD28 64 PCI_AD HMI_LCD_RESET 124 N.C. 182 GND 5 CLK_ADJUST 6 N.C. 65 PCI_AD27 66 PCI_REQ 125 HMI_LCD_DNC_SCL 126 N.C. 183 GND 7 I2C_DATA 8 N.C. 67 PCI_AD26 68 PCI_GNT 127 HMI_LCD_NCS 128 N.C. 184 GND 9 I2C_SCL 10 N.C. 69 PCI_AD25 70 PCI_CBE0 129 HMI_LCD_SDA 130 N.C. 185 GND 11 CLK_GEN_CS 12 N.C. 71 PCI_AD24 72 PCI_CBE1 131 HMI_LCD_RD 132 N.C. 186 GND 13 CLK_20MHz 14 N.C. 73 PCI_AD23 74 PCI_CBE2 133 HMI_LCD_NWR_SCL 134 N.C. 187 GND 15 CLK_25MHz 16 N.C. 75 PCI_AD22 76 PCI_CBE3 135 HMI_LCD_D0 136 N.C. 188 GND 17 CLK_33MHz 18 N.C. 77 PCI_AD21 78 PCI_CLK 137 HMI_LCD_D1 138 N.C. 189 GND 19 CLK_50MHz 20 N.C. 79 PCI_AD20 80 PCI_RST 139 HMI_LCD_D2 140 N.C. 190 GND 21 N.C. 22 N.C. 81 PCI_AD19 82 PCI_SYSEN 141 HMI_LCD_D3 142 N.C. 191 GND 23 N.C. 24 N.C. 83 PCI_AD18 84 PCI_FRAME 143 HMI_LCD_D4 144 N.C. 192 GND 25 N.C. 26 N.C. 85 PCI_AD17 86 PCI_IRDY 145 HMI_LCD_D5 146 N.C. 193 N.C. 27 N.C. 28 N.C. 87 PCI_AD16 88 PCI_TRDY 147 HMI_LCD_D6 148 N.C. 194 N.C. 29 N.C. 30 N.C. 89 PCI_AD15 90 PCI_IDSEL 149 HMI_LCD_D7 150 N.C. 31 N.C. 32 N.C. 91 PCI_AD14 92 PCI_DEVSEL 151 N.C. 152 N.C. 33 N.C. 34 N.C. 93 PCI_AD13 94 PCI_PAR 153 HMI_LED_BOOT 154 N.C. 35 N.C. 36 N.C. 95 PCI_AD12 96 PCI_STOP 155 HMI_LED_FAIL 156 N.C. 37 N.C. 38 N.C. 97 PCI_AD11 98 PCI_LOCK 157 HMI_LED_RUN 158 N.C. 39 N.C. 40 N.C. 99 PCI_AD PCI_SERR N.C. 41 N.C. 42 N.C. 101 PCI_AD9 102 PCI_PERR N.C. 43 N.C. 44 N.C. 103 PCI_AD8 104 PCI_AREQ N.C. 45 N.C. 46 N.C. 105 PCI_AD7 106 PCI_AREQ N.C. 47 N.C. 48 N.C. 107 PCI_AD6 108 PCI_AREQ N.C. 49 N.C. 50 N.C. 109 PCI_AD5 110 PCI_AREQ N.C. 51 N.C. 52 N.C. 111 PCI_AD4 112 PCI_AGNT N.C. 53 N.C. 54 N.C. 113 PCI_AD3 114 PCI_AGNT N.C. 55 N.C. 56 N.C. 115 PCI_AD2 116 PCI_AGNT N.C. 57 N.C. 58 N.C. 117 PCI_AD1 118 PCI_AGNT N.C. 59 N.C. 60 N.C. 119 PCI_AD0 120 N.C N.C. 27

28 Table 2-11 Expansion connector J101 pinout Connector J101 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 BOARD_1V8 2 RESET 61 ROMS0 62 PIO A0 122 D0 181 GND 3 BOARD_1V8 4 CLK 63 ROMS1 64 PIO A1 124 D1 182 GND 5 BOARD_1V8 6 BYPASS 65 IOS 66 PIO A2 126 D2 183 GND 7 BOARD_1V8 8 LOCK 67 RAMS0 68 PIO A3 128 D3 184 GND 9 BOARD_1V8 10 SKEW0 69 RAMS1 70 PIO A4 130 D4 185 GND 11 BOARD_1V8 12 SKEW1 71 RAMS2 72 PIO A5 132 D5 186 GND 13 BOARD_3V3 14 ERROR 73 RAMS3 74 PIO9 133 A6 134 D6 187 GND 15 BOARD_3V3 16 WDOG 75 RAMS4 76 PIO8 135 A7 136 D7 188 GND 17 BOARD_3V3 18 TDO 77 WRITE 78 PIO7 137 A8 138 D8 189 GND 19 BOARD_3V3 20 TDI 79 READ 80 PIO6 139 A9 140 D9 190 GND 21 BOARD_3V3 22 TMS 81 OE 82 PIO5 141 A D GND 23 BOARD_3V3 24 TCK 83 RAMOE0 84 PIO4 143 A D GND 25 BOARD_3V3 26 TRST 85 RAMOE1 86 PIO3 145 A D N.C. 27 BOARD_5V 28 DSUEN 87 RAMOE2 88 PIO2 147 A D N.C. 29 BOARD_5V 30 DSURX 89 RAMOE3 90 PIO1 149 A D14 31 BOARD_5V 32 DSUTX 91 RAMOE4 92 PIO0 151 A D15 33 BOARD_5V 34 DSUACT 93 RWE0 94 HMI_LED0 153 A D16 35 BOARD_5V 36 DSUBRE 95 RWE1 96 HMI_LED1 155 A D17 37 BOARD_5V 38 TRST 97 RWE2 98 HMI_LED2 157 A D V 40 PROC_CLK_SEL 99 RWE3 100 HMI_LED A D V 42 PROM_WIDHT_SEL 101 SDCLK 102 BEXC 161 A D V 44 UART_CLK_SEL 103 SDRAS 104 BRDY 163 A D V 46 ALTERNATE_RESET 105 SDCAS 106 CB0 165 A D V SDWE 108 CB1 167 A D V 50 HMI_PB SDDQM0 110 CB2 169 A D24 51 HV 52 HMI_PB4 111 SDDQM1 112 CB3 171 A D25 53 HV 54 HMI_PB3 113 SDDQM2 114 CB4 173 A D26 55 HV 56 HMI_PB2 115 SDDQM3 116 CB5 175 A D27 57 HV 58 HMI_PB1 117 SDCS0 118 CB6 177 D D28 59 HV 60 HMI_PB0 119 SDCS1 120 CB7 179 D D29 28

29 2.16 Mechanical drawing Figure PCB mechanical drawing mm 29

30 Figure Front panel mechanical drawing Note: If more information is required, an AT697.brd file is available under request. This document can be sent to any customer requiring a global view of the board and requiring additional measurement constraints over the board. Such file can be read and analyzed with Allegro Free Physical Viewer, a free tool from Cadence Board History Table 2-12 Board history Version Comments AT697F Evaluation Kit V3.0.1 AT697F Evaluation Kit V3.0.2 First release. Change U23 to a TPS386040RGP Add manual fixes to have access to SRAM8 from the processor 30

31 3. Appendix A Getting Started The purpose of this section is to present how to start with the AT697 Evaluation board. It describes the AT697 development environment and the simple application examples. 3.1 AT697 Development Kit Content The following section describes the content of the AT697 development environment. Hardware AT697 Evaluation Board AT697F Processor One Power supply cable with 2.1mm Jack connector Two RS232 cables Software Gaisler Research RCC/BCC software packages GRMON 1 Professional version (under Gaisler Research License) Notes: 1. only for Development kit. Documentation AT697 Evaluation Kit User Manual AT697 datasheet and erratasheet BCC, RCC, and GRmon user manuals Application examples General demonstration PCI demonstration 31

32 3.2 Handling This Evaluation Kit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD). When handling or installing the Evaluation Kit observe appropriate precautions and ESD safe practices. When not in use, store the Evaluation Kit in an electrostatic protective container or bag. 3.3 System requirements The development software provided with the AT697 board/development kit is especially designed to run on Windows and Linux platforms. To run on Windows platforms, the Cygwin Unix emulation layer needs to be installed. Cygwin (or higher) is recommended on this platform. Under Linux platform, Linux-2.4.x with glibc-2.3 (or higher) is recommended. The minimum hardware requirements are: Pentium 1 Processor 128 MB RAM 100 MB Available Hard Disk Space Baud RS-232 Port (COM port) 3.4 Installing software development package Here is a summary of the tools provided with the AT697 evaluation board/development kit: RCC - Development suite BCC - Development suite GRMON - Debug monitor (only included in development kit) Installation procedure for each tool is specified in the corresponding User Guide. Please refer to the documents available with GRMON after installation for detailed information. 32

33 3.5 Hardware setup In order to quickly start working with the AT697, the Evaluation Kit is designed to allow application development and test with minimum hardware implication, except the board itself. Only a power supply source and a debug communication link are necessary to get a ready-to-work environment Default switches configuration: Refer to Table 2-1 for default switches configuration Power supply setup: Use the Jack connector to power the Evaluation Kit with a voltage comprised between 8V and 12V. Power supplies switches should be on Reg position to use onboard regulators Serial communication link: For application download and debug, you shall connect the serial interface of the board to the host monitor. With the AT697 Development kit, the GRmon debug monitor from Gaisler Research is available GRMON: GRMON requires a single RS232 communication link to enable load and debug of applications. Just connect the RS232 cable to the board DSU connector (P1) and to one of the host platform RS232 connector. The host platform running GRMON under Linux or Windows environment is then used to establish the communication with the AT697 processor. Figure 4-1. Host Connection 33

34 3.6 Run your first application Once GRmon and BCC/RCC are installed on your platform and your hardware in the default configuration, you are ready to start development session on the AT697 target. Following method is split in two parts: - A part for RAM application, called A - A part for ROM application, called B Step 1A: Compiling to RAM. The BCC/RCC development environment provides a full tool set for compiling and linking your application. You can compile and link your basic application with the following command: sparc-elf-gcc -g -O2 application.c -o application Step 1B: Compiling to ROM. In addition, you can create the ROM boot strap using sparc-elf-mkprom application -o rom_application Step 2: Hardware configuration. Connect the DSU connector of the Evaluation kit to the computer through a serial cable. In your Operating System hardware properties, find your Port COM Number (for example COM1). Use the default configuration switches (table 2-1) to use internal clock without PLL. The processor clock frequency is now 25 MHz. Power on the Evaluation Kit. Step 3: Connection to the Evaluation Kit. Open a terminal window on your host platform in order to run GRmon (refer to GRmon user manual for details). - under WINDOWS: "grmon -leon2 -uart COM1 -baud " - under LINUX: "grmon -leon2 -uart /dev/ttys0 -baud where the "-uart" and "-baud" flags are to be set according to your communication interface configuration. 34

35 Note: to connect the Evaluation Kit running at 100 MHz, follow the next procedure: Turn SW37.2 OFF to enable the PLL. Reset the Evaluation Kit. The processor clock frequency is now 100 MHz. Open a terminal window on your host in order to run GRmon: - under WINDOWS: "grmon -leon2 -uart COM1 -baud romws 15 -ramws 3" - under LINUX: "grmon -leon2 -uart /dev/ttys0 -baud romws 15 -ramws 3" where the "-uart" and "-baud" flags are to be set according to your communication interface configuration, and the -romws and -ramws flags are to be tuned with respect to the AT697F internal clock frequency. Other options can be added to the command line. Please refer to the GRmon user manual for more details. Once connected to the target, you can load the application to the on-board memory. 35

36 Step 4: Go to the right directory: Before loading a program to the target, you have to be on the directory where yours compiled files (.hex) are. - Use cd your_directory command to jump to the directory, - Use cd.. to jump to the parent directory. Step 5A: load to RAM: The executable can be loaded to RAM applying the following command: - load application Step 5B: load to ROM: The ROM boot strap can be loaded to the on board flash applying the following commands: - flash enable - flash erase all - flash load rom_application 36

37 Step 5A: execute code from RAM: To execute the loaded program, use run command. Step 5B: execute code from ROM: There are two ways to execute the code: - Use go 0 command under GRMON. - Or restart the Evaluation Kit. 37

38 4. Appendix B Schematics Please refer to the file in pdf format contained in the CD-ROM to see the Evaluation Kit schematic. 5. Revision History Doc. Rev. Date Comments 7540F 02/2013 Initial document release 7540G 12/2014 Add fixes for SRAM8 access problem 7540H 10/2015 Change comments when using CPCI rack power supply 38

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