Principles of Computer Architecture. Chapter 7: Memory
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1 7-1 Chapter 7 - Memory Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 7: Memory
2 7-2 Chapter 7 - Memory Chapter Contents 7.1 The Memory Hierarchy 7.2 Random Access Memory 7.3 Chip Organization 7.4 Commercial Memory Modules 7.5 Read-Only Memory 7.6 Cache Memory 7.7 Virtual Memory 7.8 Advanced Topics 7.9 Case Study: Rambus Memory 7.10 Case Study: The Intel Pentium Memory System
3 7-3 Chapter 7 - Memory The Memory Hierarchy
4 7-4 Chapter 7 - Memory Functional Behavior of a RAM Cell
5 7-5 Chapter 7 - Memory Simplified RAM Chip Pinout
6 7-6 Chapter 7 - Memory A Four-Word Memory with Four Bits per Word in a 2D Organization
7 7-7 Chapter 7 - Memory A Simplified Representation of the Four-Word by Four-Bit RAM
8 7-8 Chapter 7 - Memory 2-1/2D Organization of a 64-Word by One-Bit RAM
9 7-9 Chapter 7 - Memory Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAM
10 7-10 Chapter 7 - Memory Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM
11 7-11 Chapter 7 - Memory Single-In-Line Memory Module Adapted from(texas Instruments, MOS Memory: Commercial and Military Specifications Data Book, Texas Instruments, Literature Response Center, P.O. Box , Denver, Colorado, 1991.)
12 7-12 Chapter 7 - Memory A ROM Stores Four Four-Bit Words
13 7-13 Chapter 7 - Memory A Lookup Table (LUT) Implements an Eight-Bit ALU
14 7-14 Chapter 7 - Memory Placement of Cache in a Computer System The locality principle: a recently referenced memory location is likely to be referenced again (temporal locality); a neighbor of a recently referenced memory location is likely to be referenced (spatial locality).
15 7-15 Chapter 7 - Memory An Associative Mapping Scheme for a Cache Memory
16 7-16 Chapter 7 - Memory Associative Mapping Example Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, and the cache consists of 2 14 slots: If the addressed word is in the cache, it will be found in word (14) 16 of a slot that has tag (501AF80) 16, which is made up of the 27 most significant bits of the address. If the addressed word is not in the cache, then the block corresponding to tag field (501AF80) 16 is brought into an available slot in the cache from the main memory, and the memory reference is then satisfied from the cache.
17 7-17 Chapter 7 - Memory Replacement Policies When there are no available slots in which to place a block, a replacement policy is implemented. The replacement policy governs the choice of which slot is freed up for the new block. Replacement policies are used for associative and setassociative mapping schemes, and also for virtual memory. Least recently used (LRU) First-in/first-out (FIFO) Least frequently used (LFU) Random Optimal (used for analysis only look backward in time and reverse-engineer the best possible strategy for a particular sequence of memory references.)
18 7-18 Chapter 7 - Memory A Direct Mapping Scheme for Cache Memory
19 7-19 Chapter 7 - Memory Direct Mapping Example For a direct mapped cache, each main memory block can be mapped to only one slot, but each slot can receive more than one block. Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, and the cache consists of 2 14 slots: If the addressed word is in the cache, it will be found in word (14) 16 of slot (2F80) 16, which will have a tag of (1406) 16.
20 7-20 Chapter 7 - Memory A Set Associative Mapping Scheme for a Cache Memory
21 7-21 Chapter 7 - Memory Set-Associative Mapping Example Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, there are two blocks per set, and the cache consists of 2 14 slots: The leftmost 14 bits form the tag field, followed by 13 bits for the set field, followed by five bits for the word field:
22 7-22 Chapter 7 - Memory Cache Read and Write Policies
23 7-23 Chapter 7 - Memory Hit Ratios and Effective Access Times Hit ratio and effective access time for single level cache: Hit ratios and effective access time for multi-level cache:
24 7-24 Chapter 7 - Memory Direct Mapped Cache Example Compute hit ratio and effective access time for a program that executes from memory locations 48 to 95, and then loops 10 times from 15 to 31. The direct mapped cache has four 16- word slots, a hit time of 80 ns, and a miss time of 2500 ns. Loadthrough is used. The cache is initially empty.
25 7-25 Chapter 7 - Memory Table of Events for Example Program
26 7-26 Chapter 7 - Memory Calculation of Hit Ratio and Effective Access Time for Example Program
27 7-27 Chapter 7 - Memory Neat Little LRU Algorithm A sequence is shown for the Neat Little LRU Algorithm for a cache with four slots. Main memory blocks are accessed in the sequence: 0, 2, 3, 1, 5, 4.
28 7-28 Chapter 7 - Memory Overlays A partition graph for a program with a main routine and three subroutines:
29 7-29 Chapter 7 - Memory Virtual Memory Virtual memory is stored in a hard disk image. The physical memory holds a small number of virtual pages in physical page frames. A mapping between a virtual and a physical memory:
30 7-30 Chapter 7 - Memory Page Table The page table maps between virtual memory and physical memory.
31 7-31 Chapter 7 - Memory Using the Page Table A virtual address is translated into a physical address:
32 7-32 Chapter 7 - Memory Using the Page Table (cont ) The configuration of a page table changes as a program executes. Initially, the page table is empty. In the final configuration, four pages are in physical memory.
33 7-33 Chapter 7 - Memory Segmentation A segmented memory allows two users to share the same word processor code, with different data spaces:
34 7-34 Chapter 7 - Memory Fragmentation (a) Free area of memory after initialization; (b) after fragmentation; (c) after coalescing.
35 7-35 Chapter 7 - Memory Translation Lookaside Buffer An example TLB holds 8 entries for a system with 32 virtual pages and 16 page frames.
36 7-36 Chapter 7 - Memory 3-Variable Decoder A conventional decoder is not extensible to large sizes because each address line drives twice as many logic gates for each added address line.
37 7-37 Chapter 7 - Memory Tree Decoder - 3 Variables A tree decoder is more easily extended to large sizes because fan-in and fan-out are managed by adding deeper levels.
38 7-38 Chapter 7 - Memory Tree Decoding One Level at a Time A decoding tree for a 16-word random access memory:
39 7-39 Chapter 7 - Memory Content Addressable Memory Addressing Relationships between random access memory and content addressable memory:
40 7-40 Chapter 7 - Memory Overview of CAM Source: (Foster, C. C., Content Addressable Parallel Processors, Van Nostrand Reinhold Company, 1976.)
41 7-41 Chapter 7 - Memory Addressing Subtrees for a CAM
42 7-42 Chapter 7 - Memory Block Diagram of Dual-Read RAM
43 7-43 Chapter 7 - Memory Rambus Memory Rambus technology on the Nintendo 64 motherboard (top left and bottom right) enables cost savings over the conventional Sega Saturn motherboard design (bottom left). (Photo source: Rambus, Inc.)
44 7-44 Chapter 7 - Memory The Intel Pentium Memory System
CPSC 352. Chapter 7: Memory. Computer Organization. Principles of Computer Architecture by M. Murdocca and V. Heuring
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CSCI-UA.0201 Computer Systems Organization Memory Hierarchy Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com Programmer s Wish List Memory Private Infinitely large Infinitely fast Non-volatile
Physical characteristics (such as packaging, volatility, and erasability Organization.
CS 320 Ch 4 Cache Memory 1. The author list 8 classifications for memory systems; Location Capacity Unit of transfer Access method (there are four:sequential, Direct, Random, and Associative) Performance
Virtual Memory. Chapter 8
Virtual Memory 1 Chapter 8 Characteristics of Paging and Segmentation Memory references are dynamically translated into physical addresses at run time E.g., process may be swapped in and out of main memory
Memory Management Virtual Memory
Background; key issues Memory Management Virtual Memory Memory allocation schemes Virtual memory Memory management design and implementation issues 1 Remember Basic OS structures: intro in historical order
DAT (cont d) Assume a page size of 256 bytes. physical addresses. Note: Virtual address (page #) is not stored, but is used as an index into the table
Assume a page size of 256 bytes 5 Page table size (determined by size of program) 1 1 0 1 0 0200 00 420B 00 xxxxxx 1183 00 xxxxxx physical addresses Residency Bit (0 page frame is empty) Note: Virtual