NEXT SET OF SLIDES FROM DENNIS FREY S FALL 2011 CMSC313.

Transcription

1 NEXT SET OF SLIDES FROM DENNIS FREY S FALL 211 CMSC313

2 The Memory Hierarchy " Topics" Storage technologies and trends" Locality of reference" Caching in the memory hierarchy"

3 Random-Access Memory (RAM)" Key features" RAM is packaged as a chip." Basic storage unit is a cell (one bit per cell)." Multiple RAM chips form a memory." Static RAM (SRAM)" Each cell stores bit with a six-transistor circuit." Retains value indefinitely, as long as it is kept powered." Relatively insensitive to disturbances such as electrical noise." Faster and more expensive than DRAM." Dynamic RAM (DRAM)" Each cell stores bit with a capacitor and transistor." Value must be refreshed every 1-1 ms." Sensitive to disturbances." Slower and cheaper than SRAM." 2 " CMSC313-F 9"

4 Conventional DRAM Organization" d x w DRAM:" dw total bits organized as d supercells of size w bits" 16 x 8 DRAM chip" cols" " 1" 2" 3" (to CPU)" memory" controller" 2 bits" /" addr 8 bits" /" data " 1" rows" 2" 3" supercell" (2,1)" 3 " internal row buffer" CMSC313-F 9"

5 Reading DRAM Supercell (2,1)" Step 1(a): Row access strobe (RAS) selects row 2." Step 1(b): Row 2 copied from DRAM array to row buffer." 16 x 8 DRAM chip" memory" controller" RAS = 2 2" /" addr " 1" rows" 2" cols" " 1" 2" 3" 8" /" data 3" 4 " internal row buffer" CMSC313-F 9"

6 Reading DRAM Supercell (2,1)" Step 2(a): Column access strobe (CAS) selects column 1." Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU." 16 x 8 DRAM chip" To CPU" memory" controller" CAS = 1 2" /" addr " 1" rows" 2" cols" " 1" 2" 3" supercell " (2,1)" 8" /" data 3" supercell " 5 " internal row buffer" (2,1)" CMSC313-F 9"

7 Memory Modules" addr (row = i, col = j) DRAM 7" DRAM " : supercell (i,j)" 64 MB " memory module" consisting of" eight 8Mx8 DRAMs" bits" bits" 56-63" 48-55" bits" 4-47" bits" 32-39" bits" 24-31" bits" 16-23" bits" 8-15" bits" -7" 63" 56" 55" 48"47" 4" 39" 32" 31" 24"23" 16"15" 8" 7" " 64-bit doubleword at main memory address A! Memory" controller" 64-bit doubleword" 6 " CMSC313-F 9"

8 Nonvolatile Memories" DRAM and SRAM are volatile memories" Lose information if powered off." Nonvolatile memories retain value even if powered off." Generic name is read-only memory (ROM)." Misleading because some ROMs can be read and modified." Types of ROMs" Programmable ROM (PROM)" Eraseable programmable ROM (EPROM)" Electrically eraseable PROM (EEPROM)" Flash memory" Firmware" " Program stored in a ROM" Boot time code, BIOS (basic input/ouput system)" graphics cards, disk controllers." 7 " CMSC313-F 9"

9 Typical Bus Structure Connecting CPU and Memory" A bus is a collection of parallel wires that carry address, data, and control signals." Buses are typically shared by multiple devices." CPU chip" register file" ALU" system bus" memory bus" bus interface" I/O " bridge" main" memory" 8 " CMSC313-F 9"

10 Memory Read Transaction (1)" CPU places address A on the memory bus." %eax" register file" ALU" Load operation: movl A, %eax! " bus interface" I/O bridge" " " A! main memory" " x" A" 9 " CMSC313-F 9"

11 Memory Read Transaction (2)" Main memory reads A from the memory bus, retrieves word x, and places it on the bus." %eax" register file" ALU" Load operation: movl A, %eax! " I/O bridge" main memory" x! " bus interface" x" A" 1 " CMSC313-F 9"

12 Memory Read Transaction (3)" CPU reads word x from the bus and copies it into register %eax." %eax" register file" x" ALU" Load operation: movl A, %eax! " I/O bridge" main memory" " bus interface" x" A" 11 " CMSC313-F 9"

13 Memory Write Transaction (1)" CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive." %eax" register file" y" ALU" Store operation: movl %eax, A! " bus interface" I/O bridge" A! main memory" " A" 12 " CMSC313-F 9"

14 Memory Write Transaction (2)" CPU places data word y on the bus." %eax" register file" y" ALU" Store operation: movl %eax, A! " bus interface" I/O bridge" y! main memory" " A" 13 " CMSC313-F 9"

15 Memory Write Transaction (3)" Main memory reads data word y from the bus and stores it at address A." %eax" register file" y" ALU" Store operation: movl %eax, A! " I/O bridge" main memory" " bus interface" y" A" 14 " CMSC313-F 9"

16 Disk Geometry" Disks consist of platters, each with two surfaces." Each surface consists of concentric rings called tracks." Each track consists of sectors separated by gaps." tracks" surface" track k! gaps" spindle" sectors" 15 " CMSC313-F 9"

17 Disk Geometry (Muliple-Platter View)" Aligned tracks form a cylinder." cylinder k surface " surface 1" surface 2" surface 3" surface 4" surface 5" platter " platter 1" platter 2" spindle" 16 " CMSC313-F 9"

18 Disk Capacity" Capacity: maximum number of bits that can be stored." Vendors express capacity in units of gigabytes (GB), where 1 GB = 1^9 bytes. " Capacity is determined by these technology factors:" Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track." Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment." Areal density (bits/in 2 ): product of recording and track density." Modern disks partition tracks into disjoint subsets called recording zones "" Each track in a zone has the same number of sectors, determined by the circumference of innermost track." Each zone has a different number of sectors/track " " "" 17 " CMSC313-F 9"

19 Computing Disk Capacity" Capacity = "(# bytes/sector) x (avg. # sectors/track) x" " " "(# tracks/surface) x (# surfaces/platter) x" " " "(# platters/disk)" Example:" 512 bytes/sector" 3 sectors/track (on average)" 2, tracks/surface" 2 surfaces/platter" 5 platters/disk" Capacity = 512 x 3 x 2 x 2 x 5" " " = 3,72,," = 3.72 GB " 18 " CMSC313-F 9"

20 Disk Operation (Single-Platter View)" " The disk surface " spins at a fixed" rotational rate" The read/write head! is attached to the end" of the arm and flies over" the disk surface on" a thin cushion of air." spindle" spindle" spindle" spindle" By moving radially, the arm can position the read/write head over any track." 19 " CMSC313-F 9"

21 Disk Operation (Multi-Platter View)" " read/write heads " move in unison" from cylinder to cylinder" arm" spindle" 2 " CMSC313-F 9"

22 Disk Access Time" Average time to access some target sector approximated by :" T access = T avg seek + T avg rotation + T avg transfer " Seek time (T avg seek )" Time to position heads over cylinder containing target sector." Typical T avg seek = 9 ms" Rotational latency (T avg rotation )" Time waiting for first bit of target sector to pass under read/write head." T avg rotation = 1/2 x 1/RPMs x 6 sec/1 min" Transfer time (T avg transfer )"" Time to read the bits in the target sector." T avg transfer = 1/RPM x 1/(avg # sectors/track) x 6 secs/1 min." 21 " CMSC313-F 9"

23 Disk Access Time Example" Given:" Rotational rate = 7,2 RPM" Average seek time = 9 ms." Avg # sectors/track = 4." Derived:" Tavg rotation = 1/2 x (6 secs/72 RPM) x 1 ms/sec = 4 ms." Tavg transfer = 6/72 RPM x 1/4 secs/track x 1 ms/sec =.2 ms" Taccess = 9 ms + 4 ms +.2 ms" Important points:" Access time dominated by seek time and rotational latency." First bit in a sector is the most expensive, the rest are free." SRAM access time is about 4 ns/doubleword, DRAM about 6 ns" Disk is about 4, times slower than SRAM, " 2,5 times slower then DRAM." 22 " CMSC313-F 9"

24 Logical Disk Blocks" Modern disks present a simpler abstract view of the complex sector geometry:" The set of available sectors is modeled as a sequence of b- sized logical blocks (, 1, 2,...)" Mapping between logical blocks and actual (physical) sectors" Maintained by hardware/firmware device called disk controller." Converts requests for logical blocks into (surface,track,sector) triples." Allows controller to set aside spare cylinders for each zone." Accounts for the difference in formatted capacity and maximum capacity. " " 23 " CMSC313-F 9"

25 I/O Bus" CPU chip" register file" ALU" system bus" memory bus" bus interface" I/O " bridge" main" memory" USB" controller" graphics" adapter" I/O bus" disk " controller" Expansion slots for" other devices such" as network adapters." " mouse"keyboard" monitor" disk" 24 " CMSC313-F 9"

26 Reading a Disk Sector (1)" CPU chip" " register file" ALU" CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller." bus interface" main" memory" I/O bus" USB" controller" graphics" adapter" disk " controller" mouse"keyboard" monitor" disk" 25 " CMSC313-F 9"

27 Reading a Disk Sector (2)" CPU chip" register file" ALU" Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory." bus interface" main" memory" I/O bus" USB" controller" graphics" adapter" disk " controller" mouse"keyboard" monitor" disk" 26 " CMSC313-F 9"

28 Reading a Disk Sector (3)" CPU chip" register file" ALU" When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU)" bus interface" main" memory" I/O bus" USB" controller" graphics" adapter" disk " controller" mouse"keyboard" monitor" disk" 27 " CMSC313-F 9"

29 Locality" Principle of Locality:" Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves." Temporal locality: Recently referenced items are likely to be referenced in the near future." Spatial locality: Items with nearby addresses tend to be referenced close together in time." Locality Example:" Data" Reference array elements in succession (stride-1 reference pattern):" Spatial locality" Reference sum each iteration:" Temporal locality" Instructions" Reference instructions in sequence:" Spatial locality" Cycle through loop repeatedly: " Temporal locality" sum = ; for (i = ; i < n; i++) sum += a[i]; return sum; 28 " CMSC313-F 9"

30 Locality Example" Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer." " Question: Does this function have good locality?" int sumarrayrows(int a[m][n]) { int i, j, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum 29 " CMSC313-F 9"

31 Locality Example" Question: Does this function have good locality?" int sumarraycols(int a[m][n]) { int i, j, sum = ; } for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum 3 " CMSC313-F 9"

32 Locality Example" Question: Can you permute the loops so that the function scans the 3-d array a[] with a stride-1 reference pattern (and thus has good spatial locality)?" int sumarray3d(int a[m][n][n]) { int i, j, k, sum = ; } for (i = ; i < N; i++) for (j = ; j < N; j++) for (k = ; k < M; k++) sum += a[k][i][j]; return sum 31 " CMSC313-F 9"

33 Memory Hierarchies" Some fundamental and enduring properties of hardware and software:" Fast storage technologies cost more per byte and have less capacity. " The gap between CPU and main memory speed is widening." Well-written programs tend to exhibit good locality." These fundamental properties complement each other beautifully." " They suggest an approach for organizing memory and storage systems known as a memory hierarchy." 32 " CMSC313-F 9"

34 An Example Memory Hierarchy" Smaller," faster," and " costlier" (per byte)" storage " devices" L2:" L:" registers" L1:" on-chip L1" cache (SRAM)" off-chip L2" cache (SRAM)" CPU registers hold words retrieved from L1 cache." L1 cache holds cache lines retrieved from the L2 cache memory." L2 cache holds cache lines retrieved from main memory." Larger, " slower, " and " cheaper " (per byte)" storage" devices" L4:" L3:" main memory" (DRAM)" local secondary storage" (local disks)" Main memory holds disk " blocks retrieved from local " disks." Local disks hold files retrieved from disks on remote network servers." L5:" remote secondary storage" (distributed file systems, Web servers)" 33 " CMSC313-F 9"

35 Caches" Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device." Fundamental idea of a memory hierarchy:" For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1." Why do memory hierarchies work?" Programs tend to access the data at level k more often than they access the data at level k+1. " Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit." Net effect: A large pool of memory that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top." " 34 " CMSC313-F 9"

36 Caching in a Memory Hierarchy" Level k:" 4" 8" 9" 1" 14" 3" Smaller, faster, more expensive" device at level k caches a " subset of the blocks from level k+1" 1" 4" Data is copied between" levels in block-sized transfer units" Level k+1:" " 1" 2" 3" 4" 5" 6" 7" 8" 9" 1" 11" 12" 13" 14" 15" Larger, slower, cheaper storage" device at level k+1 is partitioned" into blocks." 35 " CMSC313-F 9"

37 General Caching Concepts" Level" k:" Level " k+1:" 14" 12" Request" 14" 12" " 1" 2" 3" 12" 4*" 9" 14" 3" 12" 4*" Request" 12" " 1" 2" 3" 4*" 4" 5" 6" 7" 8" 9" 1" 11" 12" 13" 14" 15" Program needs object d, which is stored in some block b." Cache hit" Program finds b in the cache at level k. E.g., block 14." Cache miss" b is not at level k, so level k cache must fetch it from level k+1. E.g., block 12." If level k cache is full, then some current block must be replaced (evicted). Which one is the victim? " Placement policy: where can the new block go? E.g., b mod 4" Replacement policy: which block should be evicted? E.g., LRU" 36 " CMSC313-F 9"

38 General Caching Concepts" Types of cache misses:" Cold (compulsary) miss" Cold misses occur because the cache is empty." Conflict miss" Most caches limit blocks at level k+1 to a small subset (sometimes a singleton) of the block positions at level k." E.g. Block i at level k+1 must be placed in block (i mod 4) at level k+1." Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block." E.g. Referencing blocks, 8,, 8,, 8,... would miss every time." Capacity miss" Occurs when the set of active cache blocks (working set) is larger than the cache." 37 " CMSC313-F 9"

39 Examples of Caching in the Hierarchy" Cache Type" What Cached" Where Cached" Latency (cycles)" Managed By" Registers" 4-byte word" CPU registers" " Compiler" TLB" L1 cache" L2 cache" Virtual Memory" Buffer cache" Address translations" 32-byte block" 32-byte block" 4-KB page" Parts of files" On-Chip TLB" On-Chip L1" Off-Chip L2" Main memory" Main memory" " 1" 1" 1" 1" Hardware" Hardware" Hardware" Hardware +OS" OS" Network buffer cache" Browser cache" Web cache" Parts of files" Web pages" Web pages" Local disk" Local disk" Remote server disks" 1,," 1,," 1,,," AFS/NFS client" Web browser" Web proxy server" 38 " CMSC313-F 9"

40 CMSC 313 Lecture 13 [draft] Virtual Memory UMBC, CMSC313, Richard Chang

41 Last Time Linux/gcc/i386 Function Call Convention Now we know where our C programs store their data, right??? int global ; int main() { int *ptr, n ; printf ("Address of main: %8x\n", &main ) ; printf ("Address of global variable: %8x\n", &global ) ; printf ("Address of local variable: %8x\n", &n ) ; } ptr = (int *) malloc(4) ; printf ("Address of allocated memory: %8x\n", ptr) ; UMBC, CMSC313, Richard Chang <chang@umbc.edu>

42 Linux Virtual Memory Space " Linux reserves 1 Gig memory in the virtual address space " The size of the Linux kernel significantly affects its performance (swapping is expensive) " Linux kernel can be customized by including only relevant modules "Designating kernel space facilitates protection of "The portion of disk used for paging is called the swap space 3 Gig 4 Gig 3 Gig 3 Gig 3 Gig Linux Kernel Task #2 Task #3... Task #n Paging System RAM Disk Mohamed Younis CMCS 313, Computer Organization and Assembly Language 7

43 7-3 Chapter 7: Memory The Memory Hierarchy Fast and expensive Registers Increasing performance and increasing cost Cache Main memory Secondary storage (disks) Off-line storage (tape) Slow and inexpensive Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

44 7-28 Overlays Chapter 7: Memory A partition graph for a program with a main routine and three subroutines: Compiled program Physical Memory Main Routine Main A Partition # Subroutine A Smaller than program C B Subroutine B Partition #1 Partition graph Subroutine C Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

45 7-34 Fragmentation Chapter 7: Memory (a) Free area of memory after initialization; (b) after fragmentation; (c) after coalescing. Operating System Free Area Operating System Program A Free Area Program B Free Area Program C Operating System Program A Free Area Program B Free Area Program C Free Area Free Area Free Area Dead Zone Dead Zone Dead Zone I/O Space I/O Space I/O Space (a) (b) (c) Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

46 Memory Protection Prevents one process from reading from or writing to memory used by another process Privacy in a multiple user environments Operating system stability Prevents user processes (applications) from altering memory used by the operating system One application crashing does not cause the entire OS to crash UMBC, CMSC313, Richard Chang <chang@umbc.edu>

47 7-29 Virtual Memory Chapter 7: Memory Virtual memory is stored in a hard disk image. The physical memory holds a small number of virtual pages in physical page frames. A mapping between a virtual and a physical memory: Virtual addresses Virtual memory Page Page 1 Physical memory Physical addresses Page 2 Page frame Page 3 Page frame Page 4 Page frame Page 5 Page frame Page Page 7 Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

48 7-3 Page Table Chapter 7: Memory The page table maps between virtual memory and physical memory. Present bit Page frame Page # Disk address Present bit: : Page is not in physical memory 1: Page is in physical memory Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

49 7-31 Chapter 7: Memory Using the Page Table A virtual address is translated into a physical address: Page Offset Virtual address Physical address Page table Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

50 7-32 Using the Page Table (cont ) The configuration of a page table changes as a program executes. Initially, the page table is empty. In the final configuration, four pages are in physical memory After fault on page #1 After fault on page # Chapter 7: Memory After fault on page #2 Final Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

51 Virtual Addressing Virtual address Virtual page number Page offset Translation Physical page number Page offset Physical address Page faults are costly and take millions of cycles to process (disks are slow) 8386 Page attributes: RW: read and write permission US: User mode or kernel mode only access PP: present bit to indicate where the page is Address of Page U S W R P P Mohamed Younis CMCS 313, Computer Organization and Assembly Language 9

52 Page Table Hardware supported Page table: Resides in main memory One entry per virtual page No tag is requires since it covers all virtual pages Point directly to physical page Table can be very large Operating sys. may maintain one page table per process A dirty bit is used to track modified pages for copy back Indicates whether the virtual page is in main memory or not Page table Valid If then page is not present in memory Page table register Virtual page number Virtual address Physical page number Physical page number Physical address Page offset Page offset Mohamed Younis CMCS 313, Computer Organization and Assembly Language 1

53 Linux 2-Level Page Table CR3 register Page Table Table 124 Page Tables pages pages pages "The CR3 register is designated for pointing to the first level page table "The CR3 is part of the task state that needs to be saved at preemption Index into Page Table Table Index into Page Table Index into Page Mohamed Younis CMCS 313, Computer Organization and Assembly Language 11

54 Linear Address Translation (4-KByte Pages) Figure 3-12 shows the page directory and page-table hierarchy when mapping linear addresses to 4-KByte pages. The entries in the page directory point to page tables, and the entries in a page table point to pages in physical memory. This paging method can be used to address up to 2 2 pages, which spans a linear address space of 2 32 bytes (4 GBytes). Linear Address Directory Table Offset 12 4-KByte Page 1 Page Directory 1 Page Table Physical Address Directory Entry Page-Table Entry 2 32* CR3 (PDBR) 124 PDE * 124 PTE = 2 2 Pages *32 bits aligned onto a 4-KByte boundary. Figure Linear Address Translation (4-KByte Pages)

55 31 Page-Directory Entry (4-KByte Page Table) Page-Table Base Address Avail G P S A P C D P W T U / S R / W P Available for system programmer s use Global page (Ignored) Page size ( indicates 4 KBytes) Reserved (set to ) Accessed Cache disabled Write-through User/Supervisor Read/Write Present 31 Page-Table Entry (4-KByte Page) Page Base Address Avail P G A T P D A C D P W T U / S R / W P Available for system programmer s use Global Page Page Table Attribute Index Dirty Accessed Cache Disabled Write-Through User/Supervisor Read/Write Present Figure Format of Page-Directory and Page-Table Entries for 4-KByte Pages and 32-Bit Physical Addresses

56 7-33 Chapter 7: Memory Segmentation A segmented memory allows two users to share the same word processor code, with different data spaces: Segment # Execute only Segment #1 Read/write by user # Segment #2 Read/write by user #1 Used Used Free Used Free Unused Address space for code segment of word processor Data space for user # Data space for user #1 Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

57 7-35 Chapter 7: Memory Translation Lookaside Buffer An example TLB holds 8 entries for a system with 32 virtual pages and 16 page frames. Valid Virtual page number Physical page number Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring

58 Virtual Memory: Problems Solved Not enough physical memory Uses disk space to simulate extra memory Pages not being used can be swapped out (how and when you ll learn in CMSC 421 Operating Systems) Thrashing: pages constantly written to and retrieved from disk (time to buy more RAM) Fragmentation Contiguous blocks of virtual memory do not have to map to contiguous sections of real memory Memory protection Each process has its own page table Shared pages are read-only User processes cannot alter the page table (must be supervisor) UMBC, CMSC313, Richard Chang

59 Virtual Memory: too slow? Address translation is done in hardware In the middle of the fetch execute cycle for: MOV EAX, [buffer] the physical address of buffer is computed in hardware. Recently computed page locations are cached in the translation lookaside buffer (TLB) Page faults are very expensive (millions of cycles) Operating systems for personal computers have only recently added memory protection UMBC, CMSC313, Richard Chang