Chap. 12 Memory Organization

Transcription

1 Memory Hierarchy Memory hierarchy in a computer system : Fig Main Memory : memory unit that communicates directly with the CPU (RAM) Auxiliary Memory : device that provide backup storage (Disk Drives) Cache Memory : special very-high-speed memory to increase the processing speed (Cache RAM) Auxiliary memory Magnetic tapes Magnetic disks I/O processor Main memory CPU Cache memory Multiprogramming enable the CPU to process a number of independent program concurrently Memory Management System : sec supervise the flow of information between auxiliary memory and main memory

2 Main Memory Bootstrap Loader A program whose function is to start the computer software operating when power is turned on Power-ON RAM and ROM Chips FFFF: Typical RAM chip : Fig (Reset Point)» 128 X 8 RAM : 2 7 = 128 (7 bit address lines) POST Typical ROM chip : Fig System Init.» 512 X 8 ROM : 2 9 = 512 (9 bit address lines) Chip select 1 Chip select 2 Read Write 7 bit address CS1 CS2 RD WR AD RAM 8 bit data bus INT 19 Load Bootstrap Record (Track, Sector ) Load Operating System (IO.SYS, MSDOS.SYS, COMMAND.COM) Bootstrap Loader Bootstrap ROM Boot ROM (a) Block diagram Chip select 1 CS1 CS1 CS2 RD WR Memory function State of data bus Inhibit Inhibit Inhibit Write Read Inhibit High-impedance High-impedance High-impedance Input data to RAM Output data from RAM High-impedance Chip select 2 9 bit address CS2 AD ROM 8 bit data bus (b) Function table

3 12-3 Memory Address Map Address bus CPU Memory Configuration : RD WR Data bus» 512 bytes RAM bytes ROM» 1 x 512 byte ROM + 4 x 128 bytes RAM Decoder CS1 Memory Address Map : Tab. 12-1» Address line 9 8 RAM 1 : - 7F CS2 RD WR AD RAM 1 Data RAM 1 1 : 8 - FF RAM 1 1 : 1-17F RAM : 18-1FF CS1 CS2 RD WR RAM 2 Data» Address line 1 AD7 ROM 1 : 2-3FF CS1 Memory Connection to CPU : Fig. 12-4» 2 x 4 Decoder : RAM select (CS1)» Address line 1» 참고 RAM select : CS2 ROM select : CS2 의 Invert CS2 RD WR AD7 CS1 CS2 RD WR AD RAM RAM 4 Data Data RD : ROM 의 CS1 은보통 OE(Output Enable) 로사용 CS1 CS ROM AD9 Data

4 Auxiliary Memory Tracks Magnetic Disk : Fig. 12-5, FDD, HDD Magnetic Tape : Backup or Program 저장 Sector Optical Disk : CDR, ODD, DVD 12-4 Associative Memory Content Addressable Memory (CAM) A memory unit accessed by content Block Diagram : Fig text Argument register (A) Read/Write head 성명 학번 Key register (K) A Register K Register 111 Argument Key (Mask) Match register Memory 내용 Input Word M = Word M = 1 Match Logic Read Write Associative memory array and logic m words n bits per word M M = 1 일때출력 Output

5 12-5 m word x n cells per word : Fig Input A i K j A 1 A j A n Write K 1 K j K n Word 1 C 11 C 1j C 1n M1 Read R S F ij Match logic To M i Word i C i1 C ij C in M i Word m Cm1 C mj Cmn Mm Bit 1 Bit j Bit n Output Match Logic One cell of associative memory : Fig. 12-8» Input = 1 or 에따라Write 신호와동시에 F/F에저장» A 와 K 에의해Match Logic 에서 M=1 이면 (M을 READ에직접연결가능함 )» Read 신호에따라 F/F에서데이터를읽는다

6 12-6 Match Logic : Fig. 12-9» A j = Argument, F ij = Cell ij 번째 bit» j 번째 1 bit match 조건 x j = A j F ij (1 AND 1)+ A j F ij ( AND ) K 1 F' i1 F i1 A 1 K 2 F' i2 F i2 A 2 K n F' in F in A n» 1 - n 까지 n bits match 조건 M i = x 1 x 2..x n» Key bit K j : x j + K j K j = : A j 와 F ij 는 no comparison ( K j : x j + 1 = 1 ) K j = 1 : A j 와 F ij 는 comparison ( K j : x j + = x j )» Match Logic for word I : M i = (x 1 + K 1 ) (x 2 + K 2 ). (x n + K n ) n = (x j + K j ) j = 1 n = (A j F ij + A j F ij + K j ) j = 1 M i

7 Cache Memory Locality of Reference the references to memory tend to be confined within a few localized areas in memory Cache Memory : a fast small memory keeping the most frequently accessed instructions and data in the fast cache memory Cache 의설계요소 cache size : 보통 256 K byte ( 최대 512 K byte) mapping method : 1) associative, 2) direct, 3) set-associative replace algorithm : 1) LRU, 2) LFU, 3) FIFO write policy : 1) write-through, 2) write-back Hit Ratio the ratio of the number of hits divided by the total CPU references (hits + misses) to memory» hit : the CPU finds the word in the cache ( 보통.9 이상 )» miss : the word is not found in cache (CPU must read main memory) 총 1 회 Memory 참조 예제 : cache memory access time = 1 ns, main memory access time = 1 ns, hit ratio =.9» 1 회 miss : 1 x 1 ns 19 ns / 1 회 = 19 ns» 9 회 hit : 9 x 1 ns Cache 가없으면 1 ns, 따라서약 5 배성능향상

8 12-8 Mapping The transformation of data from main memory to cache memory» 1) Associative mapping» 2) Direct mapping» 3) Set-associative mapping Example of cache memory : Fig main memory : 32 K x 12 bit word (15 bit address lines) cache memory : 512 x 12 bit word» CPU sends a 15-bit address to cache Hit : CPU accepts the 12-bit data from cache Main memory 32K 12 Miss : CPU reads the data from main memory (then data is written to cache) Cache memory CPU Associative mapping : Fig Cache memory 로고가의 associative memory 사용 Address 와 Data 가직접 Cache memory 에사용됨 Cache Coherence (Sec. 13-5) CPU address(15 bits) Argument register Direct mapping : Fig Cache memory 로저가의일반 memory 사용 Tag field (n - k) 와 Index field (k) 를사용» 2 k words cache memory + 2 n words main memory Tag = 6 bit (15-9), Index = 9 bit Address Data

9 bits 9 bits Tag Index Tag (6 bit) - 63 Index (9 bit) Hex Address 3F 1FF 32K 12 Main memory Address = 15 bits Data = 12 bits Octal address 1FF Cache memory Address = 9 bits Data = 12 bits Direct mapping cache organization : Fig Memory address Memory data Index address Tag Data 1 2 2» 예제 : 2 번지를읽는경우 1) 우선 Index 을 cache 에서찾는다 2) 다음은 Tag 를 cache 에서비교한다 ) Index에있는cache tag는 이다 (2가아니다 ) 4) 따라서 miss 5) 그러므로 main memory에서 data read (address 2 = 567 read) (b) Cache memory (a) Main memory

10 12-1 Direct mapping cache with block size of 8 words : Fig » 64 block x 8 word = 512 cache words size 8 word 를 1 개의 block 단위로 update Block Index Tag Data Tag Block Word Index Index Tag Data Tag Data Block 1 17 Block Set-associative mapping : Fig (two-way) Direct mapping ( Fig (b)) 에서같은 Index 에다른 tag 를자주읽으면속도가저하됨 ( 예제 2777, 1777 ) 따라서 set 의개수를증가시키면속도가향상된다.

11 12-11 Replacement Algorithm : cache miss or full 일때 1) LRU (Least Recently Used) : 최근에가장적게사용된 block 교체 2) LFU (Least Frequently Used) : 사용빈도가가장적은 block 교체 3) FIFO (First-In First-Out) : 가장오래된 block 교체 Writing to Cache : Cache Coherence(Sec. 13-5) Cache 에있는내용이변경된 (WRITE) 경우, Cache 의 block 이교체되기전에 main memory 에내용도 update 해야함» 1) Write-through : Cache write 와동시에 main memory도항상동시에 write 한다.» 2) Write-back : Cache write 시에내용이변경되었다는 flag 만 set해놓고나중에 block이교체되기전에 flag를검사하여변경된부분만나중에 write 한다. Cache Initialization 따라서 Write-back 방식은 main memory 가무효한상태에빠져있을수있다. Cache is initialized : 이때 cache 는 empty 상태이고 invalid data 를갖을수있다.» 1) when power is applied to the computer» 2) when main memory is loaded with a complete set of programs from auxiliary memory valid bit» indicate whether or not the word contains valid data Cache READ 는문제없음 Main memory 와 Cache memory 의내용이동일해야함 : 통일성 ( 일관성 ) 유지

12 Virtual Memory Virtual Memory : Auxiliary memory Main memory Translate program-generated (Aux. Memory) address into main memory location» Give programmers the illusion that they have a very large memory, even though the computer actually has a relatively small main memory 예제 : Intel Pentium Processor» Physical Address Lines = A -A 31 : 2 32 = 2 3 X 2 2 = 4 Giga» Logical Address = 46 bits address : 2 46 = 2 4 X 2 6 = 64 Tera Address Space & Memory Space Address Space : Virtual Address» Address used by a programmer Memory Space : Physical Address(Location)» Address in main memory 예제 : Fig address space (N) = 124 K = 2 2» Auxiliary Memory memory space (M) = 32 K = 2 15» main Memory Auxiliary memory Program 1 Data 1,1 Data 1,2 Program 2 Data 2,1 Address space N = 124K = 2 2 Main memory Program 1 Data 1,1 Memory space M = 32K = 2 15

13 12-13 Memory table for mapping a virtual address : Fig Translate the 2 bits Virtual address into the 15 bits Physical address Virtual address Virtual address register (2 bits) Memory maping table Main memory address register (15 bits) Main memory Memory table buffer register Main memory buffer register Address Mapping Using Pages : Fig Address mapping 을간단하게하기위하여사용» Address space와 memory space를 fixed size로분할하여사용함 Address space : 1 K page 로분할 Memory space : 1 k block으로분할» Address space의 4 개 page가 memory space에 block에들어갈수있다. Page Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Block Block 1 Block 2 Block 3 Address space Memory space N = 8K = 2 13 M = 4K = 2 12

14 12-14 Memory table in a paged system : Fig Virtual address Memory address Page no. Line number Virtual address Table address Presence bit Main memory address register Main memory Block Block 1 Block 2 Block 3 MBR 1 1 Memory page table

15 12-15 Associative memory page table : Fig Associative memory를이용하여 block number(1) 를곧바로찾는다 Virtual memory Page no. 1 1 Line number Argument register Key register Associative memory Page no. Block no. Page(Block) Replacement Page Fault : the page referenced by the CPU is not in main memory» a new page should be transferred from auxiliary memory to main memory Replacement algorithm : FIFO 와 LRU 주로사용

16 Memory Management Hardware Basic components of a Memory Management Unit 1) Address mapping 2) Common program sharing 3) Program protection MMU : OS 에서지원해야함 1) CPU 에내장된형태, 2) 별도의 memory controller 형태 Segment : CS, DS, SS A set of logically related instruction or data elements associated with a given name View memory as a collection of variable-sized segments, and Eliminate internal fragmentation 예제 : a subroutine, an array of data, a table of symbol, user s program, stack Logical Address the address generated by a segmented program similar to virtual address» Virtual Address : fixed-length page» Logical Address : variable-length segment segment Length Base address

17 12-17 Segments to Pages Mapping a. Large segment paging b. Small segment paging Multi-segment Model page Segment Boundary Page Boundary

18 12-18 Segmented-page MMU refer to the slide #19 Fig (a) : 2 개의 table(segment, page) 을사용함» 따라서 2 개의 table 을읽는데많은시간이소모됨 Fig (b) : Associative memory 를이용한 1 개의 table 을사용함» 따라서속도가빠르다» TLB (Translation Look-a-side Buffer) Numerical Example associative memory 를이용한 most recently reference table 예제 : Logical address & Physical address (Fig )» Logical Address : 4 bit segment : 16 segments 8 bit page : 256 pages 8 bit word : 256 address field» Physical Address : 12 bit block : 496 blocks 8 bit word : 256 address field Segment Page Word (a) Logical address format : 16 segments of 256 pages each, each page has 256 words Address or Index Block Word Physical memory (b) Physical address format : 496 blocks of 256 word each, each word has 32 bits Fig An example of logical and physical address

19 12-19 예제 : Logical & Physical address assignment (Fig , 12-24) Segment Logical Address Hexadecimal address 6 6 FF FF FF FF FF Fig Example of logical and physical memory address assignment Page number Page Page 1 Page 2 Page 3 Page 4 Page Table Segment Page Block A61 Page Word (a) Logical address assignment (b) Segment-page versus memory block assignment Block number 19 를찾는다

20 12-2 Logical address (in haxadecimal) 6 2 7E Segment table Page table FF Physical memory Block FF Block 12 F A3 39 A61 A E 19 FF 32 bit word (a) Segment and page table mapping + Word Segment Page Block A61 + Word = 7E (b) Associative memory (TLB) Fig Mapping in segmented-page memory management unit. Fig Logical to physical memory mapping example

21 12-21 Memory Protection Typical segment descriptor : Fig Base address Length Protection Intel segment descriptor format : DPL(Descriptor Privilege Level) Access Rights : protecting the programs residing in memory» 1) Full read and write privileges : no protection» 2) Read only : write protection» 3) Execute only : program protection» 4) System only : operating system protection