Z86E30/E31/E40 1 Z8 4K OTP MICROCONTROLLER

Transcription

1 PRELIMINARY PRODCT SPECIFICATION Z86E3/E3/E4 Z8 4K OTP MICROCONTROLLER FEATRES Device ROM (KB) Standard Temperature ( CC = 3.5 to ) Extended Temperature ( CC = 4.5 to ) Available Packages: 28-Pin DIP/SOIC/PLCC OTP (Z86E3/3 only) 4-Pin DIP OTP (Z86E4 only) 44-Pin PLCC/QFP OTP (Z86E4 only) Software Enabled Watch-Dog Timer (WDT) Push-Pull/Open-Drain Programmable on Port, Port, and Port 2 24/32 Input/Output Lines Auto Latches RAM* (Bytes) Auto Power-On Reset (POR) I/O Lines Speed (MHz) Z86E Z86E Z86E Note: *General-Purpose Programmable OTP Optio: RC Oscillator EPROM Protect Auto Latch Disable Permanently Enabled WDT Crystal Oscillator Feedback Resistor Disable RAM Protect Low-Power Coumption: 6 mw Fast Itruction Pointer:.75 µs Two Standby Modes: STOP and HALT Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler Six ectored, Priority Interrupts from Six Different Sources Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive GENERAL DESCRIPTION The Z86E3/E3/E4 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip Z8 MC family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI optio, and easy hardware/software system expaion capability. Four basic address spaces support a wide range of memory configuratio. The designer has access to three additional control registers that allow easy access to register mapped peripheral and I/O circuits. For applicatio demanding powerful I/O capabilities, the Z86E3/E3 have 24 pi, and the Z86E4 has 32 pi of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All signals with a preceding front slash, /, are active Low. For example, B/W (WORD is active Low); B/W (BYTE is active Low, only). DS97Z8X52 P R E L I M I N A R Y

2 Z86E3/E3/E4 Zilog Power connectio follow conventional descriptio below: Connection Circuit Device Power CC DD Ground GND SS (E4 Only) Output Input CC GND XTAL AS DS R/W RESET Port 3 Counter/ Timers (2) AL Machine Timing & Itruction Control RESET WDT, POR Interrupt Control Two Analog Comparators FLAGS Register Pointer Register File OTP Program Counter Port 2 Port Port I/O (Bit Programmable) Address or I/O (Nibble Programmable) Address/Data or I/O (Byte Programmable) (E4 Only) Figure. Z86E3/E3/E4 Functional Block Diagram 2 P R E L I M I N A R Y DS97Z8X52

3 Zilog Z86E3/E3/E4 D7 - Z8 MC AD - AD - MSN Port 3 Address MX AD - EPROM D7 - Data MX Z8 Port TEST ROM OTP Optio D7 - Z8 Port 2 PGM + Test Mode Logic PP P33 EPM P32 CE XT PGM P3 OE P3 Figure 2. EPROM Programming Block Diagram DS97Z8X52 P R E L I M I N A R Y 3

4 Z86E3/E3/E4 PIN IDENTIFICATION R/W P25 P26 P27 P4 P5 P6 P4 P5 P7 CC P6 P7 XTAL2 XTAL P3 P32 P33 P34 AS 4-Pin DIP DS P24 P23 P22 P2 P2 P3 P3 P2 GND P2 P P P P P3 P36 P37 P35 RESET Figure 3. 4-Pin DIP Pin Configuration Standard Mode Table. 4-Pin DIP Pin Identification Standard Mode Zilog Pin # Symbol Function Direction R/W Read/Write Output 2 4 P25 P27 Port 2, Pi 5,6,7 In/Output 5 7 P4 P6 Port, Pi 4,5,6 In/Output 8 9 P4 P5 Port, Pi 4,5 In/Output P7 Port, Pin 7 In/Output CC Power Supply 2 3 P6 P7 Port, Pi 6,7 In/Output 4 XTAL2 Crystal Oscillator Output 5 XTAL Crystal Oscillator Input 6 8 P3 P33 Port 3, Pi,2,3 Input 9 P34 Port 3, Pin 4 Output 2 AS Address Strobe Output 2 RESET Reset Input 22 P35 Port 3, Pin 5 Output 23 P37 Port 3, Pin 7 Output 24 P36 Port 3, Pin 6 Output 25 P3 Port 3, Pin Input P P Port, Pi, In/Output P P Port, Pi, In/Output 3 P2 Port, Pin 2 In/Output 3 GND Ground P2 P3 Port, Pi 2,3 In/Output 34 P3 Port, Pin 3 In/Output P2 P24 Port 2, Pi,,2,3,4 In/Output 4 DS Data Strobe Output 4 P R E L I M I N A R Y DS97Z8X52

5 Zilog Z86E3/E3/E4 P2 P3 P3 P2 GND GND P2 P P P P P2 P22 P23 P24 DS R/W P25 P26 P27 P Pin PLCC P3 P36 P37 P35 RESET R/RL AS P34 P33 P32 P3 P5 P6 P4 P5 P7 CC CC P6 P7 XTAL2 XTAL Figure Pin PLCC Pin Configuration Standard Mode Table Pin PLCC Pin Identification Pin # Symbol Function Direction 2 GND Ground 3 4 P2 P3 Port, Pi 2,3 In/Output 5 P3 Port, Pin 3 In/Output 6 P2 P24 Port 2, Pi,,2,3,4 In/Output DS Data Strobe Output 2 No Connection 3 R/W Read/Write Output 4 6 P25 P27 Port 2, Pi 5,6,7 In/Output 7 9 P4 P6 Port, Pi 4,5,6 In/Output 2 2 P4 P5 Port, Pi 4,5 In/Output 22 P7 Port, Pin 7 In/Output CC Power Supply P6 P7 Port, Pi 6,7 In/Output 27 XTAL2 Crystal Oscillator Output 28 XTAL Crystal Oscillator Input 29 3 P3 P33 Port 3, Pi,2,3 Input 32 P34 Port 3, Pin 4 Output Table Pin PLCC Pin Identification Pin # Symbol Function Direction 33 AS Address Strobe Output 34 R/RL ROM/ROMless select Input 35 RESET Reset Input 36 P35 Port 3, Pin 5 Output 37 P37 Port 3, Pin 7 Output 38 P36 Port 3, Pin 6 Output 39 P3 Port 3, Pin Input 4 4 P P Port, Pi, In/Output P P Port, Pi, In/Output 44 P2 Port, Pin 2 In/Output DS97Z8X52 P R E L I M I N A R Y 5

6 Z86E3/E3/E4 Zilog PIN IDENTIFICATION (Continued) P2 P22 P23 P24 DS R/W P25 P26 P27 P P3 P36 P37 P35 RESET R/RL AS P34 P33 P32 P3 P5 P6 P4 P5 P7 CC CC P6 P7 XTAL2 XTAL P2 P3 P3 P2 GND GND P2 P P P P 44-Pin QFP Figure Pin QFP Pin Configuration Standard Mode Table Pin QFP Pin Identification Pin # Symbol Function Direction 2 P5 P6 Port, Pi 5,6 In/Output 3 4 P4 P5 Port, Pi 4,5 In/Output 5 P7 Port, Pin 7 In/Output 6 7 CC Power Supply 8 9 P6 P7 Port, Pi 6,7 In/Output XTAL2 Crystal Oscillator Output XTAL Crystal Oscillator Input 2 4 P3 P33 Port 3, Pi,2,3 Input 5 P34 Port 3, Pin 4 Output 6 AS Address Strobe Output 7 R/RL ROM/ROMless select Input 8 RESET Reset Input 9 P35 Port 3, Pin 5 Output 2 P37 Port 3, Pin 7 Output 2 P36 Port 3, Pin 6 Output 22 P3 Port 3, Pin Input P P Port, Pin, In/Output P P Port, Pi, In/Output Table Pin QFP Pin Identification Pin # Symbol Function Direction 27 P2 Port, Pin 2 In/Output GND Ground 3 3 P2 P3 Port, Pi 2,3 In/Output 32 P3 Port, Pin 3 In/Output P2 4 Port 2, Pi,,2,3,4 In/Output 38 DS Data Strobe Output 39 No Connection 4 R/W Read/Write Output 4 43 P25 P27 Port 2, Pi 5,6,7 In/Output 44 P4 Port, Pin 4 In/Output 6 P R E L I M I N A R Y DS97Z8X52

7 Zilog Z86E3/E3/E4 D5 D6 D7 A4 A5 A6 A7 CC CE OE EPM PP A8 4-Pin DIP D4 D3 D2 D D A3 GND A2 A A PGM A A A9 Figure 6. 4-Pin DIP Pin Configuration EPROM Mode Table 4. 4-Pin DIP Package Pin Identification EPROM Mode Pin # Symbol Function Direction No Connection 2 4 D5 D7 Data 5,6,7 In/Output 5 7 A4 A6 Address 4,5,6 Input 8 9 No Connection A7 Address 7 Input CC Power Supply 2 4 No Connection 5 CE Chip Select Input 6 OE Output Enable Input 7 EPM EPROM Prog. Mode Input 8 PP Prog. oltage Input 9 A8 Address 8 Input 2 2 No Connection 22 A9 Address 9 Input 23 A Address Input 24 A Address Input 25 PGM Prog. Mode Input A A Address, Input No Connection 3 A2 Address 2 Input 3 GND Ground No Connection 34 A3 Address 3 Input D D4 Data,,2,3,4 In/Output 4 No Connection DS97Z8X52 P R E L I M I N A R Y 7

8 Z86E3/E3/E4 Zilog PIN IDENTIFICATION (Continued) D D2 D3 D4 D5 D6 D7 A Pin PLCC PGM A A A9 A8 PP EPM OE A5 A6 A7 CC CC CE D A3 GND GND A2 A A Figure Pin PLCC Pin Configuration EPROM Programming Mode Table Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function Direction 2 GND Ground 3 4 No Connection 5 A3 Address 3 Input 6 D D4 Data,,2,3,4 In/Output 3 No Connection 4 6 D5 D7 Data 5,6,7 In/Output 7 9 A4 A6 Address 4,5,6 Input 2 2 No Connection 22 A7 Address 7 Input CC Power Supply No Connection 28 CE Chip Select Input 29 OE Output Enable Input 3 EPM EPROM Prog. Mode Input Table Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function Direction 3 PP Prog. oltage Input 32 A8 Address 8 Input No Connection 36 A9 Address 9 Input 37 A Address Input 38 A Address Input 39 PGM Prog. Mode Input 4 4 A,A Address, Input No Connection 44 A2 Address 2 Input 8 P R E L I M I N A R Y DS97Z8X52

9 Zilog Z86E3/E3/E4 D A3 GND GND A2 A A D D2 D3 D4 D5 D6 D7 A PGM A A A9 A8 PP EPM OE A5 A6 A7 CC CC CE 44 -Pin QFP Figure Pin QFP Pin Configuration EPROM Programming Mode Table Pin QFP Pin Identification EPROM Programming Mode Pin # Symbol Function Direction 2 A5 A6 Address 5,6 Input 3 4 No Connection 5 A7 Address 7 Input 6 7 CC Power Supply 8 No Connection CE Chip Select Input 2 OE Output Enable Input 3 EPM EPROM Prog. Input Mode 4 PP Prog. oltage Input 5 A8 Address 8 Input 6 8 No Connection 9 A9 Address 9 Input 2 A Address Input 2 A Address Input 22 PGM Prog. Mode Input Table Pin QFP Pin Identification EPROM Programming Mode Pin # Symbol Function Direction A,A Address, Input No Connection 27 A2 Address 2 Input GND Ground 3 3 No Connection 32 A3 Address 3 Input D D4 Data,,2,3,4 In/Output 38 4 No Connection 4 43 D5 D7 Data 5,6,7 In/Output 44 A4 Address 4 Input DS97Z8X52 P R E L I M I N A R Y 9

10 Z86E3/E3/E4 Zilog PIN IDENTIFICATION (Continued) P25 P26 P27 P4 P5 P6 P7 CC XTAL2 XTAL P3 P32 P33 P Pin DIP 4 5 P24 P23 P22 P2 P2 P3 SS P2 P P P3 P36 P37 P35 D5 D6 D7 A4 A5 A6 A7 CC CE OE EPM PP A Pin DIP 4 5 D4 D3 D2 D D A3 SS A2 A A PGM A A A9 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration Figure. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration Table Pin DIP/SOIC/PLCC Pin Identification* Pin # Symbol Function Direction 3 P25 P27 Port 2, Pi 5,6, In/Output 4 7 P4 P7 Port, Pi 4,5,6,7 In/Output 8 CC Power Supply 9 XTAL2 Crystal Oscillator Output XTAL Crystal Oscillator Input 3 P3 P33 Port 3, Pi,2,3 Input 4 5 P34 P35 Port 3, Pi 4,5 Output 6 P37 Port 3, Pin 7 Output 7 P36 Port 3, Pin 6 Output 8 P3 Port 3, Pin Input 9 2 P P2 Port, Pi,,2 In/Output 22 SS Ground 23 P3 Port, Pin 3 In/Output P2 P24 Port 2, Pi,,2,3,4 In/Output XXX P5 XXX P6 XXX P7 XXX CC XXX XT2 XXX XT XXX P3 5 P4 P27 P26 P25 P24 P23 P Pin PLCC P32 P33 P34 P35 P37 P36 P3 XXX P2 XXX P2 XXX P3 XXX SS XXX P2 XXX P XXX P Figure. Standard Mode 28-Pin PLCC Pin Configuration P R E L I M I N A R Y DS97Z8X52

11 Zilog Z86E3/E3/E4 XXX A5 XXX A6 XXX A7 CC XXX XXX XXX CE XXX OE 5 A4 D7 D6 D5 D4 D3 D Pin PLCC Figure 2. EPROM Programming Mode 28-Pin PLCC Pin Configuration EPM PP A8 A9 A A PGM XXX D XXX D XXX A3 XXX SS XXX A2 XXX A XXX A Table Pin EPROM Pin Identification Pin # Symbol Function Direction 3 D5 D7 Data 5,6,7 In/Output 4 7 A4 A7 Address 4,5,6,7 Input 8 CC Power Supply 9 No connection CE Chip Select Input OE Output Enable Input 2 EPM EPROM Prog. Input Mode 3 PP Prog. oltage Input 4 5 A8 A9 Address 8,9 Input 6 A Address Input 7 A Address Input 8 PGM Prog. Mode Input 9 2 A A2 Address,,2 Input 22 SS Ground 23 A3 Address 3 Input D D4 Data,,2,3,4 In/Output DS97Z8X52 P R E L I M I N A R Y

12 Z86E3/E3/E4 Zilog ABSOLTE MAXIMM RATINGS Parameter Min Max nits Ambient Temperature under Bias 4 +5 C Storage Temperature C oltage on any Pin with Respect to SS [Note ].6 +7 oltage on DD Pin with Respect to SS.3 +7 oltage on XTAL and RESET Pi with Respect to SS [Note 2].6 DD + Total Power Dissipation.2 W Maximum Allowable Current out of SS 22 ma Maximum Allowable Current into DD 8 ma Maximum Allowable Current into an Input Pin [Note 3] 6 +6 µa Maximum Allowable Current into an Open-Drain Pin [Note 4] 6 +6 µa Maximum Allowable Output Current Sinked by Any I/O Pin 25 ma Maximum Allowable Output Current Sourced by Any I/O Pin 25 ma Maximum Allowable Output Current Sinked by RESET Pin 3 ma Notes:. This applies to all pi except XTAL pi and where otherwise noted. 2. There is no input protection diode from pin to DD. 3. This excludes XTAL pi. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sectio of these specificatio is not implied. Exposure to absolute maximum rating conditio for an extended period may affect device reliability. Total power dissipation should not exceed.2 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = DD x [ I DD (sum of I OH ) ] + sum of [ ( DD OH ) x I OH ] + sum of ( L x I L ) STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditio as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load). From Output nder Test 5 pf Figure 3. Test Load Diagram 2 P R E L I M I N A R Y DS97Z8X52

13 Zilog Z86E3/E3/E4 CAPACITAE T A = 25 C, CC = GND =, f =. MHz; unmeasured pi returned to GND. Parameter Min Max Input capacitance 2 pf Output capacitance 2 pf I/O capacitance 2 pf DC ELECTRICAL CHARACTERISTICS Sym Parameter CH Clock Input High oltage 3.5 CL Clock Input Low oltage IH Input High oltage 3.5 IL Input Low oltage 3.5 OH Output High oltage Low EMI Mode T A = C to +7 C CC Note [3] Min Max 3.5 OH Output High oltage 3.5 OL Output Low oltage Low EMI Mode OL Output Low oltage OL2 Output Low oltage RH Reset Input High oltage 3.5 RL Reset Input Low oltage 3.5 OLR OFFSET ICR Reset Output Low oltage Comparator Input Offset oltage Input Common Mode oltage Range I IL Input Leakage I OL Output Leakage I IR Reset Input Current CC CC CC CC +.3 GND -.3 GND CC CC CC CC +.3 GND -.3 GND -.3 CC -.4 CC -.4 CC -.4 CC C nits Conditio Notes CC.9.2 CC CC.5.2 CC CC CC.7.8 CC CC 2. GND -.3 GND CC.3.2 CC CC -. CC m m µa µa µa µa µa µa Driven by External Clock Generator Driven by External Clock Generator I OH =.5 ma I OH = -2. ma I OH = -2. ma I OL =. ma I OL =. ma I OL = + 4. ma I OL = + 4. ma I OL = + 2 ma I OL = + 2 ma I OL =. ma I OL =. ma IN =, CC IN =, CC IN =, CC IN =, CC DS97Z8X52 P R E L I M I N A R Y 3

14 Z86E3/E3/E4 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) I CC Supply Current 3.5 I CC Standby Current 3.5 Halt Mode 3.5 I CC2 I ALL I ALH Sym Parameter Standby Current Stop Mode Auto Latch Low Current Auto Latch High Current T A = C to +7 C CC Note [3] Min Max ma ma ma ma ma ma µa µa µa µa µa µa µa 6 6 MHz IN =, 6 MHz Clock Divide by 6 MHz IN =, CC IN =, CC IN =, CC IN =, CC 4,5 4,5 4,5 4,5 4,5 4,5 6, 6, 6,, 4 6,, 4 < IN < CC 9 < IN < CC 9 < IN < CC 9 < IN < CC 9 T POR Power On Reset ms ms L Auto Reset oltage ,7 Notes:. Device does function down to the Auto Reset voltage. 2. GND= 3. The CC voltage specification of guarantees 5. ±.5 and the CC voltage specification of 3.5 guarantees only All outputs unloaded, I/O pi floating, inputs at rail. 5. CL= CL2 = 22 pf 6. Same as note [4] except inputs at CC. 7. Max. temperature is 7 C. 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected. For analog comparator inputs when analog comparators are enabled.. Clock must be forced Low, when XTAL is clock driven and XTAL2 is floating. 2. Typicals are at CC = 5. and CC = Z86E4 only 4. WDT running 25 C nits Conditio Notes 4 P R E L I M I N A R Y DS97Z8X52

15 Zilog Z86E3/E3/E4 CH CL Sym Parameter Clock Input High oltage Clock Input Low oltage T A = 4 C to +5 C CC Note [3] Min Max IH Input High oltage 4.5 IL Input Low oltage 4.5 OH Output High oltage Low EMI Mode 4.5 OH Output High oltage OL Output Low oltage Low EMI Mode 4.5 OL Output Low oltage 4.5 OL2 Output Low oltage 4.5 RH OLR Reset Input High oltage Reset Output Low oltage OFFSET Comparator Input Offset oltage 4.5 ICR Input Common 4.5 Mode oltage Range I IL Input Leakage 4.5 I OL Output Leakage 4.5 I IR Reset Input Current 4.5 I CC Supply Current 4.5 I CC Standby Current 4.5 Halt Mode I CC2 I ALL Standby Current (Stop Mode) Auto Latch Low Current CC CC CC CC +.3 GND-.3 GND-.3.7 CC CC CC CC +.3 GND-.3 GND-.3 CC -.4 CC -.4 CC -.4 CC C nits Conditio Notes CC.5.2 CC CC.5.2 CC CC CC.7.8 CC CC CC -.5 CC < < < < m m µa µa µa µa µa µa ma ma ma ma µa µa µa µa Driven by External Clock Generator Driven by External Clock Generator I OH =.5 ma I OH =.5 ma I OH = -2. ma I OH = -2. ma I OL =. ma I OL =. ma I OL = + 4. ma I OL = +4. ma I OL = + 2 ma I OL = + 2 ma I OL =. ma I OL =. ma IN =, CC IN =, CC IN =, CC IN =, CC MHz 6 MHz 4,5 IN =, CC 6 MHz IN =, CC 6 MHz IN =, CC 6,,4 IN =, CC 6,,4 < IN < CC 9 < IN < CC 9 DS97Z8X52 P R E L I M I N A R Y 5

16 Z86E3/E3/E4 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) I ALH Sym Parameter Auto Latch High Current 4.5 T A = 4 C to +5 C CC Note [3] Min Max C nits Conditio Notes µa µa < IN < CC 9 < IN < CC 9 T POR Power On Reset ms ms L Auto Reset oltage Device does function down to the Auto Reset voltage. 2. GND= 3. The CC voltage specification of guarantees 5. ± All outputs unloaded, I/O pi floating, inputs at rail. 5. CL= CL2 = 22 pf 6. Same as note [4] except inputs at CC. 7. Maximum temperature is 7 C 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected. For analog comparator inputs when analog comparators are enabled.. Clock must be forced Low, when XTAL is clock driven and XTAL2 is floating. 2. Typicals are at CC = Z86E4 only 4. WDT is not running. 6 P R E L I M I N A R Y DS97Z8X52

17 Zilog Z86E3/E3/E4 R/W, DM Port Port A7 - A D7 - D IN 2 9 AS DS (Read) 7 Port A7 - A D7 - D OT DS (W rite) Figure 4. External I/O or Memory Read/Write Timing Z86E4 Only DS97Z8X52 P R E L I M I N A R Y 7

18 Z86E3/E3/E4 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) T A = C to 7 C 6 MHz No Symbol Parameter Note [3] CC Min Max nits Notes TdA(AS) Address alid to AS Rise Delay 25 2 TdAS(A) AS Rise to Address Float Delay 35 3 TdAS(DR) AS Rise to Read Data Req d 3.5 8,2 alid 8 4 TwAS AS Low Width TdAS(DS) Address Float to DS Fall TwDSR DS (Read) Low Width , TwDSW DS (Write) Low Width 3.5 8,2 8 8 TdDSR(DR) DS Fall to Read Data Req d ,2 alid 75 9 ThDR(DS) Read Data to DS Rise Hold Time TdDS(A) DS Rise to Address Active Delay 5 TdDS(AS) DS Rise to AS Fall Delay TdR/W(AS) R/W alid to AS Rise Delay TdDS(R/W) DS Rise to R/W Not alid TdDW(DSW) Write Data alid to DS Fall (Write) Delay TdDS(DW) DS Rise to Write Data Not alid Delay TdA(DR) Address alid to Read Data Req d alid TdAS(DS) AS Rise to DS Fall Delay TdDM(AS) DM alid to AS Fall Delay ThDS(AS) DS alid to Address alid Hold Time 3.5 Notes:. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The CC voltage specification of guarantees 5. ±.5 and the CC voltage specification of 3.5 guarantees only 3.5 Standard Test Load All timing references use.7 CC for a logic and.2 CC for a logic. For Standard Mode (not Low-EMI Mode for outputs) with SMR D =, D = , P R E L I M I N A R Y DS97Z8X52

19 Zilog Z86E3/E3/E4 T A = -4 C to 5 C 6 MHz Note [3] No Symbol Parameter CC Min Max nits Notes TdA(AS) Address alid to AS Rise Delay 25 2 TdAS(A) ASAS Rise to Address Float Delay 35 3 TdAS(DR) AS Rise to Read Data Req d 4.5 8,2 alid 8 4 TwAS AS Low Width TdAS(DS) Address Float to DS Fall TwDSR DS (Read) Low Width , TwDSW DS (Write) Low Width 4.5 8,2 8 8 TdDSR(DR) DS Fall to Read Data Req d ,2 alid 75 9 ThDR(DS) Read Data to DS Rise Hold Time TdDS(A) DS Rise to Address Active Delay 5 TdDS(AS) DS Rise to AS Fall Delay TdR/W(AS) R/W alid to AS Rise Delay TdDS(R/W) DS Rise to R/W Not alid TdDW(DSW) Write Data alid to DS Fall (Write) Delay TdDS(DW) DS Rise to Write Data Not alid Delay 35 6 TdA(DR) Address alid to Read Data ,2 Req d alid 23 7 TdAS(DS) AS Rise to DS Fall Delay TdDM(AS) /DM alid to AS Fall Delay ThDS(AS) DS alid to Address alid Hold Time 4.5 Notes:. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The CC voltage specification of guarantees 5. ±.5 and the CC voltage specification of 3.5 guarantees only 3.5 Standard Test Load All timing references use.7 CC for a logic and.2 CC for a logic. For Standard Mode (not Low-EMI Mode for outputs) with SMR, D =, D = DS97Z8X52 P R E L I M I N A R Y 9

20 Z86E3/E3/E4 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) 3 Clock TIN IRQN 8 9 Clock Setup Stop Mode Recovery Source Figure 5. Additional Timing Diagram 2 P R E L I M I N A R Y DS97Z8X52

21 Zilog Z86E3/E3/E4 Additional Timing Table (Divide-By-One Mode) T A = C to +7 C T A = -4 C to +5 C 4 MHz 4 MHz No Symbol Parameter TpC Input Clock Period TrC,TfC Clock Input Rise & 3.5 Fall Times 3 TwC Input Clock Width TwTinL Timer Input Low 3.5 Width 5 TwTinH Timer Input High 3.5 Width 6 TpTin Timer Input Period TrTin, TfTin Timer Input Rise 3.5 & Fall Timer 8A TwIL Int. Request Low 3.5 Time 8B TwIL Int. Request Low 3.5 Time 9 TwIH Int. Request Input 3.5 High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time CC Note [6] Min Max Min Max nits Notes TpC 5TpC 8TpC 8TpC 7 5TpC 5TpC 5TpC 5TpC 2 2 Notes:. Timing Reference uses.7 CC for a logic and.2 CC for a logic. 2. Interrupt request via Port 3 (P3 P33). 3. Interrupt request via Port 3 (P3). 4. SMR-D5 =, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The CC voltage specification of guarantees 5. ±.5 and the CC voltage specification of 3.5 guarantees 3.5 only. 7. SMR D =. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver. DC DC TpC 5TpC TpC 5TpC 8TpC 8TpC 7 5TpC 5TpC 5TpC 5TpC 2 2 DC DC 25 25,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,7,8,2,7,8,2,7,8,3,7,8,3,7,8,2,7,8,2,7,8 4,8 4,8 5TpC 4,8,9 DS97Z8X52 P R E L I M I N A R Y 2

22 Z86E3/E3/E4 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) Handshake Timing Diagrams Data In Data In alid Next Data In alid 2 DA (Input) 3 Delayed DA RDY (Output) Delayed RDY Figure 6. Input Handshake Timing Data Out Data Out alid Next Data Out alid 7 DA (Output) Delayed DA 8 9 RDY (Input) Delayed RDY Figure 7. Output Handshake Timing 22 P R E L I M I N A R Y DS97Z8X52

23 Zilog Z86E3/E3/E4 Additional Timing Table T A = -4 C to +5 C 6 MHz No Symbol Parameter CC Note [6] Min Max nits Conditio Notes TpC Input Clock Period DC DC,7,8,7,8 2 TrC,TfC Clock Input Rise & Fall Times ,7,8,7,8 3 TwC Input Clock Width ,7,8,7,8 4 TwTinL Timer Input Low Width ,7,8,7,8 5 TwTinH Timer Input High Width 3.5 5TpC 5TpC,7,8,7,8 6 TpTin Timer Input Period 3.5 8TpC 8TpC,7,8,7,8 7 TrTin, TfTin Timer Input Rise & Fall Timer 3.5,7,8,7,8 8A TwIL Int. Request Low Time ,2,7,8,2,7,8 8B TwIL Int. Request Low Time 3.5 5TpC 5TpC,3,7,8,3,7,8 9 TwIH Int. Request Input High Time 3.5 5TpC,2,7,8 Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time 2 Twdt Watch-Dog Timer Delay Time Before Timeout Notes:. Timing Reference uses.7 CC for a logic and.2 CC for a logic. 2. Interrupt request via Port 3 (P3 P33) 3. Interrupt request via Port 3 (P3) 4. SMR-D5 =, POR STOP Mode Delay is on 5. Reg. WDTMR 6. The CC voltage spec. of guarantees 5. ± SMR D = 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver.. Standard Mode (not Low EMI output ports). sing internal RC 5TpC 5TpC ms ms ms ms ms ms ms ms D = D = D = D = D = D = D = D = 4,8 4,8 4,8 4,8 5, 5, 5, 5, 5, 5, 5, 5, DS97Z8X52 P R E L I M I N A R Y 23

24 Z86E3/E3/E4 Zilog PIN FTIONS EPROM Programming Mode D7 D Data Bus. The data can be read from or written to external memory through the data bus. A A Address Bus. During programming, the EPROM address is written to the address bus. CC Power Supply. This pin must supply 5 during the EPROM read mode and 6 during other modes. CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program erify Mode. OE Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages. PP Program oltage. This pin supplies the program voltage. PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above CC occur on pi XTAL and RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the PP, CE, EPM, OE pi while the microcontroller is in Standard Mode. Recommendatio for dampening voltage surges in both test and OTP mode include the following: R/W Read/Write (output, write Low). The R/W signal is Low when the CCP is writing to the external program or data memory (Z86E4 only). RESET Reset (input, active Low). Reset will initialize the MC. Reset is accomplished either through Power-On, Watch-Dog Timer reset, STOP-Mode Recovery, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditio. Pull-up is provided internally. After the POR time, RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z86E4 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 8 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, DS is held active Low while AS cycles at a rate of TpC/2. Program execution begi at location CH, 5 TpC cycles after RESET is released. For Power-On Reset, the reset output time is 5 ms. The Z86E4 does not reset WDTMR, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C9/C89 ROMless Z8. (Note that, when left unconnected or pulled High to CC, the device functio normally as a Z8 ROM version). Note: When using in ROM Mode in High EMI (noisy) environment, the ROMless pi should be connected directly to CC. sing a clamping diode to CC Adding a capacitor to the affected pin Standard Mode XTAL Crystal (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output. 24 P R E L I M I N A R Y DS97Z8X52

25 Zilog Port (P7 P). Port is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Either nibble output that can be globally programmed as push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to Port 's upper nibble. The lower nibble must have the same direction as the upper nibble. For external memory references, Port provides address bits A A8 (lower nibble) or A5 A8 (lower and upper Z86E3/E3/E4 nibble) depending on the required address space. If the address range requires 2 bits or less, the upper nibble of Port can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port mode register. In ROMless mode, after a hardware reset, Port is configured as address lines A5 A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode. In ROM mode, Port is defined as input after reset. Port can be set in the High-Impedance Mode if selected as an address output state, along with Port and the control signals AS, DS, and R/W (Figure 8). 4 4 Port (I/O) Handshake Controls /DA and RDY (P32 and P35) Open-Drain OEN PAD Out In Hysteresis Auto Latch R 5 kω Figure 8. Port Configuration DS97Z8X52 P R E L I M I N A R Y 25

26 Z86E3/E3/E4 Zilog PIN FTIONS (Continued) Port (P7 P). Port is an 8-bit, bidirectional, CMOScompatible port with multiplexed Address (A7 A) and Data (D7 D) ports. These eight I/O lines can be programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY and /DA (Ready and Data Available). To interface external memory, Port must be programmed for the multiplexed Address/Data mode. If more than 256 external locatio are required, Port outputs the additional lines (Figure 9). Port can be placed in the high-impedance state along with Port, AS, DS, and R/W, allowing the Z86E4 to share common resources in multiprocessor and DMA applicatio. Port 2 (I/O) MC Handshake Controls DA and RDY (P33 and P34) Open-Drain OEN PAD Out In Hysteresis Auto Latch R 5 kω Figure 9. Port Configuration (Z86E4 Only) 26 P R E L I M I N A R Y DS97Z8X52

27 Zilog Port 2 (P27 P2). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as an input or output, independently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can Z86E3/E3/E4 be globally programmed by the software. When used as an I/O port, Port 2 can be placed under handshake control. In Handshake Mode, Port 3 lines P3 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (Figure 2). Z86E4 MC Port 2 (I/O) Handshake Controls DA2 and RDY2 (P3 and P36) Open-Drain OEN PAD Out In TTL Level Shifter Auto Latch R 5 KΩ Figure 2. Port 2 Configuration DS97Z8X52 P R E L I M I N A R Y 27

28 Z86E3/E3/E4 Zilog PIN FTIONS (Continued) Port 3 (P37 P3). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33 P3) and four fixed outputs (P37 P34). These eight lines can be configured by software for interrupt and handshake control functio. Port 3, Pin is Schmitt- triggered. P3, P32, and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36, and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P3 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D to state. For the interrupt function, P3 and P33 are falling edge triggered interrupt inputs. P3 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (Figure 2). Access to Counter/Timer is made through P3 (T IN ) and P36 (T OT ). Handshake lines for Port, Port, and Port 2 are also available on Port 3 (Table 9). Note: When enabling/ or disabling analog mode, the following is recommended:. Allow two NOP delays before reading this comparator output. 2. Disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. IRQ register bits 3 to must be cleared after enabling analog mode. Note: P33 P3 differs from the Z86C3/C3/C4 in that there is no clamping diode to CC due to the EPROM highvoltage circuits. Exceeding the IH maximum specification during standard operating mode may cause the device to enter EPROM mode. 28 P R E L I M I N A R Y DS97Z8X52

29 Zilog Z86E3/E3/E4 Z86E4 MC Port 3 (I/O or Control) Auto Latch P3 R247 = P3M R 5 KΩ D = Analog = Digital P3 Data Latch IRQ3 P3 (AN) + - DIG. AN. IRQ2, Tin, P3 Data Latch P32 (AN2) IRQ, P32 Data Latch P33 (REF) + - From Stop Mode Recovery Source IRQ, P33 Data Latch Figure 2. Port 3 Configuration Table 9. Port 3 Pin Assignments Pin I/O CTC Analog Interrupt P HS P HS P2 HS Ext P3 IN IRQ3 P3 IN T IN AN IRQ2 D/R P32 IN AN2 IRQ D/R P33 IN REF IRQ D/R P34 OT AN-Out R/D /DM P35 OT R/D P36 OT T OT R/D P37 OT An2-Out DS97Z8X52 P R E L I M I N A R Y 29

30 Z86E3/E3/E4 Zilog PIN FTIONS (Continued) Comparator Inputs. Port 3, P3, and P32, each have a comparator front end. The comparator reference voltage P33 is common to both comparators. In analog mode, P3 and P32 are the positive input of the comparators and P33 is the reference voltage of the comparators. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33 P3) that are not externally driven. Whether this level is or, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Auto Latches are available on Port, Port 2, and P3. There are no Auto Latches on P3, P32, and P33. Low EMI Emission. The Z86E4 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently. se of this feature results in: The pre-drivers slew rate reduced to typical. Low EMI output drivers have resistance of 2 Ohms (typical). Low EMI Oscillator. Internal SCLK/TCLK= XTAL operation limited to a maximum of 4 MHz 25 cycle time, when Low EMI Oscillator is selected and system clock (SCLK = XTAL, SMR Reg. Bit D =). Note for emulation only: Do not set the emulator to emulate Port in low EMI mode. Port must always be configured in Standard Mode. 3 P R E L I M I N A R Y DS97Z8X52

31 Zilog FTIONAL DESCRIPTION The MC incorporates the following special functio to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways:. Power-On Reset 2. Watch-Dog Timer 3. STOP-Mode Recovery Source Note: Having the Auto Power-On Reset circuitry built-in, the MC does not need to be connected to an external power-on reset circuit. The reset time is 5 ms (typical). The MC does not reinitialize WDTMR, SMR, P2M, and P3M registers to their reset values on a STOP-Mode Recovery operation. Z86E3/E3/E4 Note: The device CC must rise up to the operating CC specification before the TPOR expires. Program Memory. The MC can address up to 4 KB of Internal Program Memory (Figure 22). The first 2 bytes of program memory are reserved for the interrupt vectors. These locatio contain six 6-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 2 (CH) to address 495 (FFFH) coists of programmable EPROM. After reset, the program counter points at the address CH, which is the starting address of the user program. In ROMless mode, the Z86E4 can address up to 64 KB of External Program Memory. The ROM/ROMless option is only available on the 44-pin devices EPROM External ROM and RAM On-Chip One Time PROM ROMless External ROM and RAM Location of First Byte of Itruction Executed After RESET 2 IRQ5 IRQ5 IRQ5 IRQ5 9 IRQ4 IRQ4 8 IRQ4 IRQ4 Interrupt ector (Lower Byte) IRQ3 IRQ3 IRQ2 IRQ3 IRQ3 IRQ2 Interrupt ector (pper Byte) IRQ2 IRQ IRQ IRQ2 IRQ IRQ IRQ IRQ IRQ IRQ Figure 22. Program Memory Map (ROMless Z86E4 Only) EPROM Protect. When in ROM Protect Mode, and executing out of External Program Memory, itructio LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in ROM Protect Mode and executing out of Internal Program Memory, itructio LDC, LDCI, LDE, and LDEI can read Internal Program Memory. DS97Z8X52 P R E L I M I N A R Y 3

32 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) Data Memory (DM). In EPROM Mode, the Z86E4 can address up to 6 KB of external data memory beginning at location 496. In ROMless mode, the Z86E4 can address up to 64 KB of data memory. External data memory may be included with, or separated from, the external program memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 23). The state of the DM signal is controlled by the type of itruction being executed. An LDC opcode references PROGRAM (DM inactive) memory, and an LDE itruction references data (DM active Low) memory EPROM ROMless External Data Memory External Data Memory Not Addressable Figure 23. Data Memory Map 32 P R E L I M I N A R Y DS97Z8X52

33 Zilog Register File. The register file coists of three I/O port registers, 236/25 general-purpose registers, 5 control and status registers, and three system configuration registers in the expanded register group. The itructio can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 24). In the 4-bit mode, the register file is divided into 6 working register groups, each Z86E3/E3/E4 occupying 6 continuous locatio. The Register Pointer addresses the starting location of the active working-register group. Note: Register Bank E EF can only be accessed through working register and indirect addressing modes. (This bank is available in Z86E3/E4 only.) R253 RP D7 D6 D5 D4 D3 D2 D D Expanded Register Group Working Register Group Default setting after RESET = Figure 24. Register Pointer Register Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space R through R5 is implemented as 6 groups of 6 registers per group (Figure 26). These register groups are known as the Expanded Register File (ERF). The low nibble (D3 D) of the Register Pointer (RP) select the active ERF group, and the high nibble (D7 D4) of register RP select the working register group. Three system configuration registers reside in the Expanded Register File at bank FH: PCON, SMR, and WDTMR. The rest of the Expanded Register is not physically implemented and is reserved for future expaion. DS97Z8X52 P R E L I M I N A R Y 33

34 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) r7 r6 r5 r4 r3 r2 r r R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF F EF 8 7F 7 6F Register Group F Note: Registers 8H through EFH are available in the Z86C3 only. 6 5F 5 4F 4 3F 3 2F 2 F F Specified Working Register Group Register Group Register Group I/O Ports * Expanded Register Group () is selected in this figure by handling bits D3 to D as "" in Register R253 (RP). The lower nibble of the register file address provided by the itruction points to the specified register. R5 to R R5 to R4* R3 to R* Figure 25. Register Pointer 34 P R E L I M I N A R Y DS97Z8X52

35 Zilog Z86E3/E3/E4 REGISTER POINTER Z8 STANDARD CONTROL REGISTERS RESET CONDITION D7 D6 D5 D4 D3 D2 D D REGISTER % FF SPL % FE SPH Working Register Group Pointer Expanded Register Group Pointer % FD % FC % FB RP FLAGS IMR % FA IRQ % F9 IPR %FF %FO Z8 Reg. File Z86E3/E4 Only * * % F8 % F7 % F6 % F5 % F4 % F3 % F2 PM P3M P2M PRE T PRE T % F TMR % F Reserved %7F Z86E3/E4 Only EXPANDED REG. GROP (F) REGISTER RESET CONDITION * * % (F) F % (F) E % (F) D WDTMR Reserved SMR2 ** % (F) C % (F) B Reserved SMR % (F) A Reserved % (F) 9 Reserved Reserved % (F) 8 % (F) 7 Reserved Reserved %F % % (F) 6 % (F) 5 Reserved Reserved % (F) 4 Reserved % (F) 3 Reserved % (F) 2 Reserved % (F) Reserved % (F) PCON Notes: = nknown For Z86E4 (ROMless) reset condition: "" Will not be reset with a STOP Mode Recovery Will not be reset with a STOP Mode Recovery, except Bit D. * ** EXPANDED REG. GROP () REGISTER * % () 3 P3 * % () 2 P2 % () P % () P RESET CONDITION Figure 26. Expanded Register File Architecture DS97Z8X52 P R E L I M I N A R Y 35

36 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the CC voltage-specified operating range. The register R254 is general-purpose on Z86E3/E3. R254 and R255 are set to H after any reset or STOP-Mode Recovery. RAM Protect. The upper portion of the RAM's address spaces 8H to EFH (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R25) is used to turn off/on the RAM protect by loading a or, respectively. A in D6 indicates RAM Protect enabled. RAM Protect is not available on the Z86E3. Stack. The Z86E4 external data memory or the internal register file can be used for the stack. The 6-bit Stack Pointer (R254 R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 496 to in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z86E3/E3/E4 that resides within the 236 general-purpose registers (R4 R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to H after any reset or Stop- Mode Recovery. Counter/Timers. There are two 8-bit programmable counter/timers (T and T), each driven by its own 6-bit programmable prescaler. The T prescaler is driven by internal or external clock sources; however, the T prescaler is driven by the internal clock only (Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from to 64. Each prescaler drives its counter, which decrements the value ( to 256), that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T) or IRQ5 (T), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P3) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 serves as a timer output (T OT ) through which T, T, or the internal clock can be output. The counter/timers can be cascaded by connecting the T output to the input of T. 36 P R E L I M I N A R Y DS97Z8X52

37 Zilog Z86E3/E3/E4 D (SMR) OSC Internal Data Bus D (SMR) 2 Write Write Read PRE Initial alue Register T Initial alue Register T Current alue Register Bit Down Counter 8-bit Down Counter IRQ4 Internal Clock External Clock 2 TOT P36 Clock Logic 4 6-Bit Down Counter 8-Bit Down Counter IRQ5 Internal Clock Gated Clock Triggered Clock PRE Initial alue Register T Initial alue Register T Current alue Register TIN P3 Write Write Read Internal Data Bus Figure 27. Counter/Timer Block Diagram DS97Z8X52 P R E L I M I N A R Y 37

38 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) Interrupts. The MC has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines P33 P3) and two in counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table ). IRQ IRQ2 IRQ, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7) IRQ IMR 6 Global Interrupt Enable IPR Interrupt Request Priority Logic ector Select Figure 28. Interrupt Block Diagram Table. Interrupt Types, Sources, and ectors Name Source ector Location Comments IRQ DA, IRQ, External (P32), Rising/Falling Edge Triggered IRQ IRQ 2, 3 External (P33), Falling Edge Triggered IRQ2 DA2, IRQ2, T IN 4, 5 External (P3), Rising/Falling Edge Triggered IRQ3 IRQ3 6, 7 External (P3), Falling Edge Triggered IRQ4 T 8, 9 Internal IRQ5 TI, Internal 38 P R E L I M I N A R Y DS97Z8X52

39 Zilog When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All interrupts are vectored through locatio in the program memory. This memory location and the next byte contain the 6-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ. Interrupts IRQ2 and IRQ may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in bits D7 and D6 of the IRQ Register (R25). The configuration is shown in Table. Z86E3/E3/E4 Table. IRQ Register Configuration IRQ Interrupt Edge D7 D6 P3 P32 F F F R R F R/F R/F Notes: F = Falling Edge R = Rising Edge Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, RC, ceramic resonator, or any suitable external clock source (XTAL = Input, XTAL2 = Output). The crystal should be AT cut, KHz to 6 MHz max, with a series resistance (RS) less than or equal to Ohms. The crystal should be connected across XTAL and XTAL2 using the vendor's recommended capacitor values from each pin directly to device pin Ground. The RC oscillator option can be selected in the programming mode. The RC oscillator configuration must be an external resistor connected from XTAL to XTAL2, with a frequency-setting capacitor from XTAL to Ground (Figure 29). C XTAL C XTAL C XTAL XTAL L R C2 XTAL2 C2 XTAL2 XTAL2 XTAL2 Ceramic Resonator or Crystal C, C2 = 47 pf TYP * F = 8 MHz LC C, C2 = 22 pf L = 3 µh * F = 3 MHz * * Typical value including pin parasitics 5 cc (TYP) C = pf R = 2K F = 6 MHz External Clock Figure 29. Oscillator Configuration DS97Z8X52 P R E L I M I N A R Y 39

40 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR timer allows CC and the oscillator circuit to stabilize before itruction execution begi. The POR timer circuit is a one-shot timer triggered by one of three conditio:. Power fail to Power OK status 2. Stop-Mode Recovery (if D5 of SMR=) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is bypassed after STOP-Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Tur off the internal CP clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ, IRQ, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the itruction after the HALT. In order to enter STOP or HALT Mode, it is necessary to first flush the itruction pipeline to avoid suspending execution in mid-itruction. To do this, the user must execute a NOP (Opcode=FFH) immediately before the appropriate sleep itruction, that is: FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode STOP. This itruction tur off the internal clock and external crystal oscillation and reduces the standby current to microamperes or less. STOP Mode is terminated by one of the following resets: either by WDT time-out, POR, a Stop-Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address CH. Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port and Port, low EMI on Ports,, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location (Figure 3). PCON (FH) H D7 D6 D5 D4 D3 D2 D D Comparator Output Port 3 P34, P37 Standard Output* P34, P37 Comparator Output * Default Setting After Reset Port Open Drain Port Push-pull Active* Port Open Drain Port Push-pull Active* Port Low EMI Port Standard* Port Low EMI Port Standard* Port 2 Low EMI Port 2 Standard* Port 3 Low EMI Port 3 Standard* Low EMI Oscillator Low EMI Standard* Figure 3. Port Configuration Register (PCON) (Write Only) 4 P R E L I M I N A R Y DS97Z8X52

41 Zilog Comparator Output Port 3 (D). Bit controls the comparator output in Port 3. A in this location brings the comparator outputs to P34 and P37, and a releases the Port to its standard I/O configuration. The default value is. Port Open-Drain (D). Port can be configured as an open-drain by resetting this bit (D=) or configured as push-pull active by setting this bit (D=). The default value is. Port Open-Drain (D2). Port can be configured as an open-drain by resetting this bit (D2=) or configured as push-pull active by setting this bit (D2=). The default value is. Low EMI Port (D3). Port can be configured as a Low EMI Port by resetting this bit (D3=) or configured as a Standard Port by setting this bit (D3=). The default value is. Low EMI Port (D4). Port can be configured as a Low EMI Port by resetting this bit (D4=) or configured as a Standard Port by setting this bit (D4=). The default value is. Note: The emulator does not support Port low EMI mode and must be set D4 =. Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=) or configured as a Standard Port by setting this bit (D5=). The default value is. Z86E3/E3/E4 Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=) or configured as a Standard Port by setting this bit (D6=). The default value is. Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscillator. A in this location configures the oscillator with standard drive. While a configures the oscillator with low noise drive, however, it does not affect the relatiohip of SCLK and XTAL. The low EMI mode will reduce the drive of the oscillator (OSC). The default value is. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 3). All bits are Write Only except bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4 of the SMR register specify the Stop-Mode Recovery Source. The SMR is located in Bank F of the Expanded Register Group at address BH. DS97Z8X52 P R E L I M I N A R Y 4

42 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) SMR (F) B D7 D6 D5 D4 D3 D2 D D SCLK/TCLK Divide by 6 OFF ** ON External Clock Divide by 2 SCLK/TCLK =XTAL/2* SCLK/TCLK =XTAL Stop Mode Recovery Source POR and/or External Reset* P3 P3 P32 P33 P27 P2 NOR :3 P2 NOR :7 Stop Delay OFF ON * Stop Recovery Level Low * High Stop Flag POR * Stop Recovery * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Figure 3. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which is Read-Only) 42 P R E L I M I N A R Y DS97Z8X52

43 Zilog SCLK/TCLK Divide-by-6 Select (D). This bit of the SMR controls a divide-by-6 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power coumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D=). sing this bit together with D7 of Z86E3/E3/E4 PCON further helps lower EMI (i.e., D7 (PCON) =, D (SMR) = ). The default setting is zero. STOP-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake up source of the STOP-Mode Recovery (Figure 32). Table 2 shows the SMR source selected with the setting of D2 to D4. P33 P3 cannot be used to wake up from STOP mode when programmed as analog inputs. When the STOP- Mode Recovery sources are selected in this register then SMR2 register bits D, D must be set to zero. Note: If the Port2 pin is configured as an output, this output level will be read by the SMR circuitry. SMR2 D D DD SMR2 D D SMR2 D D P2 P2 P23 P27 SMR D4 D3 D2 DD P3 P3 P32 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 P2 P33 P27 P23 SMR D4 D3 D2 P2 P27 SMR D4 D3 D2 To POR RESET Stop-Mode Recovery Edge Select (SMR) P33 From Pads MX To P33 Data Latch and IRQ Digital/Analog Mode Select (P3M) Figure 32. Stop-Mode Recovery Source DS97Z8X52 P R E L I M I N A R Y 43

44 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) Table 2. Stop-Mode Recovery Source D4 D3 D2 SMR Source selection POR recovery only P3 traition P3 traition (Not in analog mode) P32 traition (Not in analog mode) P33 traition (Not in analog mode) P27 traition Logical NOR of Port 2 bits 3 Logical NOR of Port 2 bits 7 Stop-Mode Recovery Delay Select (D5). The 5 ms RE- SET delay after Stop-Mode Recovery is disabled by programming this bit to a zero. A in this bit will cause a 5 ms RESET delay after Stop-Mode Recovery. The default condition of this bit is. If the fast wake up mode is selected, the Stop-Mode Recovery source needs to be kept active for at least 5TpC. Stop-Mode Recovery Level Select (D6). A in this bit defines that a high level on any one of the recovery sources wakes the MC from STOP Mode. A defines low level recovery. The default value is. Cold or Warm Start (D7). This bit is set by the device upon entering STOP Mode. A in this bit indicates that the device has been reset by POR (cold). A in this bit indicates the device was awakened by a SMR source (warm). Stop-Mode Recovery Register 2 (SMR2). This register contai additional Stop-Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR Register. Bits D2, D3, and D4 must be. SMR: Operation D D Description of Action POR and/or external reset recovery Logical AND of P2 through P23 Logical AND of P2 through P27 Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On Reset and initially enabled by executing the WDT itruction and refreshed on subsequent executio of the WDT itruction. The WDT is driven either by an on-board RC oscillator or an external oscillator from XTAL pin. The POR clock source is selected with bit 4 of the WDT register. Note: Execution of the WDT itruction affects the Z (Zero), S (Sign), and (Overflow) flags. WDT Time-Out Period (D and D). Bits and control a tap circuit that determines the time-out periods that can be obtained (Table 3). The default value of D and D are and, respectively. D Table 3. Time-out Period of WDT D Time-out of the Internal RC OSC Time-out of the System Clock 5 ms 28 SCLK ms* 256 SCLK* 2 ms 52 SCLK 8 ms 248 SCLK Notes: *The default setting is ms. WDT During HALT Mode (D2). This bit determines whether or not the WDT is active during HALT Mode. A indicates that the WDT is active during HALT. A disables the WDT in HALT Mode. The default value is. WDT During STOP Mode (D3). This bit determines whether or not the WDT is active during STOP mode. A indicates active during STOP. A disables the WDT during STOP Mode. This is applicable only when the WDT clock source is the internal RC oscillator. Clock Source For WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL, and the WDT is stopped in STOP Mode. The default configuration of this bit is, which selects the RC oscillator. Permanent WDT. When this feature is enabled, the WDT is enabled after reset and will operate in Run and Halt Mode. The control bits in the WDTMR do not affect the WDT operation. If the clock source of the WDT is the internal RC oscillator, then the WDT will run in STOP mode. If the clock source of the WDT is the XTAL pin, then the WDT will not run in STOP mode. Note: WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 6 internal system clock 44 P R E L I M I N A R Y DS97Z8X52

45 Zilog cycles from the execution of the first itruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery (Figures 33 and 34). After this point, the register cannot be modified by any mea, intentional or Z86E3/E3/E4 otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location FH. WDTMR (F) F D7 D6 D5 D4 D3 D2 D D WDT TAP INT RC OSC System Clock 5 ms 28 SCLK * ms 256 SCLK 2 ms 52 SCLK 8 ms 248 SCLK WDT During HALT OFF ON * WDT During STOP OFF ON * XTAL/INT RC Select for WDT On-Board RC * XTAL Reserved (Must be ) * Default setting after RESET Figure 33. Watch-Dog Timer Mode Register Write Only DS97Z8X52 P R E L I M I N A R Y 45

46 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) Reset 4 Clock Filter Clear CLK 8 Clock RESET Generator RESET Internal RESET WDT Select (WDTMR) WDT TAP SELECT CLK Source Select (WDTMR) XTAL Internal RC OSC. M X 5ms POR 5ms 5ms 25ms ms CK WDT/POR Counter Chain CLR DD L Operating oltage Det. WDT From Stop Mode Recovery Source Stop Delay Select (SMR) Figure 34. Resets and WDT 46 P R E L I M I N A R Y DS97Z8X52

47 Zilog Auto Reset oltage. An on-board oltage Comparator checks that CC is at the required level to eure correct operation of the device. Reset is globally driven if CC is below L (Figure 35). Z86E3/E3/E4 Note: CC must be in the allowed operating range prior to the minimum Power-On Reset time-out (T POR ). CC (olts) Temperature ( C) Figure 35. Typical Z86E4 L oltage vs. Temperature DS97Z8X52 P R E L I M I N A R Y 47

48 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) EPROM MODE Table 4 shows the programming voltages of each programming mode. Table 5, and figures that follow show the programming timing of each programming mode. Figure 38 shows the circuit diagram of a Z86E4 programming adapter, which adapts from 2764A to Z86E4 and Figure 39 shows the Z86E3/E3 Programming Adapter Circuitry. Figure 4 shows the flowchart of an Intelligent Programming Algorithm, which is compatible with 2764A EPROM (Z86E4 is 4K EPROM, 2764A is 8K EPROM). Since the EPROM size of Z86E3/E3/E4 differs from 2764A, the programming address range has to be set from H to FFFH for the Z86E3/E4 and H to 7FFH for Z86E3. Otherwise, the upper portion of EPROM data will overwrite the lower portion of EPROM data. Figure 39 shows the adaptation from the 2764A to Z86E3/E3. Note: EPROM Protect feature allows the LDC, LDCI, LDE, and LDEI itructio from internal program memory. A ROM lookup table can be used with this feature. During programming, the PP input pin supplies the programming voltage and current to the EPROM. This pin is also used to latch which EPROM mode is to be used (R/W EPROM or R/W Option bits). The mode is set by placing the correct mode number on the least significant bits of the address and raising the EPM pin above. After a setup time, the PP pin can then be raised or lowered. The latched EPROM mode will remain until the EPM pin is reduced below H. EPROM R/W mode allows the programming of the user mode program ROM. Option Bit R/W allows the programming of the Z8 option bits. When the device is latched into Option Bit R/W mode, the address must then be changed to 63 decimals ( Binary). The Optio are mapped into this address as follows: Bit Option 7 nused 6 nused 5 32 KHz XTAL Option 4 Permanent WDT 3 Auto Latch Disable 2 RC Oscillator Option RAM Protect ROM Protect Table 4 gives the proper conditio for EPROM R/W operatio, once the mode is latched. Mode Name Mode # LSB Addr EPROM R/W Option Bit R/W 3 48 P R E L I M I N A R Y DS97Z8X52

49 Zilog Z86E3/E3/E4 Table 4. EPROM Programming Table Programming Modes PP EPM CE OE PGM ADDR DATA CC * EPROM READ X H IL IL IH ADDR Out 4.5 EPROM READ2 X H IL IL IH ADDR Out PROGRAM H H IL IH IL ADDR In 6.4 PROGRAM H H IL IL IH ADDR Out 6. ERIFY OPTION BIT PGM H H IL IH IL 63 IN 6.4 OPTION BIT READ X H IL IL IH 63 OT 6. Notes: H = 3. ±. IH = As per specific Z8 DC specification IL= As per specific Z8 DC specification X=Not used, but must be set to H, IH, or IL level. N = Not used, but must be set to either IH or IL level. I PP during programming = 4 ma maximum. I CC during programming, verify, or read = 4 ma maximum. * CC has a tolerance of ±.25. Zilog recommends an EPROM read at CC = 4.5 and 5.5 to eure proper device operatio during the CC after programming, but CC = 5. is acceptable. Table 5. EPROM Programming Timing Parameters Name Min Max nits Address Setup Time 2 µs 2 Data Setup Time 2 µs 3 PP Setup 2 µs 4 CC Setup Time 2 µs 5 Chip Enable Setup Time 2 µs 6 Program Pulse Width.95.5 ms 7 Data Hold Time 2 µs 8 OE Setup Time 2 µs 9 Data Access Time 2 Data Output Float Time Overprogram Pulse 2.85 ms Width/Option Program Pulse Width 2 EPM Setup Time 2 µs 3 PGM Setup Time 2 µs 4 Address to OE Setup Time 2 µs 5 OE Width 25 6 Address to OE Low 25 DS97Z8X52 P R E L I M I N A R Y 49

50 Z86E3/E3/E4 Zilog FTIONAL DESCRIPTION (Continued) IH Address IL Address Stable Address Stable Data PP IH IL H IL 6 Invalid alid Invalid alid 9 H EPM CC IL IH CE IL IH 5 5 OE IL IH 5 5 PGM IL 3 Figure 36. EPROM Read Mode Timing Diagram 5 P R E L I M I N A R Y DS97Z8X52

51 Zilog Z86E3/E3/E4 Z86E4 TIMING DIAGRAMS IH Address IL Address Stable IH Data IL Data Stable Data Out alid 2 9 PP H IH 3 EPM H IL CC IH 4 7 CE IL IH 5 OE IL IH PGM IL Program Cycle erify Cycle Figure 37. Timing Diagram of EPROM Program and erify Modes DS97Z8X52 P R E L I M I N A R Y 5

52 Z86E3/E3/E4 Zilog Z86E4 TIMING DIAGRAMS (Continued) 2 D D D2 D3 D4 D5 D6 D P2 P2 P22 P23 P24 P25 P26 P27 P P P2 P3 P4 P5 P6 P A A A2 A3 A4 A5 A6 A7 A8 A 9 A 8 A2 7 A3 6 A4 5 A5 4 A6 3 A7 25 A D D D2 D3 D4 D5 D6 D7 A A A2 A3 A4 A5 A6 A7 GND 26 P 27 P 3 P2 34 P3 5 P4 6 P P6 P7 R/W AS DS RESET P3 P3 P32 P33 P34 P35 P36 P37 XTAL XTAL2 25 PGM 6 OE 7 EPM 8 PP 9 A8 22 A9 24 A 23 A 3 GND CC 5 CE 4 A9 A A KOhm R2 2 KOhm R A9 A A A2 PGM GND CS CC OE PP 2764 Pi 4 GND 28 CC PP C 2.µF GND Z86E4 4-Pin DIP Socket 2.5 R4 2 R X 3 D.µF C2 2 KOhm N D KOhm GND CC 4 X3 5 IX D3 3 EPM GND 5. GND 2 P R olt 4 X S2 5 X S4 X IX2 D2 3 X D4 6 X CC 5. GND N523 2 D2 KOhm IH543 Figure 38. Z86E4 Z8 OTP Programming Adapter For use with Standard EPROM Programmers 52 P R E L I M I N A R Y DS97Z8X52

53 Zilog Z86E3/E3/E4 2 D D D2 D3 D4 D5 D6 D P2 P2 P22 P23 P24 P25 P26 P27 A A A2 A3 A4 A5 A6 A7 A4 A 9 A 8 A2 7 A3 6 A4 5 A5 4 A6 3 A7 25 A D D D2 D3 D4 D5 D6 D7 A A A2 A3 A4 A5 A6 A7 9 P 2 P 2 P2 23 P3 4 P4 5 P5 6 7 P6 P7 P3 P3 P32 P33 P34 P35 P36 P PGM OE EPM PP A8 A9 A A A5 A6 A7 KOhm R2 2 KOhm R A9 A A A2 PGM CS OE GND CC PP 4 GND 28 CC PP XTAL XTAL2 9 CE 2764 Pi C 2.µF GND Z86E3/3 28-Pin DIP Socket 2.5 R4 2 R3 2 KOhm KOhm 3.µF C2 2 N D X GND CC 4 X3 5 IX 4 S2 X D D3 3 D2 3 X EPM GND 5. N523 GND 2 D2 2 KOhm P R olt 5 S4 X D4 6 X GND X IX2 IH543 CC 5. Note: The programming address must be set to H - FFFH (Lower 4K Byte Memory). For Z86E3 H - 7FFH (Lower 2K Byte Memory). For Z86E3 Figure 39. Z86E3/E3 Programming Adapter Circuitry DS97Z8X52 P R E L I M I N A R Y 53

54 Zilog Z86E3/E3/E4 Start Addr = First Location cc = 6.4 pp = 3. N = Program ms Pulse Increment N N = 25? Yes No Fail Pass erify One Byte erify Byte Pass Fail Prog. One Pulse 3xN ms Duration Increment Address No Last Addr? Yes cc = pp = 4.5 * Note: * To eure proper operaton, Zilog recommends cc range of the device cc specification, But cc = 5. is acceptable. Pass erify All Bytes Fail cc = pp = * Device Failed Pass erify All Bytes Fail Device Passed Figure 4. Z86E4 Programming Algorithm DS97Z8X52 P R E L I M I N A R Y 55

55 Z86E3/E3/E4 Zilog EXPANDED REGISTER FILE CONTROL REGISTERS PCON (FH) H D7 D6 D5 D4 D3 D2 D D WDTMR (F) F D7 D6 D5 D4 D3 D2 D D * Default Setting After Reset Must Be for Z86E3/E3 Comparator Output Port 3 P34, P37 Standard* P34, P37 Comparator Output Port Open-Drain Port Push-Pull Active* Port Open-Drain Port Push-pull Active* Port Low EMI Port Standard* Port Low EMI Port Standard* Port 2 Low EMI Port 2 Standard* Port 3 Low EMI Port 3 Standard* Low EMI Oscillator Low EMI Standard* * Default setting after RESET WDT TAP INT RC OSC System Clock 5 ms 28 SCLK * ms 256 SCLK 2 ms 52 SCLK 8 ms 248 SCLK WDT During HALT OFF ON * WDT During STOP OFF ON * XTAL/INT RC Select for WDT On-Board RC * XTAL Reserved (Must be ) Figure 43. Watch-Dog Timer Mode Register Write Only Figure 4. Port Configuration Register Write Only SMR2 (F) DH D7 D6 D5 D4 D3 D2 D D SMR (FH) B D7 D6 D5 D4 D3 D2 D D SCLK/TCLK Divide-by-6 OFF ** ON External Clock Divide by 2 SCLK/TCLK =XTAL/2* SCLK/TCLK =XTAL Stop Mode Recovery Source POR Only and/or External Reset* P3 P3 P32 P33 P27 P2 NOR -3 P2 NOR -7 Stop Delay OFF ON* Stop Recovery Level Low* High Stop Flag POR* Stop Recovery * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Note: Not used in conjunction with SMR Source Stop-Mode Recovery Source 2 POR only* AND P2,P2,P22,P23 AND P2,P2,P22,P23,P24, P25,P26,P27 Reserved (Must be ) Figure 44. STOP-Mode Recovery Register 2 Write Only Figure 42. STOP-Mode Recovery Register Write Only Except Bit D7, Which is Read Only 56 P R E L I M I N A R Y DS97Z8X52

56 Zilog Z86E3/E3/E4 Z8 CONTROL REGISTER DIAGRAMS R24 D7 D6 D5 D4 D3 D2 D D R243 PRE D7 D6 D5 D4 D3 D2 D D Figure 45. Reserved R24 TMR D7 D6 D5 D4 D3 D2 D D Reserved (Must be ) *Default After Reset Count Mode T Single Pass* T Modulo N Clock Source T Internal T External Timing Input (TIN Mode) Prescaler Modulo (Range: -64 Decimal - HEX) No Function* Load T Disable T Count* Enable T Count No Function* Load T Disable T Count* Enable T Count TIN Modes External Clock Input* Gate Input Trigger Input (Non-retriggerable) Trigger Input (Retriggerable) TOT Modes Not sed* T Out T Out Internal Clock Out R244 T Figure 48. Prescaler Register F3H: Write Only D7 D6 D5 D4 D3 D2 D D T Initial alue (When Written) (Range: -256 Decimal - HEX) T Current alue (When Read) Figure 49. Counter/Timer Register F4H; Read/Write Default After Reset = H Figure 46. Timer Mode Register FH: Read/Write R245 PRE D7 D6 D5 D4 D3 D2 D D R242 T D7 D6 D5 D4 D3 D2 D D Count Mode T Single Pass T Modulo N Reserved (Must be ) T Initial alue (When Written) (Range: -256 Decimal - HEX) T Current alue (When Read) Figure 5. Prescaler Register F5H: Write Only Prescaler Modulo (Range: -64 Decimal - HEX) Figure 47. Counter/Timer Register F2H: Read/Write DS97Z8X52 P R E L I M I N A R Y 57

57 Z86E3/E3/E4 Zilog Z8 CONTROL REGISTER DIAGRAMS (Continued) R246 P2M D7 D6 D5 D4 D3 D2 D D R248 PM D7 D6 D5 D4 D3 D2 D D * Default After Reset P2 - P27 I/O Definition Defines Bit as Output Defines Bit as Input* P3 P Mode Output Input X A A8 Stack Selection External Internal R247 P3M Figure 5. Port 2 Mode Register F6H: Write Only D7 D6 D5 D4 D3 D2 D D Port 2 Open-Drain Port 2 Push-pull Active P3, P32 Digital Mode P3, P32 Analog Mode P32 = Input P35 = Output P32 = DA/RDY P35 = RDY/DA P33 = Input P34 = Output P33 = Input P34 = DM P33 = DA/RDY P34 = RDY/DA Reset Condition = B For ROMless Condition = B Z86E3/E3 Must be P7 P Mode Byte Output Byte Input AD7 AD High-Impedance AD7 AD, AS, DS, R/W, A A8, A5 A2, If Selected External Memory Timing Normal Extended P7 P4 Mode Output Input X A5 - A2 Figure 53. Port and Mode Register F8H: Write Only Z86E3/E3 Only Default After Reset = H Z86E3/E3 Must Be P3 = Input (TIN) P36 = Output (TOT) P3 = DA2/RDY2 P36 = RDY2/DA2 P3 = Input P37 = Output Reserved (Must be ) Figure 52. Port 3 Mode Register F7H: Write Only R249 IPR D7 D6 D5 D4 D3 D2 D D Interrupt Group Priority Reserved C > A > B A > B > C A > C > B B > C > A C > B > A B > A > C Reserved IRQ, IRQ4 Priority (Group C) IRQ > IRQ4 IRQ4 > IRQ IRQ, IRQ2 Priority (Group B) IRQ2 > IRQ IRQ > IRQ2 IRQ3, IRQ5 Priority (Group A) IRQ5 > IRQ3 IRQ3 > IRQ5 Reserved (Must be ) Figure 54. Interrupt Priority Register F9H: Write Only 58 P R E L I M I N A R Y DS97Z8X52

58 Zilog Z86E3/E3/E4 R25 IRQ D7 D6 D5 D4 D3 D2 D D R253 RP D7 D6 D5 D4 D3 D2 D D IRQ = P32 Input IRQ = P33 Input IRQ2 = P3 Input IRQ3 = P3 Input IRQ4 = T IRQ5 = T Default After Reset = H Expanded Register File Working Register Pointer Default After Reset = H Inter Edge P3 P32 = P3 P32 = P3 P32 = P3 P32 = Figure 58. Register Pointer FDH: Read/Write Figure 55. Interrupt Request Register FAH: Read/Write R254 SPH D7 D6 D5 D4 D3 D2 D D R25 IMR D7 D6 D5 D4 D3 D2 D D (Z86E4) Stack Pointer pper Byte (SP8 - SP5) (Z86E3/E3) = State = State Enables IRQ5-IRQ (D = IRQ) Enables RAM Protect Enables Interrupts Figure 59. Stack Pointer High FEH: Read/Write This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently. R252 FLAGS Figure 56. Interrupt Mask Register FBH: Read/Write R255 SPL D7 D6 D5 D4 D3 D2 D D Stack Pointer Lower Byte (SP - SP7) D7 D6 D5 D4 D3 D2 D D ser Flag F ser Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 6. Stack Pointer Low FFH: Read/Write Figure 57. Flag Register FCH: Read/Write DS97Z8X52 P R E L I M I N A R Y 59

59 Z86E3/E3/E4 Zilog PACKAGE INFORMATION (Continued) PACKAGE INFORMATION Figure 6. 4-Pin DIP Package Diagram 6 P R E L I M I N A R Y DS97Z8X52

60 Zilog Z86E3/E3/E4 Figure Pin PLCC Package Diagram Figure Pin QFP Package Diagram DS97Z8X52 P R E L I M I N A R Y 6

61 Z86E3/E3/E4 Zilog Figure Pin DIP Package Diagram Figure Pin SOIC Package Diagram 62 P R E L I M I N A R Y DS97Z8X52