Computer Architecture. Lecture 1 Introduction

Transcription

1 Computer Architecture Lecture 1 Introduction

2 Why do you want to study Computer Architecture? Because.You won t graduate if you don t take this course. Because.You want to design the next great instruction set. Instruction set architecture has largely converged, especially in the desktop/server/laptop space. Dictated by powerful market forces (Intel/ARM). Because.You want to become a computer architect and design the next great computer systems. Because.The design, analysis, implementation concepts that you will learn are vital to all aspects of computer science and engineering operating systems, computer networks, compiler, programming languages Because.The course will equip you with an intellectual toolbox for dealing with a host of systems design challenges. From Prof. Fernando C. Colon Osorio s lecture notes Computer Architecture & Network Lab

3 Course Goals Understand Interfaces Instruction Set Architecture ( The Hardware/Software Interface ) Engineering methodology/ Correctness criteria/ Evaluation methods/ Technology trends involved in the following design techniques Pipelining Cache Multiprocessor Cache Coherence Synchronization Interconnection Network Computer Architecture & Network Lab 3

4 Interface Source : Computer Architecture & Network Lab 4

5 Abstract Data Type (ADT) as an Example of Interface Abstract data type : A set of data values (state) and associated operations that are precisely specified independent of any particular implementation ADT Example : stack push pop Create_stack (top) (bottom) stack S is_empty Computer Architecture & Network Lab 5

6 Abstract Data Type (ADT) as an Example of Interface Operations viewed as state transformation 5 1 S Push (s, 4) S` (Before) stack (After) stack Computer Architecture & Network Lab 6

7 Abstraction (Before) (After) Jeff Kramer, Is Abstraction the Key to Computing, Communications of ACM, April 007, Vol. 50, No. 4, pp Computer Architecture & Network Lab 7

8 Abstraction (Before) (After) Computer Architecture & Network Lab 8

9 Abstraction (Before) (After) Jinwook Seo, Information Visualization Design for Map Use on Future Mobile Devices (Presentation at Samsung Electronics, Dec. 8, 008) Computer Architecture & Network Lab 9

10 Instruction Set Architecture (ISA) Application S/W library Operating System complier assembler ISA H/W Computer Architecture & Network Lab 10

11 Instruction Set Architecture as an ADT the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation. - Amdahl, Blaauw, and Brooks, 1964 instruction instruction.. instruction instruction Registers + Memory instruction instruction.. instruction Computer Architecture & Network Lab 11

12 Instruction Set Architecture as an ADT Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B 63 Memory 63 Memory r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) add r 1, r, r 3 r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) Before Register and Memory After Register and Memory Computer Architecture & Network Lab 1

13 Instruction Set Architecture as an ADT Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B 63 Memory 63 Memory r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) lw r, 1(r 0 ) r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) Before Register and Memory After Register and Memory Computer Architecture & Network Lab 13

14 Instruction Set Architecture as an ADT Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B 63 Memory 63 Memory r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) sw r 3, 0(r 0 ) r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) Before Register and Memory After Register and Memory Computer Architecture & Network Lab 14

15 Instruction Set Architecture as an ADT Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B 63 Memory 63 Memory r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) beq r 0, r 1, r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) Before Register and Memory After Register and Memory Computer Architecture & Network Lab 15

16 Instruction Set Architecture as an ADT Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B 63 Memory 63 Memory r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) j 15 r r r 1 r 0 PC Registers (j 15) (beq r 0, r 1, ) (sw r 3, 0(r 0 )) (lw r, 1(r 0 )) (add r 1, r, r 3 ) Before Register and Memory After Register and Memory Computer Architecture & Network Lab 16

17 Design Techniques Design Techniques Engineering methodology Correctness criteria Evaluation methods Technology trends Computer Architecture & Network Lab 17

18 Design Techniques Processor Processor Sequential execution Pipelined execution Out-of-order execution Speculative execution I-cache D-cache Cache Design Memory Hierarchy Unified cache To main memory system Input/Output and Storage Computer Architecture & Network Lab 18

19 Design Techniques processor processor I-cache D-cache I-cache D-cache Main Memory Main Memory Unified cache Unified cache Interconnection Network Cache Coherence, Synchronization, Interconnection network Computer Architecture & Network Lab 19

20 Engineering methodology Rule 1 : Identify and optimize the common case Rule : Make the rare case correct and reasonably fast Computer Architecture & Network Lab 0

21 Correctness criteria Examples Pipelined execution : pipelined execution of instructions is correct if the results is as if the instructions were executed sequentially Cache memory : execution of instructions on a system with cache memory is correct if the results is as if the instructions were executed on the same system but without cache memory We ll see a lot of as if s Computer Architecture & Network Lab 1

22 Performance Evaluation Methods Performance types Time Rate Ratio response time execution time throughput : MIPS, MFLOPS bandwidth : Mbps relative performance Computer Architecture & Network Lab

23 Technology Trends IBM System 360/50 DEC VAX 11/780 Apple imac Pentium MIPS 64 KB $1M 1 MIPS(peak) 0.5 MIPS(estimated) 1 MB $00K 700 MIPS(peak) 47 MIPS(estimated) 3 MB $19(September 1998) ~15000 MIPS(peak) ~6000 MIPS(estimated) 51 MB < $1000 $6.6M per MIPS $16M per MB $00K to $400 per MIPS $00K per MB $1.75 to $.90 per MIPS $38 per MB $0.07 to $0.17 per MIPS < $ per MB Computer Architecture & Network Lab 3

24 A Big Picture Randy H. Katz, Tech Titans Building Boom, IEEE Spectrum, Vol. 46, No., Feb. 009, pp Computer Architecture & Network Lab 4

25 A Big Picture Randy H. Katz, Tech Titans Building Boom, IEEE Spectrum, Vol. 46, No., Feb. 009, pp Computer Architecture & Network Lab 5

26 Embedded Processors Computer Architecture & Network Lab 6

27 Embedded Processors From Flash and the Embedded Space by Grady Lambert Computer Architecture & Network Lab 7

28 Embedded Processing Example Impact sensors Airbags Brakes Engine Central controller Navigation & entertainment From Prof. Behrooz Parhami s lecture notes Computer Architecture & Network Lab 8

29 Automotive Electronic System Information Systems Telematics Fault Tolerant MOST Firewire Mobile Communications Fire Wall DAB Navigation Access to WWW Body Electronics Body Functions Fail Safe Air Conditioning CAN Lin Gate Way Theft warning Door Module Light Module ABS Body Electronics Driving and Vehicle Dynamic Functions Fault Functional CAN TTCAN Steer by Wire Gate Way Shift by Wire Engine Management Brake by Wire FlexRay From Design of Embedded Systems: Methodologies, Tools and Applications by Alberto Sangiovanni-Vincentelli Computer Architecture & Network Lab 9

30 Technology Trends Five components of a computer system Computer Architecture & Network Lab 30

31 Chip Manufacturing Process Chip cost = Die cost + Testing cost + Packaging cost Final test yield Computer Architecture & Network Lab 31

32 Processor Performance Trends Computer Architecture & Network Lab 3

33 Performance Improvements by Advances on Lithography (VLSI) Technology 0.6 µm 306 mm² 5.5M Tx µm 195 mm² 5.5M Tx µm 148 mm² 3.1M Tx µm 90 mm² 3.1M Tx 1996 Computer Architecture & Network Lab 33

34 Processor Computations/Energy Trends J. G. Koomey, et al. Outperforming Moore s Law IEEE Spectrum, Vol. 47, No. 3, Mar. 010, pp Computer Architecture & Network Lab 34

35 Processor Clock Rate/Power Trends Power = Capacitive load Voltage Frequency Computer Architecture & Network Lab 35

36 DRAM Technology Trends (4x in three years) 60% increase/year (4x in four years) year size cycle time Kbits 50 ns Kbits 0 ns Mbits 190 ns Mbits 165 ns Mbits 145 ns Mbits 15 ns Mbits 100 ns Computer Architecture & Network Lab 36

37 Transistors Per Die Trends Source: Computer Architecture & Network Lab 37

38 Lithography Technology Trends Source: Computer Architecture & Network Lab 38

39 Die Size Trends Source: Computer Architecture & Network Lab 39

40 Defect Density Trends Source: Computer Architecture & Network Lab 40

41 4 Die Cost f (Die size ) Die Cost and Yield 0 Defects 0 Bad Die 64 Gross Die 9% Yield 0 Defects 16 Bad Die 54 Gross Die 70% Yield Source: Computer Architecture & Network Lab 41

42 Hard-Disk Technology Trends Source: IBM HDD Evolution by Ed Grochowski at Almaden Disk density: 1.50x x per year (4x in three years) Computer Architecture & Network Lab 4

43 Hard-Disk Technology Trends Will Hard drives Finally Stop Shrinking? by Linda Dailey Paulson (IEEE Computer, May 005) Computer Architecture & Network Lab 43

44 Future Outlook of Flash Memory Source: Scott Deutsch (SanDisk), Bringing Solid State Drives to Mainstream Notebooks, Flash Memory Summit 007. Computer Architecture & Network Lab 44

45 Internet Technology Trends in DWDM (Dense wavelength Division Multiplexing) X/1 months X/9 months X/6 months Source: Lawrence G. Roberts, Beyond Moore's Law: Internet Growth Trends, IEEE COMPUTER JANUARY 000, pp Computer Architecture & Network Lab 45

46 Pitfalls of Computer Technology Forecasting DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more. Microsoft, K ought to be enough for anybody. Bill Gates, 1981 Computers in the future may weigh no more than 1.5 tons. Popular Mechanics I think there is a world market for maybe five computers. Thomas Watson, IBM Chairman, 1943 There is no reason anyone would want a computer in their home. Ken Olsen, DEC founder, 1977 The 3-bit machine would be an overkill for a personal computer. Sol Libes, ByteLines From Prof. Behrooz Parhami s lecture notes Computer Architecture & Network Lab 46