ECE 468 Computer Architecture and Organization Lecture 1

Transcription

1 ECE 468 Computer Architecture and Organization Lecture 1 September 7, 1999 ece 468 Intro.1 What is "Computer Architecture" Co-ordination of levels of abstraction Application Compiler Instr. Set Proc. Operating System Digital Design Circuit Design I/O system Instruction Set Architecture Under a set of rapidly changing Forces ece 468 Intro.2

2 Forces on Computer Architecture Technology Programming Languages Applications Computer Architecture Operating Systems History (A = F / M) ece 468 Intro.3 Technology Trend: Clock rate 1,000 Clock rate (MHz) R10000 Pentium100 i8086 i80286 i80386 i8080 i8008 i % per year ---> today s PC is yesterday s Supercomputer ece 468 Intro.4

3 Technology Trends: Transistor Count Growth 100,000,000 Transistors 10,000,000 1,000, ,000 i80286 R10000 Pentium i80386 R3000 R2000 i ,000 i8080 i8008 i4004 1, % per year, order of magnitude more contribution in 2 decades - More and more functions can be performed by a CPU - Similar story for storage: capacity increased by 1000x over ten years, speed only 2x ece 468 Intro.5 Technology => dramatic change Processor logic capacity: about 30% per year clock rate: about 20% per year Memory capacity: about 60% per year (4x every 3 years) Memory speed: about 10% per year Cost per bit: improves about 25% per year Disk capacity: about 60% per year ece 468 Intro.6

4 Performance Trends 1000 Performance Supercomputers Mainframes Minicomputers Microprocessors Year ece 468 Intro.7 Processor Performance (SPEC) performance now improves - 50% per year (2x every 1.5 years) RISC Performance RISC introduction Intel x %/yr Year ece 468 Intro.8 Did RISC win the technology battle and lose the market war?

5 CPU and LAN Performance Relative Performance CPU (spec) Mb MIPS M/120 DEC Alpha 100 Mb FDDI 1 Gb ATM LAN Year ece 468 Intro.9 Computer Arch. = Instruction Set Arch. + Organization Computer Design Instruction Set Design Machine Language Compiler View "Computer Architecture" "Instruction Set Processor" "Building Architect" Computer Hardware Design Machine Implementation Logic Designer's View "Processor Architecture" "Computer Organization" "Construction Engineer" ece 468 Intro.10

6 Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaw, and Brooks, Organization of Programmable Storage SOFTWARE -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions ece 468 Intro.11 MIPS R3000 Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special R0 - R31 PC HI LO Instruction Format OP OP OP rs rt rd sa funct rs rt immediate target ece 468 Intro.12

7 Organization Logic Designer's View -- Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units, etc. -- Ways in which these components are interconnected -- nature of information flows between components -- logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level Description ISA Level FUs & Interconnect ece 468 Intro.13 Example Organization TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 SuperSPARC MBus Module Floating-point Unit Integer Unit L2 $ CC MBus Controller Inst Cache Ref MMU Bus Interface Data Cache Store Buffer L64852 DMA Cards MBus control M-S Adapter SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy ece 468 Intro.14

8 Measurement and Evaluation Design Architecture is an iterative process -- searching the space of possible designs -- at all levels of computer systems Analysis Creativity Cost / Performance Analysis Bad Ideas Good Ideas Mediocre Ideas ece 468 Intro.15 Levels of Representation High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Control Signal Spec Machine Interpretation ece 468 Intro.16

9 ECE468: Course Overview Computer Design Instruction Set Deign Machine Language Compiler View "Computer Architecture" "Instruction Set Processor" "Building Architect" Computer Hardware Design Machine Implementation\ Logic Designer's View "Processor Architecture" "Computer Organization" Construction Engineer Few people design computers! Very few design instruction sets! Many people design computer components. Very many people are concerned with computer function, in detail. ece 468 Intro.17 ECE468:So what's in it for me? In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary. Insight into fast/slow operations that are easy/hard to implementation hardware Experience with the design process in the context of a large complex (hardware) design. Functional Spec --> Control & Datapath Learn how to completely design a correct single processor computer. No magic required to design a computer Foundation for students aspiring to work in computer architecture. Others: solidifies an intuition about why hardware is as it is. ece 468 Intro.18

10 The Memory Controller Memory SIMMs Memory Bus MBus Disk MBu s MBu s Slot 1 Slot 0 Slot 1 Slot 0 Slot 3 Slot 2 Tape MSBI SEC MACIO SCSI Bus Keyboard & Mouse Floppy Disk External Bus ece 468 Intro.19 Levels of Organization Computer SPARC Processor Control Memory Devices Input Datapath Output ece 468 Intro.20

11 The Underlying Network Memory Controller Memory Bus MSBI Processor Bus: MBus SEC Standard I/O Bus: Sun s High Speed I/O Bus: SCSI Bus MACIO Low Speed I/O Bus: External Bus ece 468 Intro.21 Processor and Caches MBus Module MBus SuperSPARC Processor MBu s MBu s Slot 1 Slot 0 Registers Datapath Internal Cache Control External Cache ece 468 Intro.22

12 Memory Memory Controller SIMM Slot 0 SIMM Slot 1 SIMM Slot 2 SIMM Slot 3 SIMM Slot 4 SIMM Slot 5 SIMM Slot 6 SIMM Slot 7 Memory Bus SIMM ece 468 Intro.23 Input and Output (I/O) Devices SCSI Bus: Standard I/O Devices : High Speed I/O Devices External Bus: Low Speed I/O Device Disk Slot 1 Slot 3 Tape Slot 0 Slot 2 SEC MACIO SCSI Bus Keyboard & Mouse Floppy Disk External Bus ece 468 Intro.24

13 Standard I/O Devices SCSI = Small Computer Systems Interface A standard interface (IBM, Apple, HP, Sun... etc.) Computers and I/O devices communicate with each other The hard disk is one I/O device resides on the SCSI Bus Disk Tape SCSI Bus ece 468 Intro.25 High Speed I/O Devices is SUN s own high speed I/O bus SS20 has four slots where we can plug in I/O devices Example: graphics accelerator, video adaptor,... etc. High speed and low speed are relative terms Slot 1 Slot 3 Slot 0 Slot 2 ece 468 Intro.26

14 Slow Speed I/O Devices The are only four slots in SS20-- seats are expensive The speed of some I/O devices is limited by human reaction time--very very slow by computer standard Examples: Keyboard and mouse No reason to use up one of the expensive slot Keyboard & Mouse Floppy Disk External Bus ece 468 Intro.27 Summary All computers consist of five components Processor: (1) datapath and (2) control (3) Memory (4) Input devices and (5) Output devices Not all memory are created equally Cache: fast (expensive) memory are placed closer to the processor Main memory: less expensive memory--we can have more Input and output (I/O) devices has the messiest organization Wide range of speed: graphics vs. keyboard Wide range of requirements: speed, standard, cost... etc. Least amount of research (so far) ece 468 Intro.28