CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design John Lazzaro (not a prof - John is always OK) TA: Eric Love www-inst.eecs.berkeley.edu/~cs152/ Play: 1

2 Today s lecture plan... Class Outline. What we ll be doing this semester. Short Break. Single-cycle processor design. Preliminaries... prep for Thursday. 2

3 Nvidia Tegra K1 Tech Talk 5:30 PM this Thursday in the Woz. Tegra K1 remixes the Kepler GPU architecture for lowpower SOCs. 3

4 Nvidia Tegra K1 This class prepares you to be on a team like the one at Nvidia that designed this chip. 4

5 Nvidia Tegra K1 This is true even if your goal is to be in the group that designs circuits or writes software... for the chip. 5

6 Lecture topics GPU architecture: Apr 15/17. Dynamic scheduling: Apr 1/3, 8/10. Memory System: (February) Array of 192 CUDA cores in the Kepler GPU ARM A15 CPU Cores (4+1) Hierarchical Memory System 6

7 And other topics What do we get to do? 7

8 Timeline For 9 weeks, lectures and labs only. Lab 1: Pipelines: Lab 2: Caches: Midterm March 18: Complete HW1 and take Midterm 1 Lab 3: Dynamically-Scheduled CPU Design: Midterm II May 1: Complete HW2 and take Midterm 2 8

9 About the labs Rocket, a RISC-V ( risk five ) chip project Professor Krste Asanovic directs ASPIRE (microprocessor design research project). CS 152 uses ASPIRE software tools and CPU designs. ASPIRE graduate students take turns with TA duties. RISC-V: a new instruction set architecture (ISA) Extensive software support: gcc port, disassemblers, etc. Chisel: Professor Bachrach s hardware description language Labs will use Chisel simulators of RISC-V CPU designs 9

10 Open-source... on the web... Warning: It s tricky to compile... 10

11 Each lab has two parts Directed portion Teaches you how to use the tools. Helps you understand the material. Not doing well puts you in C grade territory. Not team labs - you work alone. Open-ended portion Define a project and work on it for several weeks. High bar for an A grade (about 10% of class). Solid, competent work gets you a B grade. Falls out of EECS upper-division GPA guidelines. 11

12 About exams: Two mid-terms and no final. Mid-term start time TBD 12

13 About homeworks: 13

14 Discussion sections Focused on labs. Go to the section you can make. TA: Eric Love (ASPIRE graduate student). Essential for doing well in the labs. John does Q&A for lecture materials, midterms, hw. What constitutes cheating on labs? 14

15 And more generally... 15

16 Required text... 5th edition only On reserve in library. See class website for readings for each lecture... 16

17 Recommended text... On reserve in library. Any edition is fine... whatever you used for 61C. 17

18 Administriva, Part I Piazza is our all-to-all communication media. Send John if he hasn t contacted you about it. Class website is our archival media. Lecture slides, labs, due dates... add /sp14 to URL. Tools run on EECS instructional machines. Get the account form from Eric in discussion. Laptop/tablet/smartphone in class. Fine for note taking and class-related activities. Every lecture will have a short break in the middle. Please wait till the break for heavy-duty multitasking. 18

19 Administriva Rain Checks Expect updates soon on the following items: Course grading Breakdown between mid-terms and labs, more details on how we will grade the labs. Office hours For Eric and John. Deadlines policies. Our late policies for labs, and procedures if you can t make it to one of the mid-terms. Wait list. We hope we can let everyone in, but we don t know for sure yet. If you are planning to drop, John. 19

20 Break Play: 20

21 Instruction Set Architecture The labs will use the RISC-V ISA... Lectures examples will mostly use the MIPS ISA. 21

22 New successful instruction sets are rare software instruction set hardware Implementors suffer with original sins of ISAs, to support the installed base of software. 22

23 Instruction Sets: A Thin Interface Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10 Software Hardware Application (itunes) Compiler Assembler Processor Memory Operating System (Mac OS X) Datapath & Control I/O system Instruction Set Architecture Digital Design Circuit Design Transistors R-Format Fieldsize: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Bitfield: opcode rs rt rd shamt funct Binary: In Hexadecimal: 012A

24 Hardware implements semantics... Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10 Instruction Fetch Instruction Decode Operand Fetch Execute Fetch next inst from memory:012a4020 opcode rs rt rd shamt funct Decode fields to get : ADD $8 $9 $10 Retrieve register values: $9 $10 Add $9 to $10 Result Store Next Instruction Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. 24

25 ADD syntax & semantics, as seen in the MIPS ISA document. 25

26 Memory Instructions: LW $1,32($2) Instruction Fetch Instruction Decode Operand Fetch Execute Fetch the load inst from memory opcode rs rt offset I-Format Decode fields to get : LW $1, 32($2) Retrieve register value: $2 Compute memory address: 32 + $2 Result Store Next Instruction Load memory address contents into: $1 Prepare to fetch instr that follows the LW in the program. Depending on load semantics, new $1 is visible to that instr, or not until the following instr ( delayed loads ). 26

27 LW syntax & semantics, as seen in the MIPS ISA document. 27

28 Branch Instructions: BEQ $1,$2,25 Instruction Fetch Instruction Decode Operand Fetch Execute Fetch branch inst from memory opcode rs rt offset I-Format Decode fields to get: BEQ $1, $2, 25 Retrieve register values: $1, $2 Compute if we take branch: $1 == $2? Result Store Next Instruction ALWAYS prepare to fetch instr that follows the BEQ in the program ( delayed branch ). IF we take branch, the instr we fetch AFTER that instruction is PC PC == Program Counter 28

29 BEQ syntax & semantics, as seen in the MIPS ISA document. 29

30 define: The Architect s Contract To the program, it appears that instructions execute in the correct order defined by the ISA. As each instruction completes, the machine state (regs, mem) appears to the program to obey the ISA. What the machine actually does is up to the hardware designers, as long as the contract is kept. 30

31 Single Cycle CPU Design Preliminaries... 31

32 Single cycle data paths: Assumptions Processor uses synchronous logic design (a clock ). clk f T 1 MHz 1 μs 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns All state elements act like positive edgetriggered flip flops. D Q Reset? clk 32

33 Review: Edge-Triggered D Flip Flops D Q Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle. CLK D Q This abstraction is sufficient for the 2014 CS 152! 33

34 If you are a circuit designer... D Q Not required for 2014 CS A flip-flop samples right before the edge, and then holds value. clk Sampling circuit clk Holds value clk clk clk clk clk Clock to Q delay results fr 16 Transistors: Makes an SRAM look compact! What do we get for the 10 extra transistors? Clocked logic semantics. clk CS 250 L3: Timing UC Regents Fall 2013 UCB 34

35 If you are a CS 150 veteran... D Q Not required for 2014 CS Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle. module ff(d, Q, CLK); CLK input D, CLK; output Q; reg Q; (posedge CLK) Q <= D; endmodule 35

36 define: Single-cycle datapath clk All instructions execute in a single cycle of the clock (positive edge to positive edge) Advantage: a great way to learn CPUs. Drawbacks: unrealistic hardware assumptions, slow clock period 36

37 Thursday: Complete single-cycle... and maybe get to other listed topics. 37