SPTWIMAXCC1E Multi-Standard Baseband AMC Channel Card

Transcription

1 Product Brief Document Number: SPTWIMAXCC1EPB Agile Number: Rev. 0, 04/2007 SPTWIMAXCC1E Multi-Standard Baseband AMC Channel Card The Freescale SPTWIMAXCC1E multi-standard baseband advanced mezzanine card (AMC) channel card is a system development platform for worldwide interoperability for microwave access (WiMAX) and wideband code division multiple access (WCDMA) markets. The channel card has a double AMC form factor for use as a standalone card or as part of an advanced TCA platform. It is designed for use as a channel card module for a base station system solution or as a standalone platform for Pico-base station implementation. The platform is designed around the Freescale MPC8555E PowerQUICC III (PQIII) integrated communication processor and the StarCore MSC bit fixed-point DSP. The MPC8555E processor implements the MAC layer processing for WiMAX and WCDMA and the frame protocol processing for WCDMA. Two DSPs implement the upper PHY layer processing, including user domain processing and frequency domain signal processing for WiMAX applications and symbol rate processing for WCDMA applications. The channel card uses a field-programmable gate array (FPGA) to provide interconnection solutions on the Contents 1 Example Application: WiMAX Reference System Features Board-Level Features Features of the PowerQUICC III Processor Subsystem5 2.3 Features of the StarCore DSP Subsystem Features of the Algorithmic FPGA Features of the SerDes FPGA Programmable Device References and Board Interface Features SPTWIMAXCC1E Block Diagram SPTWIMAXCC1E AMC Channel Card Assembly Compliance and Certification , Inc., All rights reserved.

2 board and algorithmic integration for time domain processing or for chip rate processing. The interconnectivity delivered through the FPGA offers extension to an RF module. In addition, the FPGA has access to high bandwidth DDR2 for memory storage. A serializer/deserializer (SerDes) FPGA provides a serial RapidIO (srio) connection to the board AMC connector. Plugged into an ATCA platform or µtca rack, the channel card interfaces with other AMC platforms, giving it scope for future expansion and development. Data flow for downlink processing comes onto the board from the 1 Gbps Ethernet port of the MPC8555E processor, either through the RJ45 connector or the AMC connector. After PHY processing, the data can be transmitted through the RF module connected to the channel card. The data flow for uplink processing is the reverse path. Figure 1. Freescale Multi-Standard AMC Channel Card 2

3 Example Application: WiMAX Reference System 1 Example Application: WiMAX Reference System The channel card is designed to implement multiple wireless interface standards. However, WiMAX is its key target technology. The on-board MPC8555E processor, the DSPs, and the FPGAs along with the on-board connectivity and the backplane connectivity are designed to meet the requirements of a single-sector 10 MHz TDD WiMAX system. If this card is combined with other AMC cards from Freescale or third-party partners, then a complete sandbox base station system can be built. For example, if this card is connected to an 8548AMC card and an RF reference card, the complete MAC-CS, MAC-CPS, scheduler, and PHY components of a WiMAX base station can be developed. MAC CS MPC8548 MPC8548AMC Eth MAC CPS MPC8555E srio PHY Processing MSC8126 Channel Card AMC FPGA RF RF FPGA WiMAX AMC Figure 2. Freescale WiMAX Reference System 2 Features The SPTWIMAXCC1E channel card architecture is built around four programmable blocks: PowerQUICC III processor subsystem. A single 833 MHz MPC8555E providing the required performance for MAC processing. One Ethernet link connects to port 0 of the AMC interface and another Ethernet link connects to the front panel. Starcore DSP subsystem. Two 500 MHz quad-core MSC8126 DSPs provide upper-layer PHY processing. Algorithmic FPGA. This FPGA is large enough to provide lower PHY functionality and to route data to various parts of the board and external interfaces. 3

4 Features SerDes FPGA. Provides serializer/deserializer (SerDes) connectivity and is routed to two 4x serial RapidIO interfaces (ports 4:7 and ports 8:11) on the AMC interface. 2.1 Board-Level Features The AMC channel card is compliant with the AMC.0 (Rev. 1.0) specifications for the height and width of a full-height dual-width module. The only exception is the population of the Mictor connector on side 2, which violates height restrictions. Note that this connector is not needed for normal operation of the AMC channel card. Board-level features are as follows: Target use: benchmarking, proof of concept Form factor: Double AMC size Layer count: 14 layers PCB thickness: 1.6 mm Component side 2: 2.6 mm Component side 1: Zone 1: mm Zone 2: mm Power supplies: Card supply: 12 V and 3.3 V IPMCV provided by ATCA platform (ATCA mode) Card supply: 12 V and 3.3 V IPMCV provided by the power adaptor card (standalone mode) On-board supply through variable voltage regulators providing: Dedicated 3.3 V for IOs Separated 2.5 V for DDR1 and GigE PHY IO devices Dedicated 1.8 V for DDR2 Single 1.5 V for Stratix GX core, SerDes transceiver, and single PHY GigE core Dedicated 1.5 V for Stratix GX PLLs Separated 1.2 V for MPC8555E, Stratix II, and MSC8126 cores Dedicated 1 V for Quad-PHY GigE core voltage JTAG: Single JTAG header for access to the MPC8555E Chained JTAG header for access to the MSC8126 DSPs Single JTAG header for Stratix II flash programming Chained JTAG header for FPGAs and LB/DSI CPLD Single JTAG header for reset CPLD Debug support: All devices have independent JTAG access 4

5 Features Real-time debug is supported on the Stratix II FPGA algorithmic through the MICTOR connector Connectors: Connector for RF interface AMC interface Single universal asynchronous receiver/transmitter (UART) connector for multiple UARTS Analog-to-digital convertor connector, which is a high-density 160-pin connector from Samtec (part no. SEAF S A). It is directly connected to the algorithmic FPGA with the following connections: Two sets of 16 differential pairs for a total of 32 connections. Eight differential pairs connected to clocks on the FPGA. 32 standard I/O connections. Four lines set up for a serial link. 2.2 Features of the PowerQUICC III Processor Subsystem The PowerQUICC III processor subsystem consists of an MPC8555E processor running at 833 MHz to perform MAC layer processing, network interfacing, and overall channel card control functions. Features of the MPC8555E are as follows: Communication processor module running (CPM) at 333 MHz 2 FCCs allow 100 Mbps Ethernet s ports to interconnect with the MSC8126 DSP GigE port connected to an RJ45 and a GigE port connected to the AMC connector Security processor Two RS-232 ports 16 Mbyte flash memory 256 Mbyte DDR1 module, upgradeable to 1 Gbyte Bootstrap from flash memory or TFTP from network Download of DSP images 2.3 Features of the StarCore DSP Subsystem The StarCore DSP subsystem consists of two MSC8126 DSPs running at 500 MHz to perform the symbol rate portion of the PHY layer processing: The 64-bit system bus of each MSC8126 is connected to the algorithmic FPGA JTAG ports are chained RS-232 port for each DSP Each DSP has 100 BaseT port connected to RJ45 or to 100 BaseT port of the MPC8555E DSI bus is accessible from MPC8555E local bus Bootstrapped through the DSI by the MPC8555E 5

6 Features 2.4 Features of the Algorithmic FPGA The algorithmic FPGA is one EP2S180F1508C3N (Stratix II Altera FPGA) to perform the algorithmic and chip rate portion of the PHY layer processing. Features of the algorithmic FPGA are as follows: 1.2 V, CMOS90nm #180K equivalent logic elements Up to 9 Mbit on-chip memory and 450 MHz internal clock Two system bus interfaces with the MSC8126 DSI bus interface for slave communication with the MPC8555E processor One high-speed data interface (HSDI) with FPGA SerDes double 32-bit data bus Connectivity to RF module through an ADC interface Double 7 segment display available 256 Mbyte DDR2 module, upgradeable to 1 Gbyte One UART port 2.5 Features of the SerDes FPGA The SerDes FPGA is one EP1SGX40DF1020C5 Stratix GX Altera FPGA to perform SerDes interfaces: Up to 3.4 Mbit on-chip memory Two high speed transceiver channels, dedicated to SerDes capability at a data rate of up to Gbps full duplex HSDI (64-bit Tx/Rx) with FPGA algorithmic DSI bus interface for slave communication with the MPC8555E processor srio interface supporting 1X srio up to Gbauds or 4X srio up to 2.5 Gbauds EPM240T100C5N (CPLD) to perform on-board power sequencing and reset sequencing EPM2210F324C3N (CPLD) to perform MPC8555E local bus interfacing with MSC8126 and FPGA DSI buses 2.6 Programmable Device References and Board Interface Features Table 1 lists the features of the SPTWIMAXCC1E AMC channel card programmable devices, and Table 2 lists the features of the board interfaces. Table 1. SPTWIMAXCC1E AMC Channel Card Programmable Device References MPC8555E DDR1 Manufacturer Part Number Web Site Manufacturer Part Number Web Site, Inc. KMPC8555EVTAPF Micron MT8VDDT3264HDY

7 Table 1. SPTWIMAXCC1E AMC Channel Card Programmable Device References (continued) Features Two MSC8126 DSPs FPGA(A) (Algorithmic) Manufacturer Part Number Web Site Manufacturer Part Number Web Site, Inc. MSC8126VT Altera EP2S180F1508C5N DDR2 FPGA(S) (SerDes) Manufacturer Part Number Web Site Manufacturer Part Number Web Site Samsung M CZ3-CD500 Altera EP1SGX40DF1020C5 Table 2. SPTWIMAXCC1E AMC Channel Card Board Interfaces Channel Card Component Protocol Interface Physical Interface MPC8555E MSC8126 MSC8126 FPGA(A) (Algorithmic) FPGA(S) (SerDes) GigE 1000BaseX GigE 1000BaseT UART RS-232 UART RS-232 JTAG COP UART RS-232 Header FE 100BaseT RJ45 JTAG EOnCE Header UART RS-232 Header FE 100BaseT RJ45 JTAG EOnCE Header ADC LVDS/LVTTL Connector UART RS-232 Header JTAG JTAG Header Debug General pins Header SerDes XAUI AMC ports 4 11 JTAG JTAG Header 7

8 SPTWIMAXCC1E AMC Channel Card Assembly 2.7 SPTWIMAXCC1E Block Diagram Under typical operating conditions for a downlink chain, the MPC8555E terminates 1000BaseT Ethernet packet traffic from the host through its RJ45 connector or the AMC connector. The subsequent data is placed into MPC8555E external DDR memory. After MAC processing, the data is distributed to the MSC8126 DSPs for upper-layer PHY processing through the MSC8126 DSI port. A CPLD performs the local bus-to DSI-translation. After MSC8126 processing, the data is forwarded through the MSC8126 system bus to the FPGA for additional PHY processing, or it is forwarded to the RF interface through the ADC connector. See the block diagram in Figure 3. RS232 RS232 RJ45 RJ45 RJ45 PHY MPC8555E UART UART Local Bus GigE GigE 64-bit DDRI-SODIMM CPLD 32-bit Flash Port0 AMC RS232 JTAG RS232 JTAG RS232 ADC MSC8126A DSI FEnt UART JTAG System Bus MSC8126B DSI FEnt UART JTAG System Bus 64-bit 64-bit DSI Algorithmic FPGA System Bus HSDI System Bus HSDI UART ADC 64-bit Clocks DDRII-SODIMM 64-bit 64-bit Flash CPLD Reset DSI SERDES FPGA HSDI HSDI srio srio MMC µcontroller Port[4:7] Port[8:11] I 2 C Figure 3. Block Diagram of the SPTWIMAXCC1E AMC Channel Card 3 SPTWIMAXCC1E AMC Channel Card Assembly Figure 4 shows the dimensions of the AMC channel card, in millimeters. 8

9 SPTWIMAXCC1E AMC Channel Card Assembly REV S/N FREESCALE All Dimensions in Millimeters Figure 4. Channel Card Assembly 9

10 Compliance and Certification 4 Compliance and Certification The channel card currently is compliant with the form factor and power considerations of the AMC.0 specification. Note the following restrictions: The module management controller (MMC) is not populated. Select the MMC bypass option on the carrier. The channel card cannot be hot swapped. The SPTWIMAXCC1E AMC channel card is CE/UL certified. 10

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