Best Practices for Architecting Embedded Applications in LabVIEW Jacques Cilliers Applications Engineering

Transcription

1 Best Practices for Architecting Embedded Applications in LabVIEW Jacques Cilliers Applications Engineering

2 Overview of NI RIO Architecture PC Real Time Controller FPGA 4

3 Where to Start? 5

4 Requirements These are the key requirements that typically drive a design: Data acquisition rates Channel count Control loop rates and latencies Level and timing of data analysis o Offline, online, inline Data destinations o Log all raw data to disk o Display all data on PC UI 6

5 Build with Modular Processes Break up the application into numerous (typically 5-8) independent, free-running processes Each process is a loop, in a subvi Each process should be responsible for one aspect of the system Limit the state data that needs to be shared between processes 7

6 Assign Processes to the Right Target PC RT FPG A PC Real-Time FPGA Offline processing and analysis User Interface Long-term data storage Enterprise interface o o SQL Database OPC Online analysis Temporary data storage Closed-loop control (100 us ms time scales) Peripheral interface o o o Modbus Serial CAN/LIN Inline analysis Closed-loop control (10s of ns us time scales) Anything related to safety or time-critical operation Digital hardware interface o o I2C SPI 8

7 I/O Modules I/O Modules Accessing IO: NI Scan Engine Provides single-point access to I/O channels using a scan that stores and updates data in a global memory map Updates all values concurrently at a single rate (Scan Period) CompactRIO Scan Mode Interface LabVIEW Real-Time RT VI I/O Variables NI Scan Engine I/O memory table FPGA RIO Scan Interface 9

8 Accessing IO: Scan Engine vs FPGA Scan Engine: FPGA Continuous single point acquisition Scalar data Scan rates below ~1 KHz o CPU usage scales with scan rate higher-performance targets can handle higher scan rates. Pre-written, easy access to data No FPGA programming required Custom triggering Waveform or scalar data Acquisition rates to ~ 1 MHz Requires writing FPGA code, allows full control 10

9 Accessing IO: Hybrid Mode Can choose what IO mode to use for each module Location in project tree determines mode Scan Interface Mode I/O LabVIEW FPGA Interface Mode I/O 11

10 Available LabVIEW Data Communication APIs Local Process Local Variable Global Variable Single-Process Variable Functional Global Variable Queues Notifiers RT FIFOs User Events Data Value Reference Shared Memory Current Value Table (CVT)* Tag Bus(*) NI Pipes Network TCP UDP Network Streams Network Variable Dynamic Variables Time-Triggered Variable Web Services Datasocket Simple TCP Messaging (STM)* Asynchronous Message Communication (AMC)* FTP HTTP WebDAV FPGA Memory Item Register Target Scoped FIFO VI VI Defined FIFO DRAM FIFO DMA FIFO Read/Write Controls User Defined IO Variables Peer-to-Peer (P2P) PXImc *SE Maintained 12

11 Three Fundamental Communication Paradigms Lossy Current value Lossless High throughput Buffered data Reliable delivery Low latency 13

12 Three Fundamental Communication Paradigms Global and Local Variables Network Published Shared Variables Tag Bus Current Value Table (CVT) FPGA Registers Scan Engine I/O Variables Network Streams TCP/IP Queues RT FIFOs FPGA FIFOs TCP and UDP Network Streams Queues and Notifiers User Events RT FIFOs FPGA / RT FIFOs FPGA Handshakes FPGA IRQs 14

13 FPGA Internal Communication Tags: Registers Local\Global Variables Messages: Handshake Target (or VI)-scoped FIFO PC RT FPG A Streams: Target (or VI)-scoped FIFO Memories 15

14 FPGA External Communication Tags: FPGA Front Panel User-Defined Variable (if using Scan Engine) Messages: Interrupt DMA FIFO PC RT FPG A Streams: DMA FIFO 17

15 RT Internal Communication Tags: Current Value Table Single-Process Shared Variables (no RT FIFO) Global Variables Messages: Queue RT FIFO User Events Streams: RT FIFO Queue Single-Process Shared Variable (with RT FIFO) PC RT FPG A 18

16 RT to HMI Communication Tags: Network-Published Shared Variable Web Service Messages: Network Stream STM PC RT FPG A TCP Web Service Streams: Network Stream UDP TCP 21

17 Typical RT Modules Acquisition/Control (main logic) Incoming Message Handler System Health Monitor Central Error Handler Debug Trace Logger Watchdog 23

18 Error Management Each process should attempt to handle (or ignore) its own errors If the scope of an error requires higher-level action, this action should be triggered by the central error handler One and only one process should log errors, all other processes forward errors to be logged Leverage existing reference designs and components Sample Projects Structured Error Handler Tag Bus 24

19 Central Error Handling Framework Specific Command Receiver Loop Handler UI message handling loop Specific Watchdog Loop Handler Monitoring Loop Specific Handler 25

20 System Health Continuously monitor and report critical system health tags CPU usage Memory usage Disk usage Delete older log/acquisition files if disk usage is high Controlled restart if available memory or CPU usage crosses a threshold Consider also using this process to control LEDs to visually inform users of system status 26

21 Trace Logging Single process responsible for logging trace data Expose a simple API for other processes to send trace strings This permits changes to the logging method without impacting other processes Simplifies field debugging Consider Syslog for network transmission of trace data 27

22 Watchdogs A watchdog timer is a hardware counter that interfaces with the embedded software application to detect and recover from software failures A user can then: Reboot real-time target automatically Perform user-defined recovery actions Two types of watchdogs with NI Real-Time hardware: LabVIEW Real-Time Watchdog Real-Time <-> FPGA Watchdog (FPGA Fail Safe Design) 29

23 LabVIEW Real-Time Only Watchdog Uses hardware timer built into CompactRIO hardware Reset = True reboots system if the watchdog process is starved 30

24 LabVIEW Real-Time Watchdog Enable occurrence in expiration actions Configure appropriate watchdog timeout and Watchdog Whack loop period 31

25 Real-Time <-> FPGA Watchdog Reset timer Put control loop into a safe state, and reset system 32

26 Configuration Any item that is a constant on the diagram or entered via the front panel of an RT VI should be considered for inclusion in a configuration file instead Use a lookup table, such as the Current Value Table, to make configuration parameters available throughout the application Use a human-readable format for your configuration files Consider using a tool, such as the Configuration Editor Framework (CEF), to help create a user application to edit your configuration files. 35

27 LabVIEW for CompactRIO Sample Projects Pre-built architectures for embedded control and monitoring applications Designed to ensure quality and scalability of a system 36

28 FPGA Waveform Acquisition and Logging 39

29 How and where to learn more Embedded Programming with LabVIEW and CompactRIO link 3 Design Decisions to Make When Programming an Embedded System link CompactRIO Developer s Guide: /compactriodevguide/ Code and utilities NI-created reuse code: /referencedesigns/ LabVIEW add-ons: /labview-tools-network/ Replication and Deployment (RAD) Utility /example/30986/ NI Labs Relevant Courses LabVIEW Embedded Control and Monitoring 40