Making the Most of your FPGA Design

Transcription

1 Making the Most of your FPGA Design Rejwan Ali Marketing Engineer

2 Overview Introduction to Making the most Maintainability through Simulation Creating Scalable LVFPGA Reactor Pattern in LVFPGA

3 Making the Most of our FPGA Maintainable The code is easy to test and change Scalable Maximize FPGA capabilities

4 LabVIEW FPGA Reconfigurable I/O Custom hardware algorithms 4

5 LV FPGA Development Process Requirements Design Implement Test Deploy 5

6 LV FPGA Development Process Implement Compile Test 6

7 LV FPGA Development Process Implement 15 sec 544 Compilesec 65 sec Test 87% spent compiling 7

8 Reduce Development Time Buy a faster compilation machine Improve the compiler (Xilinx, NI) Simulation /trycompilecloud 8

9 Simulation Simulation The imitation of the operation of a real-world system over time. LVFPGA Simulation Options 1. Simulation on Windows 2. Development Computer with Simulated I/O 3. Conditional Disable Structures 4. LVFPGA Desktop Execution Node 5. Testbench 9

10 Simulation On Windows Pre-FPGA Windows FPGA code Post- FPGA Windows 10

11 Simulation On Windows + Quick Good for inline algorithms Allows Windows VIs - No/incorrect timing I/O does not work Code snipets only Use case: Quick functionality 11

12 Development Computer with Simulated I/O FPGA Target Press Run Generate VHDL Compile Bitfile Run on Hardware Development Computer w/ Sim I/O Press Run Run Diagram on Windows (Simulation) Debug Code 12

13 Development Computer with Simulated I/O

14 Development Computer with Simulated I/O 14

15 Development Computer with Simulated I/O + - Inputs are Full simulation random data by default Memory, FIFOs and I/O supported Windows VIs unsupported on FPGA Standard debug tool available Use case: Functional test 15

16 Conditional Disable Allows changing FPGA source easily by switching between FPGA and Development Computer context 16

17 Conditional Disable + - Quick Branches code Changes functionality automatically Windows VIs unsupported 17

18 LV FPGA Desktop Execution Node Host-side LV FPGA 18

19 LV FPGA Desktop Execution Node 19

20 LV FPGA Desktop Execution Node Unit Test Test Harness 20

21 LV FPGA Desktop Execution Node + Iteration Accurate - Not Tick Accurate Simulates I/O Memory and FIFO supported Use case: Unit Testing & Integration Testing 21

22 Testbench Embedded Testbench An application which verifies functionality of software and hardware through simulation 22

23 Testbench Testbench FPGA Interface I/O Simulation FPGA Example 23

24 Testbench + Full Simulation - Ensure Simulation starts first Test FPGA Interface UI available Customizable I/O Waveform Probes Use case: System testing 24

25 Scalable LabVIEW FPGA How difficult to scale this FPGA Code? 25

26 Scalable LabVIEW FPGA 1. Copy/Paste 2. Change IO 3. Add more memory blocks to the project 4. Add more DMA FIFOs 5. Change the names of controls and indicators DO NOT DO THIS: Unmaintainable Limited DMA FIFOs Huge Diagrams make it hard to debug/simulate 26

27 Scalable SubVIs 1. Create SubVI 2. Copy SubVIs Profit??? Problems: 1. I/O is incorrect 2. Same memory blocks in each copy 3. Same DMA FIFO in each SubVI 4. How do we change the Delay? 27

28 Purple Wires References Inputs Outputs DMA FIFOs Local FIFOs Memory Registers Timing Sources VI-Defined Local FIFOs Memory Registers 28

29 Single-cycle Timed Loops Not allowed in SCTL Problems Some hardware MUST be run inside a SCTL SCTL is not compatible with some operations 29

30 Single-cycle Timed Loops Bonus SCTL code can be used in non-sctl locations SCTL code is typically smaller than non-sctl SCTL code is very deterministic 30

31 Reactor Pattern Reactor Pattern A design pattern for handling information that is being sent concurrently. Very common is networking software. 33

32 Reactor Pattern Host Application Local FIFO DMA FIFO Dispatcher FPGA Channel 0 Channel 1 Channel 2.. Channel N Aggregator 34

33 Reactor Pattern Advantages Very scalable Works on all NI Targets Concurrency Disadvantages Difficult without simulation FIFO sizing can be tricky 37

34 Questions Maintainable Scalable 39