6. Mechanism: Limited Direct Execution

Transcription

1 6. Mechanism: Limited Direct Execution Oerating System: Three Easy Pieces 1

2 How to efficiently virtualize the CPU with control? The OS needs to share the hysical CPU by time sharing. Issue w Performance: How can we imlement virtualization without adding excessive overhead to the system? w Control: How can we run rocesses efficiently while retaining control over the CPU? AOS@UC 2

3 Direct Execution (without limits!) Just run the rogram directly on the CPU. OS 1. Create entry for rocess list 2. Allocate memory for rogram 3. Load rogram into memory 4. Set u stack with argc / argv 5. Clear registers 6. Execute call main() 9. Free memory of rocess 10. Remove from rocess list Program 7. Run main() 8. Execute return from main() Without limits on running rograms, the OS wouldn t be in control of anything and thus would be just a library AOS@UC 3

4 Problem 1: Restricted Oeration What if a rocess wishes to erform some kind of restricted oeration such as w Issuing an I/O request to a disk w Gaining access to more system resources such as CPU or memory Solution: Using rotected control transfer (rocessor has to suort it) w User mode: Alications do not have full access to hardware resources. w Kernel mode: The OS has access to the full resources of the machine AOS@UC 4

5 System Call Allow the kernel to carefully exose certain key ieces of functionality to user rogram, such as w Accessing the file system w Creating and destroying rocesses w Communicating with other rocesses w Allocating more memory But, why they look like a regular rocedure call sometimes (e.g. libc calls)? AOS@UC 5

6 System Call (Cont.) Tra instruction w Jum into the kernel (how to tell where?) w Raise (the rocessor) rivilege level to kernel mode Return-from-tra instruction w Return into the calling user rogram w Reduce (the rocessor) rivilege level back to user mode AOS@UC 6

7 Limited Direction Execution Protocol boot (kernel mode) initialize tra table Hardware remember address of syscall handler run (kernel mode) Create entry for rocess list Allocate memory for rogram Load rogram into memory Setu user stack with argv Fill kernel stack with reg/pc return-from -tra Hardware restore regs from kernel stack move to user mode jum to main Program (user mode) Run main() Call system tra into OS AOS@UC 7

8 Limited Direction Execution Protocol (Cont.) run (kernel mode) Hardware Program (user mode) Handle tra Do work of syscall return-from-tra Free memory of rocess Remove from rocess list (Cont.) save regs to kernel stack move to kernel mode jum to tra handler restore regs from kernel stack move to user mode jum to PC after tra return from main tra (via exit()) AOS@UC 8

9 Problem 2: Switching Between Processes How can the OS regain control of the CPU so that it can switch between rocesses? w A cooerative Aroach: Wait for system calls w A Non-Cooerative Aroach: The OS takes control AOS@UC 9

10 A cooerative Aroach: Wait for system calls Processes eriodically give u the CPU by making system calls such as yield. w The OS decides to run some other task. w Alication also transfer control to the OS when they do something illegal. Divide by zero Try to access memory that it shouldn t be able to access w Ex) Early versions of the Macintosh OS, The old Xerox Alto system A rocess gets stuck in an infinite loo. à Reboot the machine AOS@UC 10

11 A Non-Cooerative Aroach: OS Takes Control A timer interrut w During the boot sequence, the OS start the timer (hardware). w The timer raise an interrut every so many milliseconds. (hardware) w When the interrut is raised : The currently running rocess is halted. Save enough of the state of the rogram A re-configured interrut handler in the OS runs. A timer interrut gives OS the ability to run again on a CPU. AOS@UC 11

12 Saving and Restoring Context Scheduler makes a decision: w Whether to continue running the current rocess, or switch to a different one. w If the decision is made to switch, the OS executes context switch. AOS@UC 12

13 Context Switch A low-level iece of assembly code w Save a few register values for the current rocess onto its kernel stack General urose registers PC kernel stack ointer w Restore a few for the soon-to-be-executing rocess from its kernel stack w Switch to the kernel stack for the soon-to-be-executing rocess AOS@UC 13

14 Limited Direction Execution Protocol (Timer interrut) boot (kernel mode) initialize tra table start interrut timer Hardware remember address of syscall handler timer handler start timer interrut CPU in X ms run (kernel mode) Hardware timer interrut save regs(a) to k-stack(a) move to kernel mode jum to tra handler Program (user mode) Process A AOS@UC 14

15 Limited Direction Execution Protocol (Timer interrut) run (kernel mode) Hardware (Cont.) Program (user mode) Handle the tra Call switch() routine save regs(a) to roc-struct(a) restore regs(b) from roc-struct(b) switch to k-stack(b) return-from-tra (into B) restore regs(b) from k-stack(b) move to user mode jum to B s PC Process B AOS@UC 15

16 The xv6 Context Switch Code 1 # void swtch(struct context **old, struct context *new); 2 # 3 # Save current register context in old 4 # and then load register context from new. 5.globl swtch 6 swtch: 7 # Save old registers 8 movl 4(%es), %eax # ut old tr into eax 9 ol 0(%eax) # save the old IP (o from stack to mem) 10 movl %es, 4(%eax) # and stack 11 movl %ebx, 8(%eax) # and other registers 12 movl %ecx, 12(%eax) 13 movl %edx, 16(%eax) 14 movl %esi, 20(%eax) 15 movl %edi, 24(%eax) 16 movl %eb, 28(%eax) # Load new registers 19 movl 8(%es), %eax # ut new tr into eax 20 movl 28(%eax), %eb # restore other registers 21 movl 24(%eax), %edi 22 movl 20(%eax), %esi 23 movl 16(%eax), %edx 24 movl 12(%eax), %ecx 25 movl 8(%eax), %ebx 26 movl 4(%eax), %es # stack is switched here 27 ushl 0(%eax) # return addr ut in lace 28 ret # finally return into new ctxt AOS@UC 16

17 Current xv6 Code No actual change to new %ei, because we need to switch memory addressing sace before (done in the scheduler switchkvm();) In roc.h // Don't need to save %eax, %ecx, %edx, because the 46 // x86 convention is that the caller has saved them. 17

18 Worried About Concurrency? What haens if, during interrut or tra handling, another interrut occurs? OS handles these situations: w Disable interruts during interrut rocessing w Use a number of sohisticate locking schemes to rotect concurrent access to internal data structures. AOS@UC 18

19 Disclaimer: This lecture slide set is used in AOS course in University of Cantabria. Was initially develoed for Oerating System course in Comuter Science Det. at Hanyang University. This lecture slide set is for OSTEP book written by Remzi and Andrea Araci- Dusseau (at University of Wisconsin) 19