15. Address Translation

Size: px
Start display at page:

Download "15. Address Translation"

Transcription

1 15. Address Translation Oerating System: Three Easy Pieces 1

2 Memory Virtualizing with Efficiency and Control Memory virtualizing takes a similar strategy known as limited direct execution(lde) for efficiency and control. In memory virtualizing, efficiency and control are attained by hardware suort. w e.g., registers, TLB(Translation Look-aside Buffer)s, age-table AOS@UC 2

3 Assumtions Made (just in this lecture) User address sace is contiguous in memory User address sace is smaller than the hysical memory (u to 64KB) Each address sace has the same size (u to ) AOS@UC 3

4 Address Translation Hardware transforms a virtual address to a hysical address. w The desired information is actually stored in a hysical address. The OS must get involved at key oints to set u the hardware. w The OS must manage memory to judiciously intervene. AOS@UC 4

5 Examle: Address Translation C - Language code void func() int x;... x = x + 3; // this is the line of code we are interested in w Load a value from memory w Increment it by three w Store the value back into memory AOS@UC 5

6 Examle: Address Translation(Cont.) Assembly 128 : movl 0x0(%ebx), %eax ; load 0+ebx into eax 132 : addl $0x03, %eax ; add 3 to eax register 135 : movl %eax, 0x0(%ebx) ; store eax back to mem w Presume that the address of x has been lace in ebx register. w Load the value at that address into eax register. w Add 3 to eax register. w Store the value in eax back into memory. AOS@UC 6

7 Examle: Address Translation(Cont.) 1KB 2KB 3KB 4KB movl 0x0(%ebx),%eax Addl 0x03,%eax movl %eax,0x0(%ebx) Program Code Hea hea Fetch instruction at address 128 Execute this instruction (load from address 15KB) Fetch instruction at address 132 Execute this instruction (no memory reference) Fetch the instruction at address 135 Execute this instruction (store to address 15 KB) (free) stack 14KB 15KB 3000 Stack 7

8 Relocation Address Sace The OS wants to lace the rocess somewhere else in hysical memory, not at address 0. w The address sace start at address 0. But how make it transarently? AOS@UC 8

9 A Single Relocated Process Program Code Oerating System Hea hea (free) stack Code Hea (allocated but not in use) Stack Relocated Process Stack Address Sace 64KB Physical Memory 9

10 Base and Bounds Registers Program Code Oerating System Hea base register hea (free) Code Hea (allocated but not in use) stack Stack bounds register Stack Address Sace 64KB Physical Memory 10

11 Aside: Software-based Relocation If Harware-suort is not resent? w Static-Relocation Loader should transform the executable Problems w No rotection w Late relocation is hard Hardware suort is mandatory! AOS@UC 11

12 Dynamic (Hardware based) Relocation When a rogram starts running, the OS decides where in hysical memory a rocess should be loaded. w Set the base register a value. hycal address = virtual address + base w Every virtual address must not be greater than bound and negative. 0 virtual address < bounds w ISA rovide Privileged ins to handle those registers Secific excetion to detect (and handle miss behaviors) AOS@UC 12

13 Relocation and Address Translation 128 : movl 0x0(%ebx), %eax w Fetch instruction at address = (base) w Execute this instruction Load from address 15KB 47KB = 15KB + (base) 1KB 2KB 3KB 4KB movl 0x0(%ebx),%eax Addl 0x03,%eax movl %eax,0x0(%ebx) Program Code Hea hea (free) stack CPU MMU base bounds Memory 14KB 15KB 3000 Stack AOS@UC 13

14 Two ways of Bounds Register Program Code Oerating System Hea the size of address sace bounds (free) Code Hea (allocated but not in use) Stack hysical address of the end of address sace bounds Stack Address Sace 64KB Physical Memory 14

15 OS Issues for Memory Virtualizing The OS must take action to imlement base-and-bounds aroach. Three critical junctures: w When a rocess starts running: Finding sace for address sace in hysical memory w When a rocess is terminated: Reclaiming the memory for use w When context switch occurs: Saving and storing the base-and-bounds air AOS@UC 15

16 OS Issues: When a Process Starts Running The OS must find a room for a new address sace. w free list : A list of the range of the hysical memory which are not in use. The OS looku the free list Free list Oerating System 64KB Code Hea (allocated but not in use) Stack Physical Memory AOS@UC 16

17 OS Issues: When a Process Is Terminated The OS must ut the memory back on the free list. Free list Oerating System Free list Oerating System Process A 64KB Physical Memory 64KB Physical Memory AOS@UC 17

18 OS Issues: When Context Switch Occurs The OS must save and restore the base-and-bounds air. w In rocess structure or rocess control block(pcb) Process A PCB Oerating System Context Switching Oerating System base : bounds : base base 64KB Process A Currently Running Process B bounds 64KB Process A Process B Currently Running bounds 64KB Physical Memory Physical Memory AOS@UC 18

19 Summary: Dynamic Relocation (strawman version) boot (kernel mode) initialize tra table start interrut timer initialize rocess table initialize free list Hardware remember addresses of... system call handler timer handler illegal mem-access handler illegal instruction handler start timer; interrut after X ms run Hardware Program (kernel mode) (user mode) To start rocess A: allocate entry in rocess table allocate memory for rocess set base/bounds registers return-from-tra (into A) restore registers of A move to user mode jum to A s (initial) PC Translate virtual address and erform fetch If exlicit load/store: Process A runs Fetch instruction Execute instruction AOS@UC 19

20 Summary: Dynamic Relocation (strawman version) Handle the tra Call switch() routine save regs(a) to roc-struct(a) (including base/bounds) restore regs(b) from roc-struct(b) (including base/bounds) return-from-tra (into B) Handle the tra Decide to terminate rocess B de-allocate B s memory free B s entry in rocess table Translate virtual address and erform fetch If exlicit load/store: Ensure address is in-bounds; Translate virtual address and erform load/store Timer interrut move to kernel mode Jum to interrut handler restore registers of B move to user mode jum to B s PC Load is out-of-bounds; move to kernel mode jum to tra handler... Fetch instruction Execute instruction Process B runs Execute bad load AOS@UC 20

21 Disclaimer: Disclaimer: This lecture slide set is used in AOS course at University of Cantabria. Was initially develoed for Oerating System course in Comuter Science Det. at Hanyang University. This lecture slide set is for OSTEP book written by Remzi and Andrea Araci- Dusseau (at University of Wisconsin) 21

6. Mechanism: Limited Direct Execution

6. Mechanism: Limited Direct Execution 6. Mechanism: Limited Direct Execution Oerating System: Three Easy Pieces AOS@UC 1 How to efficiently virtualize the CPU with control? The OS needs to share the hysical CPU by time sharing. Issue w Performance:

More information

20. Paging: Smaller Tables

20. Paging: Smaller Tables 20. Paging: Smaller Tables Oerating System: Three Easy Pieces AOS@UC 1 Paging: Linear Tables We usually have one age table for every rocess in the system. w Assume that 32-bit address sace with 4KB ages

More information

30. Condition Variables

30. Condition Variables 30. Condition Variables Oerating System: Three Easy Pieces AOS@UC 1 Condition Variables There are many cases where a thread wishes to check whether a condition is true before continuing its execution.

More information

2. Introduction to Operating Systems

2. Introduction to Operating Systems 2. Introduction to Oerating Systems Oerating System: Three Easy Pieces 1 What a haens when a rogram runs? A running rogram executes instructions. 1. The rocessor fetches an instruction from memory. 2.

More information

Mechanism: Address Translation

Mechanism: Address Translation 15 Mechanism: Address Translation In developing the virtualization of the CPU, we focused on a general mechanism known as limited direct execution (or LDE). The idea behind LDE is simple: for the most

More information

36. I/O Devices. Operating System: Three Easy Pieces 1

36. I/O Devices. Operating System: Three Easy Pieces 1 36. I/O Devices Oerating System: Three Easy Pieces AOS@UC 1 I/O Devices I/O is critical to comuter system to interact with systems. Issue : w How should I/O be integrated into systems? w What are the general

More information

33. Event-based Concurrency

33. Event-based Concurrency 33. Event-based Concurrency Oerating System: Three Easy Pieces AOS@UC 1 Event-based Concurrency A different style of concurrent rogramming without threads w Used in GUI-based alications, some tyes of internet

More information

28. Locks. Operating System: Three Easy Pieces

28. Locks. Operating System: Three Easy Pieces 28. Locks Oerating System: Three Easy Pieces AOS@UC 1 Locks: The Basic Idea Ensure that any critical section executes as if it were a single atomic instruction. w An examle: the canonical udate of a shared

More information

22. Swaping: Policies

22. Swaping: Policies 22. Swaing: Policies Oerating System: Three Easy Pieces 1 Beyond Physical Memory: Policies Memory ressure forces the OS to start aging out ages to make room for actively-used ages. Deciding which age to

More information

10. Multiprocessor Scheduling (Advanced)

10. Multiprocessor Scheduling (Advanced) 10. Multirocessor Scheduling (Advanced) Oerating System: Three Easy Pieces AOS@UC 1 Multirocessor Scheduling The rise of the multicore rocessor is the source of multirocessorscheduling roliferation. w

More information

14. Memory API. Operating System: Three Easy Pieces

14. Memory API. Operating System: Three Easy Pieces 14. Memory API Oerating System: Three Easy Pieces 1 Memory API: malloc() #include void* malloc(size_t size) Allocate a memory region on the hea. w Argument size_t size : size of the memory block(in

More information

37. Hard Disk Drives. Operating System: Three Easy Pieces

37. Hard Disk Drives. Operating System: Three Easy Pieces 37. Hard Disk Drives Oerating System: Three Easy Pieces AOS@UC 1 Hard Disk Driver Hard disk driver have been the main form of ersistent data storage in comuter systems for decades ( and consequently file

More information

4. The Abstraction: The Process

4. The Abstraction: The Process 4. The Abstraction: The Process Operating System: Three Easy Pieces AOS@UC 1 How to provide the illusion of many CPUs? p CPU virtualizing w The OS can promote the illusion that many virtual CPUs exist.

More information

32. Common Concurrency Problems.

32. Common Concurrency Problems. 32. Common Concurrency Problems. Oerating System: Three Easy Pieces AOS@UC 1 Common Concurrency Problems More recent work focuses on studying other tyes of common concurrency bugs. w Take a brief look

More information

42. Crash Consistency: FSCK and Journaling

42. Crash Consistency: FSCK and Journaling 42. Crash Consistency: FSCK and Journaling Oerating System: Three Easy Pieces AOS@UC 1 Crash Consistency AOS@UC 2 Crash Consistency Unlike most data structure, file system data structures must ersist w

More information

43. Log-structured File Systems

43. Log-structured File Systems 43. Log-structured File Systems Oerating System: Three Easy Pieces AOS@UC 1 LFS: Log-structured File System Proosed by Stanford back in 91 Motivated by: w DRAM Memory sizes where growing. w Large ga between

More information

Operating System Labs. Yuanbin Wu

Operating System Labs. Yuanbin Wu Operating System Labs Yuanbin Wu cs@ecnu Operating System Labs Review of Memory Management Early days Memory Management Memory Management Multiprogramming and Time Sharing Multiple processes live in memory

More information

Operating System Labs. Yuanbin Wu

Operating System Labs. Yuanbin Wu Operating System Labs Yuanbin Wu cs@ecnu Operating System Labs Review of Memory Management Early days Memory Management Memory Management Multiprogramming multiple processes could be ready to run at a

More information

Mechanism: Address Translation

Mechanism: Address Translation 14 Mechanism: Address Translation In developing the virtualization of the CPU, we focused on a general mechanism known as limited direct execution (or LDE). The idea behind LDE is simple: for the most

More information

Operating Systems. Pablo Prieto Torralbo. 3. Memory Virtualizing DEPARTMENT OF COMPUTER ENGINEERING

Operating Systems. Pablo Prieto Torralbo. 3. Memory Virtualizing DEPARTMENT OF COMPUTER ENGINEERING Operating Systems 3. Memory Virtualizing Pablo Prieto Torralbo DEPARTMENT OF COMPUTER ENGINEERING AND ELECTRONICS This material is published under: Creative Commons BY-NC-SA 4. 3.1 Memory Virtualization

More information

Virtualizing Memory: Paging. Announcements

Virtualizing Memory: Paging. Announcements CS 537 Introduction to Operating Systems UNIVERSITY of WISCONSIN-MADISON Computer Sciences Department Andrea C. Arpaci-Dusseau Remzi H. Arpaci-Dusseau Virtualizing Memory: Paging Questions answered in

More information

Fall 2017 :: CSE 306. Introduction to. Virtual Memory. Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau)

Fall 2017 :: CSE 306. Introduction to. Virtual Memory. Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau) Introduction to Virtual Memory Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau) Motivating Virtual Memory (Very) old days: Uniprogramming only one process existed at a time OS was little

More information

39. File and Directories

39. File and Directories 39. File and Directories Oerating System: Three Easy Pieces AOS@UC 1 Persistent Storage Kee a data intact even if there is a ower loss. w Hard disk drive w Solid-state storage device Two key abstractions

More information

Virtual memory Paging

Virtual memory Paging Virtual memory Paging M1 MOSIG Operating System Design Renaud Lachaize Acknowledgments Many ideas and slides in these lectures were inspired by or even borrowed from the work of others: Arnaud Legrand,

More information

Lecture 04 Control Flow II. Stephen Checkoway University of Illinois at Chicago CS 487 Fall 2017 Based on Michael Bailey s ECE 422

Lecture 04 Control Flow II. Stephen Checkoway University of Illinois at Chicago CS 487 Fall 2017 Based on Michael Bailey s ECE 422 Lecture 04 Control Flow II Stehen Checkoway University of Illinois at Chicago CS 487 Fall 2017 Based on Michael Bailey s ECE 422 Function calls on 32-bit x86 Stack grows down (from high to low addresses)

More information

Protection. - Programmers typically assume machine has enough memory - Sum of sizes of all processes often greater than physical memory 1 / 36

Protection. - Programmers typically assume machine has enough memory - Sum of sizes of all processes often greater than physical memory 1 / 36 Want processes to co-exist Issues in sharing physical memory rotection - A bug in one process can corrupt memory in another - Must somehow prevent process A from trashing B s memory - Also prevent A from

More information

- Established working set model - Led directly to virtual memory. Protection

- Established working set model - Led directly to virtual memory. Protection Administrivia Virtual Lab 1 due Friday 12pm (noon) We give will give short extensions to groups that run into trouble But email us: - How much is done and left? - How much longer do you need? Attend section

More information

The Process Abstraction. CMPU 334 Operating Systems Jason Waterman

The Process Abstraction. CMPU 334 Operating Systems Jason Waterman The Process Abstraction CMPU 334 Operating Systems Jason Waterman How to Provide the Illusion of Many CPUs? Goal: run N processes at once even though there are M CPUs N >> M CPU virtualizing The OS can

More information

Shuigeng Zhou. May 18, 2016 School of Computer Science Fudan University

Shuigeng Zhou. May 18, 2016 School of Computer Science Fudan University Query Processing Shuigeng Zhou May 18, 2016 School of Comuter Science Fudan University Overview Outline Measures of Query Cost Selection Oeration Sorting Join Oeration Other Oerations Evaluation of Exressions

More information

x86 architecture et similia

x86 architecture et similia x86 architecture et similia 1 FREELY INSPIRED FROM CLASS 6.828, MIT A full PC has: PC architecture 2 an x86 CPU with registers, execution unit, and memory management CPU chip pins include address and data

More information

CS 5460/6460 Operating Systems

CS 5460/6460 Operating Systems CS 5460/6460 Operating Systems Fall 2009 Instructor: Matthew Flatt Lecturer: Kevin Tew TAs: Bigyan Mukherjee, Amrish Kapoor 1 Join the Mailing List! Reminders Make sure you can log into the CADE machines

More information

Shell Code For Beginners

Shell Code For Beginners Shell Code For Beginners Beenu Arora Site: www.beenuarora.com Email: beenudel1986@gmail.com ################################################################ #.. # # _/ \ _ \ _/ # # / \ \\ \ / // \/ /_\

More information

Optimizing Dynamic Memory Management!

Optimizing Dynamic Memory Management! Otimizing Dynamic Memory Management! 1 Goals of this Lecture! Hel you learn about:" Details of K&R hea mgr" Hea mgr otimizations related to Assignment #6" Faster free() via doubly-linked list, redundant

More information

TCBs and Address-Space Layouts Universität Karlsruhe, System Architecture Group

TCBs and Address-Space Layouts Universität Karlsruhe, System Architecture Group µ-kernel Construction (3) TCBs and Address-Space Layouts 1 Thread Control Blocks (TCBs) 2 Fundamental Abstractions Thread Address space What is a thread? How to implement it? 3 Construction Conclusion

More information

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions?

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? exam on Wednesday today s material not on the exam 1 Assembly Assembly is programming

More information

CS399 New Beginnings. Jonathan Walpole

CS399 New Beginnings. Jonathan Walpole CS399 New Beginnings Jonathan Walpole Memory Management Memory Management Memory a linear array of bytes - Holds O.S. and programs (processes) - Each cell (byte) is named by a unique memory address Recall,

More information

Operating Systems and Protection CS 217

Operating Systems and Protection CS 217 Operating Systems and Protection CS 7 Goals of Today s Lecture How multiple programs can run at once o es o Context switching o control block o Virtual Boundary between parts of the system o User programs

More information

Virtual memory - Paging

Virtual memory - Paging Virtual memory - Paging Johan Montelius KTH 2017 1 / 32 The process code (.text) data heap stack kernel 0x00000000 0xC0000000 0xffffffff Memory layout for a 32-bit Linux process 2 / 32 Segments - a could

More information

The process. one problem

The process. one problem The process Virtual memory - Paging Johan Montelius code (.text) data heap stack kernel KTH 0x00000000 0xC0000000 0xffffffff 2017 Memory layout for a 32-bit Linux process Segments - a could be solution

More information

Binary Translation 2

Binary Translation 2 Binary Translation 2 G. Lettieri 22 Oct. 2014 1 Introduction Fig. 1 shows the main data structures used in binary translation. The guest system is represented by the usual data structures implementing

More information

Lecture 8 Memory Management Strategies (chapter 8)

Lecture 8 Memory Management Strategies (chapter 8) Bilkent University Department of Computer Engineering CS342 Operating Systems Lecture 8 Memory Management Strategies (chapter 8) Dr. İbrahim Körpeoğlu http://www.cs.bilkent.edu.tr/~korpe 1 References The

More information

CS 537 Lecture 2 - Processes

CS 537 Lecture 2 - Processes CS 537 Lecture 2 - Processes Michael Swift 1 Basic Structure Kernel is a big program that starts when you boot your program Has full access to physical hardware. User programs, utilities, services see

More information

Argo Programming Guide

Argo Programming Guide Argo Programming Guide Evangelia Kasaaki, asmus Bo Sørensen February 9, 2015 Coyright 2014 Technical University of Denmark This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International

More information

Computer Systems II. Memory Management" Subdividing memory to accommodate many processes. A program is loaded in main memory to be executed

Computer Systems II. Memory Management Subdividing memory to accommodate many processes. A program is loaded in main memory to be executed Computer Systems II Memory Management" Memory Management" Subdividing memory to accommodate many processes A program is loaded in main memory to be executed Memory needs to be allocated efficiently to

More information

CS 471 Operating Systems. Yue Cheng. George Mason University Fall 2017

CS 471 Operating Systems. Yue Cheng. George Mason University Fall 2017 CS 471 Operating Systems Yue Cheng George Mason University Fall 2017 Review: Segmentation 2 Virtual Memory Accesses o Approaches: Static Relocation Dynamic Relocation Base Base-and-Bounds Segmentation

More information

Protection and System Calls. Otto J. Anshus

Protection and System Calls. Otto J. Anshus Protection and System Calls Otto J. Anshus Protection Issues CPU protection Prevent a user from using the CPU for too long Throughput of jobs, and response time to events (incl. user interactive response

More information

10 File System Mass Storage Structure Mass Storage Systems Mass Storage Structure Mass Storage Structure FILE SYSTEM 1

10 File System Mass Storage Structure Mass Storage Systems Mass Storage Structure Mass Storage Structure FILE SYSTEM 1 10 File System 1 We will examine this chater in three subtitles: Mass Storage Systems OERATING SYSTEMS FILE SYSTEM 1 File System Interface File System Imlementation 10.1.1 Mass Storage Structure 3 2 10.1

More information

Linear Data Structure Linked List

Linear Data Structure Linked List . Definition. Reresenting List in C. Imlementing the oerations a. Inserting a node b. Deleting a node c. List Traversal. Linked imlementation of Stack 5. Linked imlementation of Queue 6. Circular List

More information

Computer Systems II. Memory Management" Subdividing memory to accommodate many processes. A program is loaded in main memory to be executed

Computer Systems II. Memory Management Subdividing memory to accommodate many processes. A program is loaded in main memory to be executed Computer Systems II Memory Management" Memory Management" Subdividing memory to accommodate many processes A program is loaded in main memory to be executed Memory needs to be allocated efficiently to

More information

Background. Contiguous Memory Allocation

Background. Contiguous Memory Allocation Operating System Lecture 8 2017.5.9 Chapter 8 (Main Memory) Background Swapping Contiguous Memory Allocation Segmentation - Paging Memory Management Selection of a memory-management method for a specific

More information

Processes (Intro) Yannis Smaragdakis, U. Athens

Processes (Intro) Yannis Smaragdakis, U. Athens Processes (Intro) Yannis Smaragdakis, U. Athens Process: CPU Virtualization Process = Program, instantiated has memory, code, current state What kind of memory do we have? registers + address space Let's

More information

CMSC 313 Lecture 14 Reminder: Midterm Exam next Tues (10/26) Project 4 Questions Virtual Memory on Linux/Pentium platform

CMSC 313 Lecture 14 Reminder: Midterm Exam next Tues (10/26) Project 4 Questions Virtual Memory on Linux/Pentium platform CMSC 313 Lecture 14 Reminder: Midterm Exam next Tues (10/26) roject 4 Questions Virtual Memory on Linux/entium platform UMBC, CMSC313, Richard Chang CMSC 313, Computer Organization & Assembly

More information

12) United States Patent 10) Patent No.: US 6,321,328 B1

12) United States Patent 10) Patent No.: US 6,321,328 B1 USOO6321328B1 12) United States Patent 10) Patent No.: 9 9 Kar et al. (45) Date of Patent: Nov. 20, 2001 (54) PROCESSOR HAVING DATA FOR 5,961,615 10/1999 Zaid... 710/54 SPECULATIVE LOADS 6,006,317 * 12/1999

More information

Lecture 4: Mechanism of process execution. Mythili Vutukuru IIT Bombay

Lecture 4: Mechanism of process execution. Mythili Vutukuru IIT Bombay Lecture 4: Mechanism of process execution Mythili Vutukuru IIT Bombay Low-level mechanisms How does the OS run a process? How does it handle a system call? How does it context switch from one process to

More information

W4118: PC Hardware and x86. Junfeng Yang

W4118: PC Hardware and x86. Junfeng Yang W4118: PC Hardware and x86 Junfeng Yang A PC How to make it do something useful? 2 Outline PC organization x86 instruction set gcc calling conventions PC emulation 3 PC board 4 PC organization One or more

More information

Equality-Based Translation Validator for LLVM

Equality-Based Translation Validator for LLVM Equality-Based Translation Validator for LLVM Michael Ste, Ross Tate, and Sorin Lerner University of California, San Diego {mste,rtate,lerner@cs.ucsd.edu Abstract. We udated our Peggy tool, reviously resented

More information

UML for Global Computing Lecture 3: Property-Driven Development

UML for Global Computing Lecture 3: Property-Driven Development Contents UML for Global Comuting Lecture 3: Proerty-Driven Develoment Martin Wirsing LMU München in cooeration with Hubert Baumeister Lecture : Introducing UML for Mobility Lecture 2: Refining Mobility

More information

Object and Native Code Thread Mobility Among Heterogeneous Computers

Object and Native Code Thread Mobility Among Heterogeneous Computers Object and Native Code Thread Mobility Among Heterogeneous Comuters Bjarne Steensgaard Eric Jul Microsoft Research DIKU (Det. of Comuter Science) One Microsoft Way University of Coenhagen Redmond, WA 98052

More information

Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi

Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Lecture - 13 Virtual memory and memory management unit In the last class, we had discussed

More information

Process Description and Control. Chapter 3

Process Description and Control. Chapter 3 Process Description and Control 1 Chapter 3 2 Processes Working definition: An instance of a program Processes are among the most important abstractions in an OS all the running software on a computer,

More information

CS252 Graduate Computer Architecture Spring 2014 Lecture 6: Modern Out- of- Order Processors

CS252 Graduate Computer Architecture Spring 2014 Lecture 6: Modern Out- of- Order Processors CS252 Graduate Comuter Architecture Sring 2014 Lecture 6: Modern Out- of- Order Processors Krste Asanovic krste@eecs.berkeley.edu htt://inst.eecs.berkeley.edu/~cs252/s14 CS252, Sring 2014, Lecture 6 Last

More information

Recap: Memory Management

Recap: Memory Management , 4/13/2018 EE445M/EE360L.12 Embedded and Real-Time Systems/ Real-Time Operating Systems : Memory Protection, Virtual Memory, Paging References: T. Anderson, M. Dahlin, Operating Systems: Principles and

More information

Operating Systems CMPSCI 377 Spring Mark Corner University of Massachusetts Amherst

Operating Systems CMPSCI 377 Spring Mark Corner University of Massachusetts Amherst Operating Systems CMPSCI 377 Spring 2017 Mark Corner University of Massachusetts Amherst Last Class: Intro to OS An operating system is the interface between the user and the architecture. User-level Applications

More information

Who. Winter Compiler Construction Generic compiler structure. Mailing list and forum. IC compiler. How

Who. Winter Compiler Construction Generic compiler structure. Mailing list and forum. IC compiler. How Winter 2007-2008 Comiler Construction 0368-3133 Mooly Sagiv and Roman Manevich School of Comuter Science Tel-Aviv University Who Roman Manevich Schreiber Oen-sace (basement) Tel: 640-5358 rumster@ost.tau.ac.il

More information

Performance of Various Levels of Storage. Movement between levels of storage hierarchy can be explicit or implicit

Performance of Various Levels of Storage. Movement between levels of storage hierarchy can be explicit or implicit Memory Management All data in memory before and after processing All instructions in memory in order to execute Memory management determines what is to be in memory Memory management activities Keeping

More information

CSE 421/521 - Operating Systems Fall Lecture - XII Main Memory Management. Tevfik Koşar. University at Buffalo. October 18 th, 2012.

CSE 421/521 - Operating Systems Fall Lecture - XII Main Memory Management. Tevfik Koşar. University at Buffalo. October 18 th, 2012. CSE 421/521 - Operating Systems Fall 2012 Lecture - XII Main Memory Management Tevfik Koşar University at Buffalo October 18 th, 2012 1 Roadmap Main Memory Management Fixed and Dynamic Memory Allocation

More information

COMP Parallel Computing. BSP (1) Bulk-Synchronous Processing Model

COMP Parallel Computing. BSP (1) Bulk-Synchronous Processing Model COMP 6 - Parallel Comuting Lecture 6 November, 8 Bulk-Synchronous essing Model Models of arallel comutation Shared-memory model Imlicit communication algorithm design and analysis relatively simle but

More information

CS 537 Lecture 2 Computer Architecture and Operating Systems. OS Tasks

CS 537 Lecture 2 Computer Architecture and Operating Systems. OS Tasks CS 537 Lecture 2 Computer Architecture and Operating Systems Michael Swift OS Tasks What is the role of the OS regarding hardware? What does the OS need from hardware to perform this role? 1 Computer Hardware

More information

Address spaces and memory management

Address spaces and memory management Address spaces and memory management Review of processes Process = one or more threads in an address space Thread = stream of executing instructions Address space = memory space used by threads Address

More information

4) C = 96 * B 5) 1 and 3 only 6) 2 and 4 only

4) C = 96 * B 5) 1 and 3 only 6) 2 and 4 only Instructions: The following questions use the AT&T (GNU) syntax for x86-32 assembly code, as in the course notes. Submit your answers to these questions to the Curator as OQ05 by the posted due date and

More information

Main Memory. CISC3595, Spring 2015 X. Zhang Fordham University

Main Memory. CISC3595, Spring 2015 X. Zhang Fordham University Main Memory CISC3595, Spring 2015 X. Zhang Fordham University 1 Memory Management! Background!! Contiguous Memory Allocation!! Paging!! Structure of the Page Table!! Segmentation!! Example: The Intel Pentium

More information

Administrivia. Lab 1 due Friday 12pm. We give will give short extensions to groups that run into trouble. But us:

Administrivia. Lab 1 due Friday 12pm. We give will give short extensions to groups that run into trouble. But  us: Administrivia Lab 1 due Friday 12pm. We give will give short extensions to groups that run into trouble. But email us: - How much is done & left? - How much longer do you need? Attend section Friday at

More information

Mitigating the Impact of Decompression Latency in L1 Compressed Data Caches via Prefetching

Mitigating the Impact of Decompression Latency in L1 Compressed Data Caches via Prefetching Mitigating the Imact of Decomression Latency in L1 Comressed Data Caches via Prefetching by Sean Rea A thesis resented to Lakehead University in artial fulfillment of the requirement for the degree of

More information

CS370: Operating Systems [Spring 2017] Dept. Of Computer Science, Colorado State University

CS370: Operating Systems [Spring 2017] Dept. Of Computer Science, Colorado State University Frequently asked questions from the previous class survey CS 370: OPERATING SYSTEMS [MEMORY MANAGEMENT] Matrices in Banker s algorithm Max, need, allocated Shrideep Pallickara Computer Science Colorado

More information

Computer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2.

Computer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2. BASIC ELEMENTS Simplified view: Processor Slide 1 Computer System Overview Operating Systems Slide 3 Main Memory referred to as real memory or primary memory volatile modules 2004/S2 secondary memory devices

More information

COMPSCI: Principles of Operating Systems. Lecture 1: Introduction. Anton Burtsev January, 2017

COMPSCI: Principles of Operating Systems. Lecture 1: Introduction. Anton Burtsev January, 2017 COMPSCI: Principles of Operating Systems Lecture 1: Introduction Anton Burtsev January, 2017 Class details Undergraduate 22 students Instructor: Anton Burtsev Meeting time: 9:00-9:50am (M, W, F) Discussions:

More information

CS 162 Operating Systems and Systems Programming Professor: Anthony D. Joseph Spring Lecture 13: Address Translation

CS 162 Operating Systems and Systems Programming Professor: Anthony D. Joseph Spring Lecture 13: Address Translation CS 162 Operating Systems and Systems Programming Professor: Anthony D. Joseph Spring 2004 Lecture 13: Address Translation 13.0 Main Points 13.1 Hardware Translation Overview CPU Virtual Address Translation

More information

Slide 6-1. Processes. Operating Systems: A Modern Perspective, Chapter 6. Copyright 2004 Pearson Education, Inc.

Slide 6-1. Processes. Operating Systems: A Modern Perspective, Chapter 6. Copyright 2004 Pearson Education, Inc. Slide 6-1 6 es Announcements Slide 6-2 Extension til Friday 11 am for HW #1 Previous lectures online Program Assignment #1 online later today, due 2 weeks from today Homework Set #2 online later today,

More information

Principles of Operating Systems

Principles of Operating Systems Principles of Operating Systems Lecture 18-20 - Main Memory Ardalan Amiri Sani (ardalan@uci.edu) [lecture slides contains some content adapted from previous slides by Prof. Nalini Venkatasubramanian, and

More information

Storage Allocation CSE 143. Pointers, Arrays, and Dynamic Storage Allocation. Pointer Variables. Pointers: Review. Pointers and Types

Storage Allocation CSE 143. Pointers, Arrays, and Dynamic Storage Allocation. Pointer Variables. Pointers: Review. Pointers and Types CSE 143 Pointers, Arrays, and Dynamic Storage Allocation [Chater 4,. 148-157, 172-177] Storage Allocation Storage (memory) is a linear array of cells (bytes) Objects of different tyes often reuire differing

More information

Memory Management. CSCI 315 Operating Systems Design Department of Computer Science

Memory Management. CSCI 315 Operating Systems Design Department of Computer Science Memory Management CSCI 315 Operating Systems Design Department of Computer Science Notice: The slides for this lecture are based on those from Operating Systems Concepts, 9th ed., by Silberschatz, Galvin,

More information

Architecture and OS. To do. q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure

Architecture and OS. To do. q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure Architecture and OS To do q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure Computer architecture and OS OS is intimately tied to the hardware it runs on

More information

CMSC 425: Lecture 16 Motion Planning: Basic Concepts

CMSC 425: Lecture 16 Motion Planning: Basic Concepts : Lecture 16 Motion lanning: Basic Concets eading: Today s material comes from various sources, including AI Game rogramming Wisdom 2 by S. abin and lanning Algorithms by S. M. LaValle (Chats. 4 and 5).

More information

Interrupts & System Calls

Interrupts & System Calls Interrupts & System Calls Nima Honarmand Previously on CSE306 Open file hw1.txt App Ok, here s handle App 4 App Libraries Libraries Libraries User System Call Table (350 1200) Supervisor Kernel Hardware

More information

CSE 153 Design of Operating Systems

CSE 153 Design of Operating Systems CSE 153 Design of Operating Systems Winter 19 Lecture 3: OS model and Architectural Support Last time/today Historic evolution of Operating Systems (and computing!) Today: We start our journey in exploring

More information

Processes. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Processes. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University Processes Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu OS Internals User space shell ls trap shell ps Kernel space File System Management I/O

More information

Memory Allocation. Copyright : University of Illinois CS 241 Staff 1

Memory Allocation. Copyright : University of Illinois CS 241 Staff 1 Memory Allocation Copyright : University of Illinois CS 241 Staff 1 Recap: Virtual Addresses A virtual address is a memory address that a process uses to access its own memory Virtual address actual physical

More information

CS5460: Operating Systems

CS5460: Operating Systems CS5460: Operating Systems Lecture 2: OS Hardware Interface (Chapter 2) Course web page: http://www.eng.utah.edu/~cs5460/ CADE lab: WEB L224 and L226 http://www.cade.utah.edu/ Projects will be on Linux

More information

Memory management. Requirements. Relocation: program loading. Terms. Relocation. Protection. Sharing. Logical organization. Physical organization

Memory management. Requirements. Relocation: program loading. Terms. Relocation. Protection. Sharing. Logical organization. Physical organization Requirements Relocation Memory management ability to change process image position Protection ability to avoid unwanted memory accesses Sharing ability to share memory portions among processes Logical

More information

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture Last 2 Classes: Introduction to Operating Systems & C++ tutorial User apps OS Virtual machine interface hardware physical machine interface An operating system is the interface between the user and the

More information

CSC369 Lecture 2. Larry Zhang

CSC369 Lecture 2. Larry Zhang CSC369 Lecture 2 Larry Zhang 1 Announcements Lecture slides Midterm timing issue Assignment 1 will be out soon! Start early, and ask questions. We will have bonus for groups that finish early. 2 Assignment

More information

What the CPU Sees Basic Flow Control Conditional Flow Control Structured Flow Control Functions and Scope. C Flow Control.

What the CPU Sees Basic Flow Control Conditional Flow Control Structured Flow Control Functions and Scope. C Flow Control. C Flow Control David Chisnall February 1, 2011 Outline What the CPU Sees Basic Flow Control Conditional Flow Control Structured Flow Control Functions and Scope Disclaimer! These slides contain a lot of

More information

Memory Management. Contents: Memory Management. How to generate code? Background

Memory Management. Contents: Memory Management. How to generate code? Background TDIU11 Operating systems Contents: Memory Management Memory Management [SGG7/8/9] Chapter 8 Background Relocation Dynamic loading and linking Swapping Contiguous Allocation Paging Segmentation Copyright

More information

15 Sharing Main Memory Segmentation and Paging

15 Sharing Main Memory Segmentation and Paging Operating Systems 58 15 Sharing Main Memory Segmentation and Paging Readings for this topic: Anderson/Dahlin Chapter 8 9; Siberschatz/Galvin Chapter 8 9 Simple uniprogramming with a single segment per

More information

Modified Bloom filter for high performance hybrid NoSQL systems

Modified Bloom filter for high performance hybrid NoSQL systems odified Bloom filter for high erformance hybrid NoSQL systems A.B.Vavrenyuk, N.P.Vasilyev, V.V.akarov, K.A.atyukhin,..Rovnyagin, A.A.Skitev National Research Nuclear University EPhI (oscow Engineering

More information

W4118: interrupt and system call. Junfeng Yang

W4118: interrupt and system call. Junfeng Yang W4118: interrupt and system call Junfeng Yang Outline Motivation for protection Interrupt System call 2 Need for protection Kernel privileged, cannot trust user processes User processes may be malicious

More information

Memory Management. Frédéric Haziza Spring Department of Computer Systems Uppsala University

Memory Management. Frédéric Haziza Spring Department of Computer Systems Uppsala University Memory Management Frédéric Haziza Department of Computer Systems Uppsala University Spring 2008 Operating Systems Process Management Memory Management Storage Management Compilers Compiling

More information

Programming at different levels

Programming at different levels CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 EMY MNEMONIC MACHINE LANGUAGE PROGRAMMING EXAMPLES Programming at different levels CS1114 Mathematical Problem : a = b + c CS2214 CS2214 The C-like

More information

Multi-Process Systems: Memory (2) Memory & paging structures: free frames. Memory & paging structures. Physical memory

Multi-Process Systems: Memory (2) Memory & paging structures: free frames. Memory & paging structures. Physical memory Multi-Process Systems: Memory (2) What we will learn A detailed description of various ways of organizing memory Discuss various memory-management techniques, including paging and segmentation To provide

More information

Midterm 1. Administrivia. Virtualizing Resources. CS162 Operating Systems and Systems Programming Lecture 12. Address Translation

Midterm 1. Administrivia. Virtualizing Resources. CS162 Operating Systems and Systems Programming Lecture 12. Address Translation Midterm 1 CS162 Operating Systems and Systems Programming Lecture 12 Address Translation March 5, 2018 Profs. Anthony D. Joseph & Jonathan Ragan-Kelley http://cs162.eecs.berkeley.edu Lec 12.2 Administrivia

More information