Who am I? Moritz Lipp PhD Graz University of

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2 Who am I? Moritz Lipp PhD Graz University of moritz.lipp@iaik.tugraz.at 1 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

3 Who am I? Michael Schwarz PhD Graz University of michael.schwarz@iaik.tugraz.at 2 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

4 Who am I? Daniel Gruss Graz University of daniel.gruss@iaik.tugraz.at 3 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

5 Team Anders Fogh Daniel Genkin Werner Haas Mike Hamburg Jann Horn Paul Kocher Stefan Mangard Thomas Prescher Yuval Yarom 4 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

6 Let s Read Kernel Memory from User Space!

7 Virtual Memory Kernel Addresses Non-canonical Addresses Virtual Address Space User Addresses 5 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

8 Building the Code Find something human readable, e.g., the Linux version # sudo grep linux_banner /proc/kallsyms ffffffff81a000e0 R linux_banner 6 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

$Building the Code char data = *(char*) 0xffffffff81a000e0; printf("%c\n",$

9 Building the Code char data = *(char*) 0xffffffff81a000e0; printf("%c\n", data); 7 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

10 Building the Code Compile and run 8 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

11 Building the Code Compile and run segfault at ffffffff81a000e0 ip sp 00007ffce4a80610 error 5 in reader 8 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

12 Building the Code Compile and run segfault at ffffffff81a000e0 ip sp 00007ffce4a80610 error 5 in reader Kernel addresses are of course not accessible 8 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

13 Building the Code Compile and run segfault at ffffffff81a000e0 ip sp 00007ffce4a80610 error 5 in reader Kernel addresses are of course not accessible Any invalid access throws an exception segmentation fault 8 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

14 Building the Code Just catch the segmentation fault! 9 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

15 Building the Code Just catch the segmentation fault! We can simply install a signal handler 9 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

16 Building the Code Just catch the segmentation fault! We can simply install a signal handler And if an exception occurs, just jump back and continue 9 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

17 Building the Code Just catch the segmentation fault! We can simply install a signal handler And if an exception occurs, just jump back and continue Then we can read the value 9 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

19 Building the Code Still no kernel memory 10 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

20 Building the Code Still no kernel memory Privilege checks seem to work 10 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

21 Building the Code Still no kernel memory Privilege checks seem to work Maybe it is not that straight forward 10 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

22 Building the Code Still no kernel memory Privilege checks seem to work Maybe it is not that straight forward Back to the drawing board 10 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

23 Operating Systems 101

24 Memory Isolation Userspace Kernelspace Kernel is isolated from user space Applications Operating System Memory 11 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

25 Memory Isolation Userspace Kernelspace Kernel is isolated from user space This isolation is a combination of hardware and software Applications Operating System Memory 11 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

26 Memory Isolation Userspace Applications Kernelspace Operating System Memory Kernel is isolated from user space This isolation is a combination of hardware and software User applications cannot access anything from the kernel 11 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

27 Paging CPU support virtual address spaces to isolate processes 12 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

28 Paging CPU support virtual address spaces to isolate processes Physical memory is organized in page frames 12 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

29 Paging CPU support virtual address spaces to isolate processes Physical memory is organized in page frames Virtual memory pages are mapped to page frames using page tables 12 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

30 Address Translation on x86-64 CR3 PML4 PML4E 0 PML4E 1 #PML4I PML4E 511 PDPT PDPTE 0 PDPTE 1 #PDPTI PDPTE 511 Page Directory PDE 0 PDE 1 PDE #PDI PDE 511 PML4I (9 b) PDPTI (9 b) PDI (9 b) PTI (9 b) Offset (12 b) 48-bit virtual address Page Table PTE 0 PTE 1 PTE #PTI PTE KiB Page Byte 0 Byte 1 Offset Byte Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

31 Address Translation on x86-64 CR3 PML4 PML4E 0 PML4E 1 #PML4I PML4E 511 PDPT PDPTE 0 PDPTE 1 #PDPTI PDPTE 511 Page Directory PDE 0 PDE 1 PDE #PDI PDE 511 PML4I (9 b) PDPTI (9 b) PDI (9 b) PTI (9 b) Offset (12 b) 48-bit virtual address Page Table PTE 0 PTE 1 PTE #PTI PTE KiB Page Byte 0 Byte 1 Offset Byte Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

32 Page Table Entry P RW US WT UC R D S G Ignored Physical Page Number Ignored X User/Supervisor bit defines in which privilege level the page can be accessed 14 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

33 Direct-physical map 0 max Physical memory User Kernel Kernel is typically mapped into every address space 15 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

34 Direct-physical map 0 max Physical memory User Kernel Kernel is typically mapped into every address space Entire physical memory is mapped in the kernel 15 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

35 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

36 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

37 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

38 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

39 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

40 Loading an address 16 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

41 Side-channel Attacks

42 Side-channel Attacks Safe software infrastructure does not mean safe execution 17 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

43 Side-channel Attacks Safe software infrastructure does not mean safe execution Information leaks because of the underlying hardware 17 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

44 Side-channel Attacks Safe software infrastructure does not mean safe execution Information leaks because of the underlying hardware Exploit unintentional information leakage by side-effects 17 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

45 Side-channel Attacks Safe software infrastructure does not mean safe execution Information leaks because of the underlying hardware Exploit unintentional information leakage by side-effects Power consumption Execution time CPU caches 17 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

46 Caches and Cache Attacks

47 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

48 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

49 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

50 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

51 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

52 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

53 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

54 CPU Cache 18 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

55 Memory Access Latency 10 4 Number of accesses Cache hit Cache miss ,000 1,100 1,200 Measured access time (CPU cycles) 19 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

56 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

57 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

58 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

59 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

60 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

61 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

62 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

63 Flush+Reload 20 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

64 Microarchitecture

65 Architecture and Microarchitecture Instruction Set Architecture (ISA) is an abstract model of a computer (x86, ARMv8, SPARC, ) 21 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

66 Architecture and Microarchitecture Instruction Set Architecture (ISA) is an abstract model of a computer (x86, ARMv8, SPARC, ) Serves as the interface between hardware and software 21 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

67 Architecture and Microarchitecture Instruction Set Architecture (ISA) is an abstract model of a computer (x86, ARMv8, SPARC, ) Serves as the interface between hardware and software Microarchitecture is an actual implementation of the ISA 21 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

Architecture and Microarchitecture Instruction Set Architecture (ISA) is an abstract model of a computer (x86, ARMv8, SPARC, ) Serves as the interface

68 Architecture and Microarchitecture Instruction Set Architecture (ISA) is an abstract model of a computer (x86, ARMv8, SPARC, ) Serves as the interface between hardware and software Microarchitecture is an actual implementation of the ISA 21 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

69 In-Order Execution IF ID EX MEM WB IF ID EX MEM WB Instructions are... fetched (IF) from the L1 Instruction Cache IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB 22 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

70 In-Order Execution IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Instructions are... fetched (IF) from the L1 Instruction Cache decoded (ID) IF ID EX MEM WB IF ID EX MEM WB 22 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

71 In-Order Execution IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Instructions are... fetched (IF) from the L1 Instruction Cache decoded (ID) executed (EX) by execution units IF ID EX MEM WB 22 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

72 In-Order Execution IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Instructions are... fetched (IF) from the L1 Instruction Cache decoded (ID) executed (EX) by execution units Memory access is performed (MEM) 22 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

73 In-Order Execution IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Instructions are... fetched (IF) from the L1 Instruction Cache decoded (ID) executed (EX) by execution units Memory access is performed (MEM) Architectural register file is updated (WB) 22 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

74 In-Order Execution Instructions are executed in-order 23 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

75 In-Order Execution Instructions are executed in-order Pipeline stalls when stages are not ready 23 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

76 In-Order Execution Instructions are executed in-order Pipeline stalls when stages are not ready If data is not cached, we need to wait 23 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

77 Out-of-order Execution int width = 10, height = 5; float diagonal = sqrt(width * width + height * height); int area = width * height; printf("area %d x %d = %d\n", width, height, area); 24 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

78 Out-of-order Execution int width = 10, height = 5; float diagonal = sqrt(width * width + height * height); int area = width * height; printf("area %d x %d = %d\n", width, height, area); 24 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

79 Out-of-Order Execution L1 Instruction Cache ITLB Frontend Branch Predictor µop Cache µops Instruction Fetch & PreDecode Instruction Queue 4-Way Decode µop µop µop µop CDB Execution Engine MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are fetched and decoded in the front-end Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 25 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

80 Out-of-Order Execution L1 Instruction Cache ITLB Frontend Branch Predictor µop Cache µops Instruction Fetch & PreDecode Instruction Queue 4-Way Decode µop µop µop µop CDB Execution Engine MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are fetched and decoded in the front-end dispatched to the backend Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 25 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

81 Out-of-Order Execution L1 Instruction Cache ITLB Frontend Branch Predictor µop Cache µops Instruction Fetch & PreDecode Instruction Queue 4-Way Decode µop µop µop µop CDB Execution Engine MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are fetched and decoded in the front-end dispatched to the backend processed by individual execution units Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 25 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

82 Out-of-Order Execution L1 Instruction Cache ITLB Frontend Branch Predictor µop Cache µops Instruction Fetch & PreDecode Instruction Queue 4-Way Decode µop µop µop µop MUX Instructions are executed out-of-order Allocation Queue µop µop µop µop CDB Reorder buffer µop µop µop µop µop µop µop µop Execution Engine Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

83 Out-of-Order Execution L1 Instruction Cache ITLB Frontend Branch Predictor µop Cache µops Instruction Fetch & PreDecode Instruction Queue 4-Way Decode µop µop µop µop MUX Allocation Queue µop µop µop µop Instructions are executed out-of-order wait until their dependencies are ready CDB Reorder buffer µop µop µop µop µop µop µop µop Execution Engine Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

84 Out-of-Order Execution L1 Instruction Cache ITLB Frontend CDB Execution Engine Branch Instruction Fetch & PreDecode Predictor Instruction Queue µop Cache 4-Way Decode µops µop µop µop µop MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are executed out-of-order wait until their dependencies are ready Later instructions might execute prior earlier instructions Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

85 Out-of-Order Execution L1 Instruction Cache ITLB Frontend CDB Execution Engine Branch Instruction Fetch & PreDecode Predictor Instruction Queue µop Cache 4-Way Decode µops µop µop µop µop MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are executed out-of-order wait until their dependencies are ready Later instructions might execute prior earlier instructions retire in-order Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

86 Out-of-Order Execution L1 Instruction Cache ITLB Frontend CDB Execution Engine Branch Instruction Fetch & PreDecode Predictor Instruction Queue µop Cache 4-Way Decode µops µop µop µop µop MUX Allocation Queue µop µop µop µop Reorder buffer µop µop µop µop µop µop µop µop Scheduler µop µop µop µop µop µop µop µop ALU, AES,... ALU, FMA,... ALU, Vect,... ALU, Branch Load data Load data Store data AGU Execution Units Instructions are executed out-of-order wait until their dependencies are ready Later instructions might execute prior earlier instructions retire in-order State becomes architecturally visible Memory Subsystem Load Buffer L1 Data Cache Store Buffer DTLB STLB L2 Cache 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

87 Out-of-Order Execution L1 Instruction Cache ITLB Frontend CDB Execution Engine Memory Subsystem ALU, AES,... Branch Predictor µop Cache Reorder buffer µop µop µop µop µop µop µop µop ALU, FMA,... ALU, Vect,... Execution Units Scheduler µop µop µop µop µop µop µop µop Load Buffer µops L1 Data Cache Store Buffer Allocation Queue µop µop µop µop ALU, Branch DTLB Instruction Fetch & PreDecode MUX Instruction Queue Load data 4-Way Decode µop µop µop µop Load data STLB Store data L2 Cache AGU Instructions are executed out-of-order wait until their dependencies are ready Later instructions might execute prior earlier instructions retire in-order State becomes architecturally visible Exceptions are checked during retirement 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

88 Out-of-Order Execution L1 Instruction Cache ITLB Frontend CDB Execution Engine Memory Subsystem ALU, AES,... Branch Predictor µop Cache Reorder buffer µop µop µop µop µop µop µop µop ALU, FMA,... ALU, Vect,... Execution Units Scheduler µop µop µop µop µop µop µop µop Load Buffer µops L1 Data Cache Store Buffer Allocation Queue µop µop µop µop ALU, Branch DTLB Instruction Fetch & PreDecode MUX Instruction Queue Load data 4-Way Decode µop µop µop µop Load data STLB Store data L2 Cache AGU Instructions are executed out-of-order wait until their dependencies are ready Later instructions might execute prior earlier instructions retire in-order State becomes architecturally visible Exceptions are checked during retirement Flush pipeline and recover state 26 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

89 The state does not become architecturally visible but

90 The state does not become architecturally visible but

91 Building the Code New code *(volatile char*) 0; array[84 * 4096] = 0; 27 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

92 Building the Code New code *(volatile char*) 0; array[84 * 4096] = 0; volatile because compiler was not happy warning : statement with no e f f e c t [ Wunused value ] * ( char * ) 0 ; 27 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

93 Building the Code New code *(volatile char*) 0; array[84 * 4096] = 0; volatile because compiler was not happy warning : statement with no e f f e c t [ Wunused value ] * ( char * ) 0 ; Static code analyzer is still not happy warning : Dereference of n u l l pointer * ( v o l a t i l e char * ) 0 ; 27 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

94 Building the Code Flush+Reload over all pages of the array Access time [cycles] Page 28 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

95 Building the Code Flush+Reload over all pages of the array Access time [cycles] Page Unreachable code line was actually executed 28 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

96 Building the Code Flush+Reload over all pages of the array Access time [cycles] Page Unreachable code line was actually executed Exception was only thrown afterwards 28 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

97 Building the Code Out-of-order instructions leave microarchitectural traces 29 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

98 Building the Code Out-of-order instructions leave microarchitectural traces We can see them for example in the cache 29 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

99 Building the Code Out-of-order instructions leave microarchitectural traces We can see them for example in the cache Give such instructions a name: transient instructions 29 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

100 Building the Code Out-of-order instructions leave microarchitectural traces We can see them for example in the cache Give such instructions a name: transient instructions We can indirectly observe the execution of transient instructions 29 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

101 Building the Code 30 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

102 Building the Code 30 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

103 Building the Code Add another layer of indirection to test char data = *(char*) 0xffffffff81a000e0; array[data * 4096] = 0; 31 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

104 Building the Code Add another layer of indirection to test char data = *(char*) 0xffffffff81a000e0; array[data * 4096] = 0; Then check whether any part of array is cached 31 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

105 Building the Code Flush+Reload over all pages of the array Access time [cycles] Page Index of cache hit reveals data 32 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

106 Building the Code Flush+Reload over all pages of the array Access time [cycles] Page Index of cache hit reveals data Permission check is in some cases not fast enough 32 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

107

108 Meltdown Using out-of-order execution, we can read data at any address 33 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

109 Meltdown Using out-of-order execution, we can read data at any address Index of cache hit reveals data 33 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

110 Meltdown Using out-of-order execution, we can read data at any address Index of cache hit reveals data Permission check is in some cases not fast enough 33 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

111 Meltdown Using out-of-order execution, we can read data at any address Index of cache hit reveals data Permission check is in some cases not fast enough Entire physical memory is typically accessible through kernel space 33 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

112

113 Demo

114 Details: Exception Handling Basic Meltdown code leads to a crash (segfault) 34 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

115 Details: Exception Handling Basic Meltdown code leads to a crash (segfault) How to prevent the crash? 34 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

116 Details: Exception Handling Basic Meltdown code leads to a crash (segfault) How to prevent the crash? Fault Handling Fault Suppression Fault Prevention 34 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

117 Meltdown with Fault Suppression Intel TSX to suppress exceptions instead of signal handler if(xbegin() == XBEGIN_STARTED) { char secret = *(char*) 0xffffffff81a000e0; array[secret * 4096] = 0; xend(); } for (size_t i = 0; i < 256; i++) { if (flush_and_reload(array + i * 4096) == CACHE_HIT) { printf("%c\n", i); } } 35 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

118 Meltdown with Fault Prevention Speculative execution to prevent exceptions int speculate = rand() % 2; size_t address = (0xffffffff81a000e0 * speculate) + ((size_t)&zero * (1 - speculate)); if(!speculate) { char secret = *(char*) address; array[secret * 4096] = 0; } for (size_t i = 0; i < 256; i++) { if (flush_and_reload(array + i * 4096) == CACHE_HIT) { printf("%c\n", i); } } 36 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

119 Make it faster Improve the performance with a NULL pointer dereference 37 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

$Make it faster Improve the performance with a NULL pointer dereference if(xbegin() == XBEGIN_STARTED) { *(volatile char*) 0; char secret =$

120 Make it faster Improve the performance with a NULL pointer dereference if(xbegin() == XBEGIN_STARTED) { *(volatile char*) 0; char secret = *(char*) 0xffffffff81a000e0; array[secret * 4096] = 0; xend(); } 37 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

121

122

123 Uncached memory Assumed that one can only read data stored in the L1 with Meltdown 38 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

124 Uncached memory Assumed that one can only read data stored in the L1 with Meltdown Experiment where a thread flushes the value constantly and a thread on a different core reloads the value 38 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

125 Uncached memory Assumed that one can only read data stored in the L1 with Meltdown Experiment where a thread flushes the value constantly and a thread on a different core reloads the value Target data is not in the L1 cache of the attacking core 38 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

126 Uncached memory Assumed that one can only read data stored in the L1 with Meltdown Experiment where a thread flushes the value constantly and a thread on a different core reloads the value Target data is not in the L1 cache of the attacking core We can still leak the data at a lower reading rate 38 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

127 Uncached memory Assumed that one can only read data stored in the L1 with Meltdown Experiment where a thread flushes the value constantly and a thread on a different core reloads the value Target data is not in the L1 cache of the attacking core We can still leak the data at a lower reading rate Meltdown might implicitly cache the data 38 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

128 Uncachable memory Mark pages in page tables as UC (uncachable) 39 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

129 Uncachable memory Mark pages in page tables as UC (uncachable) Every read or write operation will go to main memory 39 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

130 Uncachable memory Mark pages in page tables as UC (uncachable) Every read or write operation will go to main memory If the attacker can trigger a legitimate load (system call, ) on the same CPU core, the data still can be leaked 39 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

131 Uncachable memory Mark pages in page tables as UC (uncachable) Every read or write operation will go to main memory If the attacker can trigger a legitimate load (system call, ) on the same CPU core, the data still can be leaked Meltdown might read the data from one of the fill buffers 39 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

132 Uncachable memory Mark pages in page tables as UC (uncachable) Every read or write operation will go to main memory If the attacker can trigger a legitimate load (system call, ) on the same CPU core, the data still can be leaked Meltdown might read the data from one of the fill buffers as they are shared between threads running on the same core 39 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

133 So you can dump the entire memory.

134 So you can dump the entire memory. But it takes ages?

135 Practical attacks Dumping the entire physical memory takes some time 40 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

136 Practical attacks Dumping the entire physical memory takes some time Not very practical in most scenarios 40 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

137 Practical attacks Dumping the entire physical memory takes some time Not very practical in most scenarios Can we mount more targeted attacks? 40 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

138 VeraCrypt Open-source utility for disk encryption 41 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

139 VeraCrypt Open-source utility for disk encryption Fork of TrueCrypt 41 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

140 VeraCrypt Open-source utility for disk encryption Fork of TrueCrypt Cryptographic keys are stored in RAM 41 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

141 VeraCrypt Open-source utility for disk encryption Fork of TrueCrypt Cryptographic keys are stored in RAM With Meltdown, we can extract the keys from DRAM 41 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

142 Demo

143 Breaking KASLR De-randomize KASLR to access internal kernel structures 42 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

144 Breaking KASLR De-randomize KASLR to access internal kernel structures Locate a known value inside the kernel, e.g., Linux banner 42 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

145 Breaking KASLR De-randomize KASLR to access internal kernel structures Locate a known value inside the kernel, e.g., Linux banner Start at the default address according to the symbol table of the running kernel 42 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

146 Breaking KASLR De-randomize KASLR to access internal kernel structures Locate a known value inside the kernel, e.g., Linux banner Start at the default address according to the symbol table of the running kernel Linux KASLR has an entropy of 6 bits only 64 possible randomization offsets 42 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

147 Breaking KASLR De-randomize KASLR to access internal kernel structures Locate a known value inside the kernel, e.g., Linux banner Start at the default address according to the symbol table of the running kernel Linux KASLR has an entropy of 6 bits only 64 possible randomization offsets Difference between the found address and the non-randomized base address is the randomization offset 42 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

148 Locating the victim process Linux manages all processes in a linked list 43 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

149 Locating the victim process Linux manages all processes in a linked list Head of the list is stored at init_task structure 43 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

150 Locating the victim process Linux manages all processes in a linked list Head of the list is stored at init_task structure At a fixed offset that varies only among kernel builds 43 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

151 Locating the victim process Linux manages all processes in a linked list Head of the list is stored at init_task structure At a fixed offset that varies only among kernel builds Each task list structure contains a pointer to the next task and PID of the task name of the task Root of the multi-level page table 43 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

152 Dumping memory content Resolve physical address using paging structures 44 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

153 Dumping memory content Resolve physical address using paging structures Read the content using the direct-physical map 44 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

154 Dumping memory content Resolve physical address using paging structures Read the content using the direct-physical map Enumerate all mapped pages and dump entire process memory 44 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

155 Dumping memory content Resolve physical address using paging structures Read the content using the direct-physical map Enumerate all mapped pages and dump entire process memory Location of the key known, we can just dump the key directly 44 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

156 Final steps aeskeyfind to extract AES keys from the memory dump 45 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

157 Final steps aeskeyfind to extract AES keys from the memory dump pytruecrypt to decrypt disk image using the extracted key 45 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

158 Final steps aeskeyfind to extract AES keys from the memory dump pytruecrypt to decrypt disk image using the extracted key Affects every application that stores its secret in DRAM 45 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

159 Who is affected?

160 Affected by Meltdown Intel: Almost every CPU 46 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

161 Affected by Meltdown Intel: Almost every CPU AMD: Seems not to be affected 46 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

162 Affected by Meltdown Intel: Almost every CPU AMD: Seems not to be affected ARM: Only the Cortex-A75 46 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

163 Affected by Meltdown Intel: Almost every CPU AMD: Seems not to be affected ARM: Only the Cortex-A75 IBM: System Z, Power Architecture, POWER8 and POWER9 46 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

164 Affected by Meltdown Intel: Almost every CPU AMD: Seems not to be affected ARM: Only the Cortex-A75 IBM: System Z, Power Architecture, POWER8 and POWER9 Apple: All Mac and ios devices 46 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

165 Affected by Meltdown But there are other CPU manufacturers as well 47 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

166 Samsung Galaxy S7 Samsung Galaxy S7 Exynos Mongoose M1 CPU Architecture 48 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

167 Samsung Galaxy S7 Samsung Galaxy S7 Exynos Mongoose M1 CPU Architecture Custom CPU core in the Exynos 8 Octa (8890) 48 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

168 Samsung Galaxy S7 Samsung Galaxy S7 Exynos Mongoose M1 CPU Architecture Custom CPU core in the Exynos 8 Octa (8890) Perceptron Branch Prediction 48 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

169 Samsung Galaxy S7 Samsung Galaxy S7 Exynos Mongoose M1 CPU Architecture Custom CPU core in the Exynos 8 Octa (8890) Perceptron Branch Prediction Full Out-of-Order Instruction Execution 48 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

170 Samsung Galaxy S7 Samsung Galaxy S7 Exynos Mongoose M1 CPU Architecture Custom CPU core in the Exynos 8 Octa (8890) Perceptron Branch Prediction Full Out-of-Order Instruction Execution Full Out-of-Order loads and stores 48 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

171 Demo

172 Samsung Galaxy S7 Samsung Galaxy S7 Luckily they already fixed it 49 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

173 Samsung Galaxy S7 Samsung Galaxy S7 Luckily they already fixed it With their latest update 49 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

174 Samsung Galaxy S7 Samsung Galaxy S7 Luckily they already fixed it With their latest update on July 10, Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

175 Affected by Meltdown But there are other CPU manufacturers as well which are affected Need to evaluate the attack on other CPUs as well Notify the users and custom ROM developers, e.g., LineageOS 50 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

176 But wait, what about privileged registers?

177 Variant 3a ARM found a closely related Meltdown variant 51 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

178 Variant 3a ARM found a closely related Meltdown variant Read of system registers that are not accessible from current exception level 51 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

179 Variant 3a ARM found a closely related Meltdown variant Read of system registers that are not accessible from current exception level ARM Cortex-A15, Cortex-A57 and Cortex-A72 are vulnerable 51 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

180 Variant 3a ARM found a closely related Meltdown variant Read of system registers that are not accessible from current exception level ARM Cortex-A15, Cortex-A57 and Cortex-A72 are vulnerable Impact: breaking KASLR and pointer authentication 51 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

181 Demo

182 Variant 3a Intel is affected too (May 21, 2018) 52 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

183 Variant 3a Intel is affected too (May 21, 2018) Almost every CPU (Core i3/i5/i7, 2nd-8th Intel Core, Xeon, Atom, Pentium, ) 52 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

184 Variant 3a Intel is affected too (May 21, 2018) Almost every CPU (Core i3/i5/i7, 2nd-8th Intel Core, Xeon, Atom, Pentium, ) Rogue System Register Read (RSRE) (CVE ) 52 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

185 Is Meltdown (or Spectre) a side-channel attack? 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

186 Is Meltdown (or Spectre) a side-channel attack? 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

187 Is Meltdown (or Spectre) a side-channel attack? No. 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

188 Is Meltdown (or Spectre) a side-channel attack? No. We read the data directly 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

189 Is Meltdown (or Spectre) a side-channel attack? No. We read the data directly We use a side channel internally for transmission 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

190 Is Meltdown (or Spectre) a side-channel attack? No. We read the data directly We use a side channel internally for transmission does not make the entire thing a side-channel attack 53 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

191 Is Meltdown a variant of Spectre? Is it speculative execution? 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

192 Is Meltdown a variant of Spectre? Is it speculative execution? 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

193 Is Meltdown a variant of Spectre? Is it speculative execution? No. 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

194 Is Meltdown a variant of Spectre? Is it speculative execution? No. Often heard: Meltdown is speculating beyond faulting instructions 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

195 Is Meltdown a variant of Spectre? Is it speculative execution? No. Often heard: Meltdown is speculating beyond faulting instructions That s not speculative execution 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

196 Is Meltdown a variant of Spectre? Is it speculative execution? No. Often heard: Meltdown is speculating beyond faulting instructions That s not speculative execution Speculating beyond faulting instructions - not even the actual problem 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

197 Is Meltdown a variant of Spectre? Is it speculative execution? No. Often heard: Meltdown is speculating beyond faulting instructions That s not speculative execution Speculating beyond faulting instructions - not even the actual problem AMD does that - but is not affected! 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

198 Is Meltdown a variant of Spectre? Is it speculative execution? No. Often heard: Meltdown is speculating beyond faulting instructions That s not speculative execution Speculating beyond faulting instructions - not even the actual problem AMD does that - but is not affected! Actual problem: fetching & using real values for instructions after faulting ones 54 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

199 How can this all be fixed?

200 Meltdown Mitigation Problem is rooted in hardware 55 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

201 Meltdown Mitigation Problem is rooted in hardware Race condition between the memory fetch and corresponding permission check Serialize both of them 55 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

202 Meltdown Mitigation Problem is rooted in hardware Race condition between the memory fetch and corresponding permission check Serialize both of them Hard split of user space and kernel space New bit in control register 55 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

203 Meltdown Mitigation Problem is rooted in hardware Race condition between the memory fetch and corresponding permission check Serialize both of them Hard split of user space and kernel space New bit in control register Fix the hardware long-term solution 55 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

204 Meltdown Mitigation Problem is rooted in hardware Race condition between the memory fetch and corresponding permission check Serialize both of them Hard split of user space and kernel space New bit in control register Fix the hardware long-term solution Can we fix it in software? 55 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

205 Meltdown Mitigation Kernel addresses in user space are a problem 56 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

206 Meltdown Mitigation Kernel addresses in user space are a problem Why don t we take the kernel addresses Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

207 Meltdown Mitigation...and remove them if not needed? 57 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

208 Meltdown Mitigation...and remove them if not needed? User accessible check in hardware is not reliable 57 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

209 Meltdown Mitigation Unmap the kernel in user space 58 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

210 Meltdown Mitigation Unmap the kernel in user space Kernel addresses are then no longer present 58 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

211 Meltdown Mitigation Unmap the kernel in user space Kernel addresses are then no longer present Memory which is not mapped cannot be accessed at all 58 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

212 KAISER Userspace Kernelspace Applications Operating System Memory 59 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

213 KAISER Kernel View User View Userspace Kernelspace Userspace Kernelspace Applications Operating System Memory Applications context switch 60 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

214 KAISER We published KAISER in May Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

215 KAISER We published KAISER in May 2017 as a countermeasure against other side-channel attacks 61 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

216 KAISER We published KAISER in May 2017 as a countermeasure against other side-channel attacks Inadvertently defeats Meltdown as well 61 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

217 KAISER We published KAISER in May 2017 as a countermeasure against other side-channel attacks Inadvertently defeats Meltdown as well PoC implementation for the Linux kernel 61 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

218 KAISER Hardware interrupt while running in user mode Kernel needs to deal with interrupt but does not exist anymore in address space Traps, NMI, system calls, Must map some kernel code in user space 62 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

219 KAISER Need to update CR3 in order to switch to other address space 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

220 KAISER Need to update CR3 in order to switch to other address space How can we do this efficiently? 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

221 KAISER Need to update CR3 in order to switch to other address space How can we do this efficiently? Instead of one PGD, two PGDs are allocated 8k in size and 8k aligned 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

222 KAISER Need to update CR3 in order to switch to other address space How can we do this efficiently? Instead of one PGD, two PGDs are allocated 8k in size and 8k aligned Trick: Just flip bit 12 in the pointer to swap between both halves CR3 Pair CR3 + 0x1000 CR3 User Kernel PGD User PGD Kernel CR3[12] = 1 CR3[12] = 0 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

223 KAISER Need to update CR3 in order to switch to other address space How can we do this efficiently? Instead of one PGD, two PGDs are allocated 8k in size and 8k aligned Trick: Just flip bit 12 in the pointer to swap between both halves CR3 Pair CR3 + 0x1000 CR3 User Kernel PGD User PGD Kernel CR3[12] = 1 CR3[12] = 0 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

224 KAISER Need to update CR3 in order to switch to other address space How can we do this efficiently? Instead of one PGD, two PGDs are allocated 8k in size and 8k aligned Trick: Just flip bit 12 in the pointer to swap between both halves CR3 Pair CR3 + 0x1000 CR3 User Kernel PGD User PGD Kernel CR3[12] = 1 CR3[12] = 0 63 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

225 Kernel Page-table Isolation Intel and others improved KAISER 64 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

226 Kernel Page-table Isolation Intel and others improved KAISER Merged it into upstream as KPTI (Kernel Page-table Isolation) 64 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

227 Kernel Page-table Isolation Intel and others improved KAISER Merged it into upstream as KPTI (Kernel Page-table Isolation) Kernel patches are available for arm64 as well 64 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

228 Apple Apple released updates in ios 11.2, macos and tvos 11.2 to mitigate Meltdown Boot option: -no-shared-cr3 Unmaps the user space while running in kernel mode But not vice versa 65 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

229 KVA Shadow Kernel Virtual Address (KVA) Shadow Meltdown Mitigation for Microsoft Windows 66 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

230 Implementing Introducing such a fundamental change to the operating system is extremely challenging Our PoC implementation contained many bugs as well 67 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

231 Total Meltdown Discovered by Ulf Frisk in the security update CVE Modified the PML4 entry of 0x1ed to allow to access page from user-mode On Windows 7 and Server 2018 R2: Self-Referencing Entry Allows to read and modify entire physical memory 68 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

232 What now?

233 Future More attacks exploiting performance optimizations in hardware New variants are disclosed frequently 69 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

234 A unique chance A unique chance to rethink processor design grow up, like other fields (car industry, construction industry) 70 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

235 Proof-of-Concept You can find our proof-of-concept implementation on: 71 Moritz Lipp, Michael Schwarz, Daniel Gruss Graz University of Technology

Performance is awesome!

Performance is awesome! Acknowledgements I Background music for the choir song kindly provided by Kerbo-Kev. Cooking photos kindly provided by Becca Lee (ladyfaceblog). Santa Clause images by http://www.thevectorart.com/ Some