Software-based Microarchitectural Attacks

Transcription

1 Software-based Microarchitectural Attacks Daniel Gruss January 23, 2019 Graz University of Technology Frame Rate of Slide Deck: 11 fps 1 Daniel Gruss Graz University of Technology

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9 CPU Cache printf("%d", i); printf("%d", i); 4 Daniel Gruss Graz University of Technology

10 CPU Cache printf("%d", i); printf("%d", i); Cache miss 4 Daniel Gruss Graz University of Technology

11 CPU Cache printf("%d", i); printf("%d", i); Cache miss Request 4 Daniel Gruss Graz University of Technology

12 CPU Cache printf("%d", i); printf("%d", i); Cache miss Request Response 4 Daniel Gruss Graz University of Technology

13 CPU Cache printf("%d", i); printf("%d", i); Cache miss i Request Response 4 Daniel Gruss Graz University of Technology

14 CPU Cache printf("%d", i); printf("%d", i); Cache miss Cache hit i Request Response 4 Daniel Gruss Graz University of Technology

15 CPU Cache DRAM access, slow printf("%d", i); printf("%d", i); Cache miss Cache hit i Request Response 4 Daniel Gruss Graz University of Technology

16 CPU Cache DRAM access, slow printf("%d", i); printf("%d", i); Cache miss Cache hit i No DRAM access, much faster Request Response 4 Daniel Gruss Graz University of Technology

17 Flush+Reload ATTACKER Shared Memory VICTIM flush access access 5 Daniel Gruss Graz University of Technology

18 Flush+Reload ATTACKER Shared Memory VICTIM flush access cached Shared Memory cached access 5 Daniel Gruss Graz University of Technology

19 Flush+Reload ATTACKER Shared Memory VICTIM flush access Shared Memory access 5 Daniel Gruss Graz University of Technology

20 Flush+Reload ATTACKER Shared Memory VICTIM flush access access 5 Daniel Gruss Graz University of Technology

21 Flush+Reload ATTACKER Shared Memory VICTIM flush access access 5 Daniel Gruss Graz University of Technology

22 Flush+Reload ATTACKER Shared Memory VICTIM flush access Shared Memory access 5 Daniel Gruss Graz University of Technology

23 Flush+Reload ATTACKER Shared Memory VICTIM flush access Shared Memory access 5 Daniel Gruss Graz University of Technology

24 Flush+Reload ATTACKER Shared Memory VICTIM flush access Shared Memory access fast if victim accessed data, slow otherwise 5 Daniel Gruss Graz University of Technology

25 Memory Access Latency Cache Hits Number of accesses Access time [CPU cycles] 6 Daniel Gruss Graz University of Technology

26 Memory Access Latency Cache Hits Cache Misses Number of accesses Access time [CPU cycles] 6 Daniel Gruss Graz University of Technology

27 Cache Template Attack Demo

28 Cache Template Address 0x7c680 0x7c6c0 0x7c700 0x7c740 0x7c780 0x7c7c0 0x7c800 0x7c840 0x7c880 0x7c8c0 0x7c900 0x7c940 0x7c980 0x7c9c0 0x7ca00 0x7cb80 0x7cc40 0x7cc80 0x7ccc0 0x7cd00 Key g h i j k l m n o p q r s t u v w x y z 8 Daniel Gruss Graz University of Technology

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30 Back to Work

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33 Wait for an hour

34 Wait for an hour LATENCY

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36 Dependency Parallelize

37 Out-of-order Execution int width = 10, height = 5; float diagonal = sqrt ( width * width + height * height ); int area = width * height ; printf (" Area %d x %d = %d\n", width, height, area ); 10 Daniel Gruss Graz University of Technology

38 Out-of-order Execution Dependency int width = 10, height = 5; float diagonal = sqrt ( width * width + height * height ); int area = width * height ; Parallelize printf (" Area %d x %d = %d\n", width, height, area ); 10 Daniel Gruss Graz University of Technology

39 Building Meltdown char data = *( char *) 0 xffffffff81a000e0 ; printf ("%c\n", data ); 11 Daniel Gruss Graz University of Technology

40 Building Meltdown char data = *( char *) 0 xffffffff81a000e0 ; printf ("%c\n", data ); segfault at ffffffff81a000e0 ip sp ffce4a80610 error 5 in reader 11 Daniel Gruss Graz University of Technology

41 Building Meltdown Adapted code *( volatile char *) 0; array [84 * 4096] = 0; // unreachable 12 Daniel Gruss Graz University of Technology

42 Building Meltdown Flush+Reload over all pages of the array Access time [cycles] Page 13 Daniel Gruss Graz University of Technology

43 Building Meltdown Flush+Reload over all pages of the array Access time [cycles] Page This also works on AMD and ARM! 13 Daniel Gruss Graz University of Technology

44 Building Meltdown Combine the two things char data = *( char *) 0 xffffffff81a000e0 ; array [ data * 4096] = 0; 14 Daniel Gruss Graz University of Technology

45 Building Meltdown Flush+Reload again... Access time [cycles] Page... Meltdown actually works. 15 Daniel Gruss Graz University of Technology

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47 Take the kernel addresses... Kernel addresses in user space are a problem (the wall does not work) 17 Daniel Gruss Graz University of Technology

48 Take the kernel addresses... Kernel addresses in user space are a problem (the wall does not work) Why don t we take the kernel addresses Daniel Gruss Graz University of Technology

49 ...and remove them...and remove them if not needed? 18 Daniel Gruss Graz University of Technology

50 ...and remove them...and remove them if not needed? User accessible check in hardware is not reliable 18 Daniel Gruss Graz University of Technology

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52 Kernel Address Isolation to have Side channels Efficiently Removed

53 KAISER /ˈkʌɪzə/ 1. [german] Emperor, ruler of an empire 2. largest penguin, emperor penguin Kernel Address Isolation to have Side channels Efficiently Removed

54 Speculative Execution Let us get rid of bottlenecks 19 Daniel Gruss Graz University of Technology

55 Speculative Execution Use the naughty/nice list of last year 19 Daniel Gruss Graz University of Technology

56 Speculative Execution Finally, check predictions with list of this year 19 Daniel Gruss Graz University of Technology

57 Speculative Execution Throwing away wrongly manufactured presents 19 Daniel Gruss Graz University of Technology

58 Speculative Execution Correct predictions result in free time 19 Daniel Gruss Graz University of Technology

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60 Spectre-PHT (aka Spectre Variant 1) LUT index = 0; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

61 Spectre-PHT (aka Spectre Variant 1) LUT index = 0; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

62 Spectre-PHT (aka Spectre Variant 1) LUT index = 0; char* data = "textkey"; if (index < 4) Speculate els e en th Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

63 Spectre-PHT (aka Spectre Variant 1) LUT index = 0; char* data = "textkey"; if (index < 4) Execute Index t Prediction LUT[data[index] * 4096] 21 els e en th 0 Daniel Gruss Graz University of Technology

64 Spectre-PHT (aka Spectre Variant 1) LUT index = 1; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

65 Spectre-PHT (aka Spectre Variant 1) LUT index = 1; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

66 Spectre-PHT (aka Spectre Variant 1) LUT index = 1; char* data = "textkey"; if (index < 4) Index e Speculate els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

67 Spectre-PHT (aka Spectre Variant 1) LUT index = 1; char* data = "textkey"; if (index < 4) Index e then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

68 Spectre-PHT (aka Spectre Variant 1) LUT index = 2; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

69 Spectre-PHT (aka Spectre Variant 1) LUT index = 2; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

70 Spectre-PHT (aka Spectre Variant 1) LUT index = 2; char* data = "textkey"; if (index < 4) Speculate els en th e Prediction Index x LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

71 Spectre-PHT (aka Spectre Variant 1) LUT index = 2; char* data = "textkey"; if (index < 4) then Prediction Index x LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology else

72 Spectre-PHT (aka Spectre Variant 1) LUT index = 3; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

73 Spectre-PHT (aka Spectre Variant 1) LUT index = 3; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

74 Spectre-PHT (aka Spectre Variant 1) LUT index = 3; char* data = "textkey"; if (index < 4) Speculate Index t Prediction LUT[data[index] * 4096] 21 els e en th 0 Daniel Gruss Graz University of Technology

75 Spectre-PHT (aka Spectre Variant 1) LUT index = 3; char* data = "textkey"; if (index < 4) Index t then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

76 Spectre-PHT (aka Spectre Variant 1) LUT index = 4; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

77 Spectre-PHT (aka Spectre Variant 1) LUT index = 4; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

78 Spectre-PHT (aka Spectre Variant 1) LUT index = 4; Index K char* data = "textkey"; if (index < 4) Speculate els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

79 Spectre-PHT (aka Spectre Variant 1) LUT index = 4; Index K char* data = "textkey"; if (index < 4) Execute els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

80 Spectre-PHT (aka Spectre Variant 1) LUT index = 5; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

81 Spectre-PHT (aka Spectre Variant 1) LUT index = 5; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

82 Spectre-PHT (aka Spectre Variant 1) LUT index = 5; Index E char* data = "textkey"; if (index < 4) Speculate els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

83 Spectre-PHT (aka Spectre Variant 1) LUT index = 5; Index E char* data = "textkey"; if (index < 4) Execute els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

84 Spectre-PHT (aka Spectre Variant 1) LUT index = 6; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

85 Spectre-PHT (aka Spectre Variant 1) LUT index = 6; char* data = "textkey"; if (index < 4) then Prediction else LUT[data[index] * 4096] 0 21 Daniel Gruss Graz University of Technology

86 Spectre-PHT (aka Spectre Variant 1) LUT index = 6; char* data = "textkey"; Index Y if (index < 4) Speculate els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

87 Spectre-PHT (aka Spectre Variant 1) LUT Index Y index = 6; char* data = "textkey"; if (index < 4) Execute els en th e Prediction LUT[data[index] * 4096] 21 0 Daniel Gruss Graz University of Technology

88 Systematization Tree prediction Transient cause? fault microarchitectural buffer Spectre-type fault type Meltdown-type in-place (IP) vs., out-of-place (OP) mistraining strategy Cross-address-space Spectre-PHT Same-address-space Spectre-BTB Spectre-RSB Spectre-STL Meltdown-NM Meltdown-AC Meltdown-DE Meltdown-PF Meltdown-UD Meltdown-SS Meltdown-BR Meltdown-GP Cross-address-space Same-address-space Cross-address-space Same-address-space Meltdown-US Meltdown-P Meltdown-RW Meltdown-PK Meltdown-XD Meltdown-SM Meltdown-MPX Meltdown-BND PHT-CA-IP PHT-CA-OP PHT-SA-IP PHT-SA-OP BTB-CA-IP BTB-CA-OP BTB-SA-IP BTB-SA-OP RSB-CA-IP RSB-CA-OP RSB-SA-IP RSB-SA-OP 22 Daniel Gruss Graz University of Technology

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90 Mitigations Attack Defense InvisiSpec SafeSpec DAWG RSB Stuffing Retpoline Poison Value Index Masking Site Isolation SLH YSNB IBRS STIPB IBPB Serialization Taint Tracking Timer Reduction Sloth SSBD/SSBB Intel ARM AMD Spectre-PHT Spectre-BTB Spectre-RSB Spectre-STL Spectre-PHT Spectre-BTB Spectre-RSB Spectre-STL Spectre-PHT Spectre-BTB Spectre-RSB Spectre-STL Mitigated ( ), partially mitigated ( ), not mitigated ( ), theoretically mitigated ( ), theoretically impeded ( ), not theoretically impeded ( ), or out of scope ( ). 23 Daniel Gruss Graz University of Technology

91 Conclusions new class of attacks 24 Daniel Gruss Graz University of Technology

92 Conclusions new class of attacks many problems to solve around microarchitectural attacks and especially transient execution attacks 24 Daniel Gruss Graz University of Technology

93 Conclusions new class of attacks many problems to solve around microarchitectural attacks and especially transient execution attacks dedicate more time into identifying problems and not solely in mitigating known problems 24 Daniel Gruss Graz University of Technology

94 Software-based Microarchitectural Attacks Daniel Gruss January 23, 2019 Graz University of Technology 25 Daniel Gruss Graz University of Technology