Section 28. WDT and SLEEP Mode

Transcription

1 Section 28. WDT and SLEEP Mode HIGHLIGHTS This section of the manual contains the following major topics: Introduction Control Register Watchdog Timer (WDT) Operation SLEEP (Power-Down) Mode Initialization Design Tips Related Application Notes Revision History and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-1

2 PIC18C Reference Manual 28.1 Introduction The Watchdog Timer and SLEEP functions are two functions that can enhance the system. The Watchdog Timer may be used to return to operating mode, or to cause a controller RESET if the program begins to behave erratically. This enhances the overall operation of the system. The Watchdog Timer (WDT) is a free running on-chip RC oscillator that does not require any external components. The block diagram is shown in Figure This RC oscillator is separate from the device RC oscillator of the OSC1/CLKI pin. This means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO pins has been stopped, for example, by execution of a SLEEP instruction. The Watchdog Timer (WDT) is enabled/disabled by a device configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN configuration bit is cleared, the SWDTEN bit enables/disables the operation of the WDT. Figure 28-1: Watchdog Timer Block Diagram WDT Timer Postscaler to - 1 MUX WDTPS<2:0> WDTEN Configuration bit SWDTEN bit WDT Time-out Note: WDTPS2:WDTPS0 are bits in a configuration register. The SLEEP function halts controller activity and reduces current consumption to a minimum. The SLEEP mode is a reduced power state, where it is possible to halt almost all activity in the controller. In this mode, power consumption is very low, allowing for long term operation from battery powered applications. Normal operation may be resumed when any of several interrupts occur, the WDT times out, or a RESET occurs. DS39529A-page Microchip Technology Inc.

3 Section 28. Watchdog Timer and SLEEP Mode 28.2 Control Register Register 28-1 shows the WDTCON register. This is a readable and writable register that contains the SWDTEN control bit. If the WDT enable configuration bit has been cleared, this software controlled bit enables or disables the WDT. Register 28-1: WDTCON Register U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 SWDTEN bit 7 bit 0 bit 7:1 Unimplemented: Read as 0 bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit is 0 Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset 1 = bit is set 0 = bit is cleared x = bit is unknown 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-3

4 PIC18C Reference Manual 28.3 Watchdog Timer (WDT) Operation WDT Period Clearing the WDT Counter WDT Considerations Effects of a RESET During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. This is known as a WDT wake-up. The WDT can be permanently enabled by setting the WDTEN configuration bit. If the WDT configuration bit disables the WDT, then software can be used to enable/disable the WDT through setting/clearing the SWDTEN bit. The WDT has a nominal time-out period of 18 ms with no postscaler (see the Electrical Specifications section, parameter 31). The time-out period varies with temperature, VDD and process variations from part to part (see DC parameters in the Electrical Specifications section). If longer time-outs are desired, a postscaler with a division ratio of up to 1:128 can be assigned to the WDT. Thus, time-out periods of up to 2.3 seconds can be realized. The postscaler assignment is specified at time of device programming through the device configuration bits. The CLRWDT and SLEEP instructions clear the WDT counter and the WDT postscaler which prevents it from timing out and generating a device RESET. When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. The TO bit in the RCON register will be cleared upon a Watchdog Timer time-out (WDT Reset and WDT wake-up). The CLRWDT instruction will force the count value of the WDT counter to 0. When the WDT is disabled (WDTEN configuration bit = 0 and SWDTEN is clear), the WDT counter is forced to 0 and the internal WDT clock source is disabled. Then, when the WDT is enabled (setting the SWDTEN bit when previously cleared), the WDT counter starts from a value of 0. It should also be taken in account that under worst case conditions (VDD = Minimum, Temperature = Maximum, WDT postscaler = Maximum), it may take several seconds before a WDT time-out occurs. When a device RESET occurs, the Watchdog Timer counter and postscaler counter are cleared and the TO bit is set. Table 28-1: Summary of Watchdog Timer Registers Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H WDTPS2 WDTPS1 WDTPS0 WDTEN WDTCON SWDTEN RCON IPEN LWRT RI TO PD POR BOR Legend: Shaded cells are not used by the Watchdog Timer. DS39529A-page Microchip Technology Inc.

5 Section 28. Watchdog Timer and SLEEP Mode 28.4 SLEEP (Power-Down) Mode Wake-up from SLEEP SLEEP (Power-down) mode is the lowest current consumption state and is entered by executing a SLEEP instruction. The device oscillator is turned off, so no system clocks are occurring in the device. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the RCON register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, withno external circuitry drawing current from the I/O pin and modules that are specified to have a delta SLEEP current, should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally, to avoid switching currents caused by floating inputs. The contribution from on-chip pull-ups on PORTB should be considered. During SLEEP, the MCLR pinmustbeatavalidhigh. Some features of the device consume a delta current. These are enabled/disabled by device configuration bits. These features include the Watchdog Timer (WDT), LVD, and Brown-out Reset (BOR) circuitry modules. There are several ways to wake the controller from SLEEP. The WDT can wake-up the controller when it times out. A RESET will wake the controller and cause the program to restart, and interrupts (from peripherals or external sources) will wake the controller from SLEEP. The device can wake-up from SLEEP through one of the following events: 1. Any device RESET, such as MCLR pin = VIL, VDD =VBOR (if enabled). 2. Watchdog Timer Wake-up (if WDT was enabled). 3. Any peripheral module which can set its interrupt flag while in SLEEP, such as: - An external INT pin - Change on Port pin - Comparators -A/D -Timer1 -Timer3 -LVD - MSSP - Capture - PSP read or write - CCP1 - CCP2 - Addressable USART - PORTB Interrupt on Change - External Interrupts - Parallel Slave Port - Voltage Reference (bandgap) -WDT The first event will RESET the device upon wake-up. However, the latter two events will wake the device and then resume program execution. The TO and PD bits in the RCON register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if WDT time-out occurred (and caused a wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-5

6 PIC18C Reference Manual Wake-up Using Interrupts When interrupts are globally disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following events will occur: If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bit will not be cleared. If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is clear, a CLRWDT instruction should be executed before a SLEEP instruction. Figure 28-2: Wake-up from SLEEP Through Interrupt OSC1 CLKOUT (4) INT pin Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) INTF flag (INTCON<1>) Interrupt Latency (3) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+2 PC+4 PC+4 PC+4 INT_addr INT_addr + 1 Instruction fetched Inst(PC) = SLEEP Inst(PC + 2) Inst(PC + 4) Inst(INT_addr) Inst(INT_addr + 1) Instruction executed Inst(PC - 1) SLEEP Inst(PC + 2) Dummy cycle Dummy cycle Inst(INT_addr) Note 1: XT,HSorLPoscillatormodeassumed. 2: TOST =1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes. 3: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. DS39529A-page Microchip Technology Inc.

7 Section 28. Watchdog Timer and SLEEP Mode Interrupt sources can wake the controller from SLEEP without actually causing an interrupt. The interrupt source must have its interrupt enable flag set, but GIE does not need to be set. If GIE is clear, the controller will wake without vectoring to an interrupt. If GIE is set, the controller will vector to an interrupt. If interrupt priority is not used, all interrupt priority bits are set. If interrupt priority is used (any interrupt priority bit is cleared), GIEH controls high priority interrupts and GIEL controls low priority interrupts. Table 28-2 shows the response to the interrupt flag bits depending on the state of the interrupt enable and priority bits. Table 28-2: Interrupt Source Any interrupt source that operates during SLEEP Legend: X is don t care. SLEEP Mode, Interrupt Enable Bits, and Interrupt Results GIE/GIEH PEIE/GIEL Interrupt Priority Peripheral Interrupt Flag Response to Interrupt X X X 0 SLEEP wake low priority wake high priority 0 0 X 1 wake High priority vector followed Low priority vector followed 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-7

8 PIC18C Reference Manual Effects of SLEEP Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the Watchdog Timer and prescaler counter are cleared (if the WDT is enabled), the on-chip clocks and oscillator are turned off and the controller is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP will increase the current consumed during SLEEP. The user can wake from SLEEP through external RESET, Brown-out Reset (if enabled), external interrupt, Watchdog Timer time-out or a peripheral interrupt. Table 28-3: OSC Mode Oscillator Selections, SLEEP Mode, and Waking from SLEEP OSC1 Pin in SLEEP OSC2 Pin in SLEEP Waking Delays OSC1 in Run OSC2 in Run RC Floating, pulled high At logic low None R and C set frequency RCIO Floating, pulled high Configured as I/O pin None R and C set frequency CLKO (4Tosc) Configured as I/O pin LP TOST (1) XTAL/res XTAL/res XT TOST (1) XTAL/res XTAL/res HS TOST (1) XTAL/res XTAL/res HS w/pll TOST (1) +TPLL (2) XTAL/res XTAL/res EC Driven by external clock source At logic low None Driven by external clock source CLKO (4TOSC) ECIO Driven by external clock source Configured as I/O pin None Driven by external clock source Configured as I/O pin Note 1: OST (Oscillator Start-up Timer) counts 1024 oscillator cycles before allowing controller clocks to resume. This provides time for the oscillator to start-up and stabilize. 2: ATPLL delay is required to allow the PLL to lock to the oscillator frequency. DS39529A-page Microchip Technology Inc.

9 Section 28. Watchdog Timer and SLEEP Mode Wake-up Delays Several factors affect how much time the controller requires to return to operating mode from SLEEP. These include oscillator mode and the use of the PLL. The Oscillator Start-up Timer, OST, counts 1024 oscillator cycles to allow the oscillator to start-up and stabilize before allowing system clocks to resume. The OST is not enabled for RC and EC oscillator modes Oscillator With PLL Enabled Time-out Sequence After Wake-up The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay after a wake-up from SLEEP has occurred oscillator cycles are not a sufficient amount of time to allow the PLL to lock at high frequencies. An additional TPLL time is required to allow the PLL to lock before allowing system clocks to resume. 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-9

10 PIC18C Reference Manual Peripheral Module Operation During SLEEP Table 28-4 gives an overview of which devices operate during SLEEP. For further details, refer to the individual sections in this reference manual. Table 28-4: Peripheral Modules Active in SLEEP Mode Peripheral Module Operates During Mode of Operation Wakes from SLEEP? SLEEP? Timer1, Timer3 Yes External clock/u.s.c.g., Yes Asynchronous Counter mode A/D Yes A/D clock = RC clock Yes CCP1, CCP2 Yes Only capture available. Yes, do not rely on capture value MSSP Yes I 2 C Non-master modes SPI Slave mode Effects of a WDT Time-out Effects of a Device RESET Yes Yes Addressable USART Yes Synchronous slave mode Yes PORTB Interrupt on Yes All Yes Change External Interrupts Yes All Yes Parallel Slave Port Yes All Yes LVD Yes All Yes Volt Reference (bandgap) Yes If required to support LVD, and A/D No WDT Yes All Yes If the WDT has been enabled, either by the WDTEN configuration bit (= 1 ) or by the SWDTEN bit being set, the WDT will wake-up the controller from SLEEP mode and clear the TO bit. When MCLR is asserted, TO is set and PD is clear. All other bits in RCON are unchanged. The controller will resume code execution at the RESET vector address. DS39529A-page Microchip Technology Inc.

11 Section 28. Watchdog Timer and SLEEP Mode 28.5 Initialization No initialization code at this time. 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-11

12 PIC18C Reference Manual 28.6 Design Tips Question 1: My system voltage drops and then returns to the specified device voltage range. The device is not operating correctly and the WDT does not reset and return the device to proper operation. Answer 1: The WDT was not designed to be a recovery from a brown-out condition. It was designed to recover from errant software operation (the device remaining in the specified operating ranges). If your system can be subjected to brown-outs, either the on-chip brown-out circuitry should be enabled or an external brown-out circuit should be implemented. Question 2: Device RESETS even though I do the CLRWDT instruction in my loop. Answer 2: Make sure that the loop with the CLRWDT instruction meets the minimum specification of the WDT (not the typical). Question 3: Device never gets out of RESETS. Answer 3: On power-up, you must take into account the Oscillator Start-up time (Tost). Sometimes it helps to put the CLRWDT instruction at the beginning of the loop, since this start-up time may be variable. DS39529A-page Microchip Technology Inc.

13 Section 28. Watchdog Timer and SLEEP Mode 28.7 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced family (that is, they may be written for the Base-Line, the Mid-Range or High-End families), but the concepts are pertinent and could be used (with modification and possible limitations). The current application notes related to the WDT and SLEEP Mode are: Title Application Note # Power-up Trouble Shooting AN607 Note: Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC18CXXX. The web address for these examples is: 28 and Sleep Mode 2000 Microchip Technology Inc. DS39529A-page 28-13

14 PIC18C Reference Manual 28.8 Revision History Revision A This is the initial released revision of the Enhanced MCU Watchdog Timer and SLEEP mode description. DS39529A-page Microchip Technology Inc.