Table of Contents COMPANY PROFILE 1-1 SECTION 1. INTRODUCTION 1-1

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1 COMPANY PROFILE 1-1 SECTION 1. INTRODUCTION 1-1 Introduction Manual Objective Device Structure Development Support Device Varieties Style and Symbol Conventions Related Documents Related Application Notes Revision History SECTION 2. OSCILLATOR 2-1 Introduction Control Register Oscillator Configurations Crystal Oscillators/Ceramic Resonators External RC Oscillator HS Switching to Low Power Clock Source Effects of Sleep Mode on the On-Chip Oscillator Effects of Device Reset on the On-Chip Oscillator Design Tips Related Application Notes Revision History SECTION 3. RESET 3-1 Introduction Resets and Delay Timers Registers and Status Bit Values Design Tips Related Application Notes Revision History SECTION 4. ARCHITECTURE 4-1 Introduction Clocking Scheme/Instruction Cycle Instruction Flow/Pipelining I/O Descriptions Design Tips Related Application Notes Revision History DS39500A-page iii

2 SECTION 5. CPU AND ALU 5-1 Introduction General Instruction Format Central Processing Unit (CPU) Instruction Clock Arithmetic Logical Unit (ALU) STATUS Register Design Tips Related Application Notes Revision History SECTION 6. HARDWARE 8X8 MULTIPLIER 6-1 Introduction Operation Design Tips Related Application Notes Revision History SECTION 7. MEMORY ORGANIZATION 7-1 Introduction Program Memory Program Counter (PC) Lookup Tables Stack Data Memory Organization Return Address Stack Initialization Design Tips Related Application Notes Revision History SECTION 8. TABLE READ/TABLE WRITE 8-1 Introduction Control Registers Program Memory Enabling Internal Programming External Program Memory Operation Initialization Design Tips Related Application Notes Revision History DS39500A-page iv

3 SECTION 9. SYSTEM BUS 9-1 Revision History SECTION 10. INTERRUPTS 10-1 Introduction Control Registers Interrupt Handling Operation Initialization Design Tips Related Application Notes Revision History SECTION 11. I/O PORTS 11-1 Introduction PORTA, TRISA, and the LATA Register PORTB, TRISB, and the LATB Register PORTC, TRISC, and the LATC Register PORTD, LATD, and the TRISD Register PORTE, TRISE, and the LATE Register PORTF, LATF, and the TRISF Register PORTG, LATG, and the TRISG Register PORTH, LATH, and the TRISH Register PORTJ, LATJ, and the TRISJ Register PORTK, LATK, and the TRISK Register PORTL, LATL, and the TRISL Register Functions Multiplexed on I/O Pins I/O Programming Considerations Initialization Design Tips Related Application Notes Revision History SECTION 12. PARALLEL SLAVE PORT 12-1 Introduction Control Register Operation Operation in SLEEP Mode Effect of a RESET PSP Waveforms Design Tips Related Application Notes Revision History DS39500A-page v

4 SECTION 13. TIMER Introduction Control Register Operation Timer0 Interrupt Using Timer0 with an External Clock Timer0 Prescaler Initialization Design Tips Related Application Notes Revision History SECTION 14. TIMER Introduction Control Register Timer1 Operation in Timer Mode Timer1 Operation in Synchronized Counter Mode Timer1 Operation in Asynchronous Counter Mode Reading and Writing of Timer Timer1 Oscillator Typical Application Sleep Operation Resetting Timer1 Using a CCP Trigger Output Resetting Timer1 Register Pair (TMR1H:TMR1L) Timer1 Prescaler Initialization Design Tips Related Application Notes Revision History SECTION 15. TIMER Introduction Control Register Timer Clock Source Timer (TMR2) and Period (PR2) Registers TMR2 Match Output Clearing the Timer2 Prescaler and Postscaler Sleep Operation Initialization Design Tips Related Application Notes Revision History DS39500A-page vi

5 SECTION 16. TIMER Introduction Control Registers Timer3 Operation in Timer Mode Timer3 Operation in Synchronized Counter Mode Timer3 Operation in Asynchronous Counter Mode Reading and Writing of Timer Timer3 using the Timer1 Oscillator Timer3 and CCPx Enable Timer3 Prescaler bit Mode Timer Reads/Writes Typical Application Sleep Operation Timer3 Prescaler Initialization Design Tips Related Application Notes Revision History SECTION 17. COMPARE/CAPTURE/PWM (CCP) 17-1 Introduction CCP Control Register Capture Mode Compare Mode PWM Mode Initialization Design Tips Related Application Notes Revision History SECTION 18. ECCP 18-1 SECTION 19. SYNCHRONOUS SERIAL PORT (SSP) 19-1 Introduction Control Registers SPI Mode SSP I 2 C Operation Initialization Design Tips Related Application Notes Revision History DS39500A-page vii

6 SECTION 20. MASTER SSP 20-1 Introduction Control Registers SPI Mode MSSP I 2 C Operation Design Tips Related Application Notes Revision History SECTION 21. ADDRESSABLE USART 21-1 Introduction Control Registers USART Baud Rate Generator (BRG) USART Asynchronous Mode USART Synchronous Master Mode USART Synchronous Slave Mode Initialization Design Tips Related Application Notes Revision History SECTION 22. CAN 22-1 Introduction Control Registers for the CAN Module CAN Overview CAN Bus Features CAN Module Implementation Frame Types Modes of Operation CAN Bus Initialization Message Reception Transmission Error Detection Baud Rate Setting Interrupts Timestamping CAN Module I/O Design Tips Related Application Notes Revision History DS39500A-page viii

7 SECTION 23. COMPARATOR VOLTAGE REFERENCE 23-1 Introduction Control Register Configuring the Voltage Reference Voltage Reference Accuracy/Error Operation During Sleep Effects of a Reset Connection Considerations Initialization Design Tips Related Application Notes Revision History SECTION 24. COMPARATOR 24-1 Introduction Control Register Comparator Configuration Comparator Operation Comparator Reference Comparator Response Time Comparator Outputs Comparator Interrupts Comparator Operation During SLEEP Effects of a RESET Analog Input Connection Considerations Initialization Design Tips Related Application Notes Revision History SECTION 25. COMPATIBLE 10-BIT A/D CONVERTER 25-1 Introduction Control Register Operation A/D Acquisition Requirements Selecting the A/D Conversion Clock Configuring Analog Port Pins A/D Conversions Operation During Sleep Effects of a Reset A/D Accuracy/Error Connection Considerations Transfer Function Initialization Design Tips Related Application Notes Revision History DS39500A-page ix

8 SECTION BIT A/D CONVERTER 26-1 Introduction Control Register Operation A/D Acquisition Requirements Selecting the A/D Conversion Clock Configuring Analog Port Pins A/D Conversions Operation During Sleep Effects of a Reset A/D Accuracy/Error Connection Considerations Transfer Function Initialization Design Tips Related Application Notes Revision History SECTION 27. LOW VOLTAGE DETECT 27-1 Introduction Control Register Operation Operation During Sleep Effects of a Reset Initialization Design Tips Related Application Notes Revision History SECTION 28. WDT AND SLEEP MODE 28-1 Introduction Control Register Watchdog Timer (WDT) Operation SLEEP (Power-Down) Mode Initialization Design Tips Related Application Notes Revision History DS39500A-page x

9 SECTION 29. DEVICE CONFIGURATION BITS 29-1 Introduction Configuration Word Bits Program Verification/Code Protection ID Locations Device ID Design Tips Related Application Notes Revision History SECTION 30. IN-CIRCUIT SERIAL PROGRAMMING (ICSP ) 30-1 Introduction Entering In-Circuit Serial Programming Mode Application Circuit Programmer Programming Environment Other Benefits Field Programming of PICmicro OTP MCUs Field Programming of FLASH PICmicros Design Tips Related Application Notes Revision History SECTION 31. INSTRUCTION SET 31-1 Introduction Data Memory Map Instruction Formats Special Function Registers as Source/Destination Fast Register Stack Q Cycle Activity Instruction Descriptions Design Tips Related Application Notes Revision History DS39500A-page xi

10 SECTION 32. ELECTRICAL SPECIFICATIONS 32-1 Introduction Absolute Maximums Voltage vs Frequency Graph Device Voltage Specifications Device Current Specifications Input Threshold Levels I/O Current Specifications Output Drive Levels I/O Capacitive Loading Low Voltage Detect (LVD) EPROM/FLASH/Data EEPROM Comparators and Voltage Reference Timing Parameter Symbology Example External Clock Timing Waveforms and Requirements Example Phase Lock Loop (PLL) Timing Waveforms and Requirements Example Power-up and RESET Timing Waveforms and Requirements Example Timer0 and Timer1 Timing Waveforms and Requirements Example CCP Timing Waveforms and Requirements Example Parallel Slave Port (PSP) Timing Waveforms and Requirements Example SSP and Master SSP SPI Mode Timing Waveforms and Requirements Example SSP I 2 C Mode Timing Waveforms and Requirements Example Master SSP I 2 C Mode Timing Waveforms and Requirements Example USART/SCI Timing Waveforms and Requirements CAN Specifications Example 8-bit A/D Timing Waveforms and Requirements Example 10-bit A/D Timing Waveforms and Requirements Design Tips Related Application Notes Revision History SECTION 33. DEVICE CHARACTERISTICS 33-1 Introduction Characterization vs. Electrical Specification DC and AC Characteristics Graphs and Tables Revision History DS39500A-page xii

11 SECTION 34. DEVELOPMENT TOOLS 34-1 Introduction The Integrated Development Environment (IDE) MPLAB Software Language Support MPLAB-SIM Simulator Software MPLAB Emulator Hardware Support MPLAB High Performance Universal In-Circuit Emulator with MPLAB IDE MPLAB-ICD In-Circuit Debugger MPLAB Programmer Support Supplemental Tools Development Boards Development Tools for Other Microchip Products Related Application Notes Revision History SECTION 35. CODE DEVELOPMENT 35-1 Overview Good Practice Diagnostic Code Techniques Example Scenario and Implementation Implications of Using a High Level Language (HLL) Revision History SECTION 36. APPENDIX 36-1 Appendix A: I 2 C Overview Appendix B: CAN Overview Appendix C: Module Block Diagrams and Registers Appendix D: Register Definitions Appendix E: Migration Tips SECTION 37. GLOSSARY 37-1 Revision History SOURCE CODE Table of Contents INDEX DS39500A-page xiii

12 NOTES: DS39500A-page xiv