Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis,

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1 June 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 Pre-Boot Loader (PBL) & Pre-Boot Initialization (PBI) P2041RDB Introduction QorIQ Configuration Suite (QCS) Example #1: Building New RCW Example #2: Program New RCW to espi interface Example #3: Boot from espi Flash 2 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

3 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

4 The pre-boot loader (PBL) starts loading the RCW (Reset Configuration Word) data from the interface specified by cfg_rcw_src[0:n] configuration inputs and stores that 512 bits of data to the DCFG_RCWSRn registers within the device configuration block. Loading time varies and depends on the source of the RCW. Note that if a hard-coded RCW option is used, this PBL RCW loading process is effectively bypassed and the device is automatically configured according to the specific RCW field encodings preassigned for the given hard-coded RCW option The PBL performs Pre-Boot Initialization (PBI), if enabled by RCW[PBI_SRC] field, by reading data from either the esdhc, SPI, I2C1, or elbc interface and writing to CCSR space or local memory space (SRAM, DDR) before local cores are permitted to boot. If the PBL reports an error during its pre-boot initialization process, the device reset sequence is halted indefinitely, waiting for a hard reset or PORESET_B. Note that non-ccsr-mapped memory space of a module on OCN must not be the target of any pre-boot initialization. 4 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

5 PBL code : Format of Data Structure 1. Preamble : 0xAA55-AA55 (no need to change) 2. Command : Write RCW Status registers : 0x010E-0100 (no need to change) 3. RCW Data : 64 bytes 4. (Optional) PBI commands 5. Command : End 0x (no need to change) 6. CRC : 0xhhhh-hhhh ; CRC32-MPEG2 format Programming PBL codes In Windows : Use CodeWarrior flash programming tool for NOR, NAND and espi flash. In U-boot : Use u-boot commands, tftp, load S-record, etc. 5 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

6 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

7 CPU core speed Multiple SysClk inputs for generating various device frequencies Switch to change system version register from P2041 to P2040 personality Memory DDR3 SO-DIMM 4GB, 1333MHz data rate NOR Flash 128MB single-chip memory SPI Flash 16MB SD connector to interface with an SD memory card PCI Express Two x4 PCI Express slots Ethernet Supports five 10/100/1000 ports with no add-in card dtsec1-dtsec3 as SGMII to PHY VSC8221 dtsec4-dtsec5 as RGMII to PHY VSC8641 Can support 10 GE with Freescale s optional XAUI-RISER card IEEE 1588 connector for Symmetricom option card SATA Two SATA connectors I2C Serial EEPROM boot loader Serial EEPROM board identification Real-time clock Temperature sensor Eight GPIOs on I2C expender USB Two USB2.0 type A receptacles on the front panel UARTs Two DB9 connectors on the rear panel Form Factor PCB Standard board: Micro ATX Enclosure Micro-ATX: 440 x 325 x151 mm 7 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

8 8 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

9 SerDes Interface P2041RDB supports the SGMII, XAUI and PCI Express high-speed serial communication interfaces. The multiplexed selections are controlled by CPLD registers. Enabling XAUI function Default flash image is configured in the P2041 SerDes to support XAUI rising card. But you need add the following lane mux commands in uboot to enable XAUI card on Bank0. Controlled by CPLD =>cpld lane_mux a 0 =>cpld lane_mux c 0 =>cpld lane_mux d 0 =>cpld reset altbank <switch to bank1> 9 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

10 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

11 You need either CodeWarrior for PA 10.1 or later OR, you download an Eclipse version for free OR, you use an existing Eclipse workbench you have installed (Wind River, QNX, GNU, etc.) Processor Expert for QorIQ Configuration Suite installs using the Eclipse updater s Add new software capability. The updated version of QCS is 2.3.x which can be downloaded here: gn_tools_tab The Configuration Suite is 100% pure Java so it should run on any Eclipse or later host environment (Windows, Linux, Solaris, Mac OS, 32-bit/64-bit, ) 11 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

12 Create a new QorIQ Configuration project Use File > New > QorIQ Set project name. e.g. ex1 Click Next 12 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

13 Select target SOC Expand and select the appropriate QorIQ processor Choose a silicon revision Click Next 13 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

14 Select Toolset Expand and select the appropriate Toolset components Check PBL Click Next 14 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

15 PBL Configuration Click Import configuration from an existing PBL file Click Browse Browse rcw\rr_px_0x09\rcw_14g_15 00mhz.bin in local folder Select Binary for File Format Click Finish 15 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

16 Modify RCW Expand and Click PBL1:PBL in Project Panel Select Properties tag under Component Inspector Change the system clock frequency Modify other configuratio ns wherever necessary 16 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

17 Change SerDes protocol setting Select SRDS_PRTC L under RCW Change the setting to 0x19 Save your work Notes: May need to modify SerDes clock ratio if different protocol speed is selected in corresponding SerDes Bank 17 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

18 Output Formats : XXD Object Dump : aa55 aa55 010e a U.U...Z : 1e1e 181e 0000 cccc c3c @F@.<< Usage : Convert to BINARY format by the command, > xxd r rcw.xxd rcw.bin S-record S AA55AA55010E A E1E181E0000CCCC C3C2000FC S FE800000E B Usage : In u-boot, use loads command U-Boot commands mw.l 0x xAA55AA55 mw.l 0x x010E0100 Usage : Use copy & paste in U-boot console Hex string AA55AA55010E A0 Usage : Convert to Binary format by using hex to binary tools. > xxd r p rcw.hex > rcw.bin Binary format (supported by QCS v2.x but not in QCS v1.x) The RCW in binary format can be downloaded to memory in PA10 and u-boot for programming. 18 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

19 Code generation is invoked by clicking on the Project > Generate Processor Expert Code menu item. For PBL component, the PBL data is generated into a file within the Generated Code directory of the project. 19 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

20 Go to the Generated_Code folder in the project tree Find component s generated code here. 20 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

21 Step 1: Import and decode rcw_14g_1500mhz.bin file in QCS Platform clock : 750MHz Core clock : 1.5GHz FMAN1/2 clock : 583MHz DDR clock : 667MHz ( 1.333GHz data rate) SD_REF_CLK1: 100MHz SD_REF_CLK2: 125MHz SRDS_PRTCL: 0x09 21 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

22 Step 2: use PBL tool to change SerDes protocol setting to support four SGMII and one PCIe x2 on Bank 1 and two SATA on Bank 2 Answer: SRDS_PRTCL:0x19 SRDS_RATIO_B2:24:1 SerDes PLL 2 Clock: 3.000GHz Step 3: use PBL tool to generate new RCW and compare it with rcw_5g_1500mhz.bin 22 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

23 Step1: Power off the board and change the SYSCLK to 83.3MHz. (SW1[6:8]= ON OFF OFF) Step2: Power on the board Step3: Write the new PBL code in exercise #3 to DDR memory, address 0x using u-boot commands Method #1 : tftp ; Use binary format RCW Method #2 : loady ; Send binary format RCW via ymodem protocol Method #3 : loads ; Select S-record RCW Method #4 : mw.l commands ; Select RCW in u-boot commands Example : mw.l 0x xAA55AA55 mw.l 0x x010E0100 Select U-Boot commands as the output format under PBL Data in QCS and offset = 0x Step4: Program PBL at 0x to espi flash offset 0x0 sf probe 0 sf erase sf write x50 Step5: Turn off the power supply and change the RCW source to espi interface RCW Source : espi => CFG_RCW_SRC[0:4] =0_0101 (SW1[5:1] = OFF OFF ON OFF ON) Power on the P2041RDB and check the RCW source from the console Validate the RCW source in PORSR1[RCW_SRC], CCSRBAR + 0xE0000 => md fe0e0000 fe0e0000: 85fbff02 b Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

24 SPI and SD boot are both available on P2041RDB. The bootup process can be divided into two stages: The first stage will load RCW and write configuration registers to initialize SPI interface, and configure one CPC as 1M SRAM, and loads U-boot image to the CPC. The second stage will configure all the hardware and boot up to U-Boot command line. The PBL image contains three parts and can be produced by Processor Expert tool. 1. RCW, 2. PBI commands performs configuration registers write, KB u-boot image. 24 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

25 Step1: Open a New project in Processor Expert and Import rcw_14g_1500mhz.bin file Step2: Change the PBI_SRC to SPI 24b Addressing and BOOT_LOC to Memory Complex 1 Step3: Click PBI Data Input, a PBI Data Input editor will pop up Step 4: Product ACS file, use following command to convert the u-boot-spi-p2041rdb_spiflash-git-r30.bin to a xxd object dump file. xxd u-boot.bin > u-boot.xxd 25 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

26 Step5: paste PBI commands into text field. Then select "ACS File (XXD Object Dump)", change Offset to "f80000 for the next step. Common PBI Command (without any workaround) #Clear CPC c #Initialize CPC1 as 1MB SRAM fff0000b 09010f #Configure LAW for CPC d d04 fff d ff #Initialize espi controller d c #Flush data c Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

27 Step6: click Browse" to select the file "u-boot.xxd" produced above, and click "Add", content of the "u-boot.xxd" will be pasted after the commands PBI commands u-boot.xxd 27 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

28 Step7: Pastes " " and "091380c " at the end of the code in order to flush the data again. Click "Apply PBL Data Structure RCW PBI Commands U-boot.xxd PBI Commands 28 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

29 Step 8: Click Generate Processor Expert Code in menu Project. After it finished, click Generated_Code in Project Panel window and PBL1.pbl appears. Find the file "PBL1.pbl" in workspace of this project and convert PBL1.pbl to PBL binary file using the following command. This file will be programmed to SPI flash. xxd -r PBL1.pbl > u-boot.pbl (For QCS v2.x, Step 8 can be simplified by changing the PBL Data Output Format to Binary in Component Inspector and the output file will be called PBL1.bin. Rename it to u-boot.pbl or just keep this filename for tftp) Step 9: Program PBL file at 0x to espi flash offset 0x0 => tftp u-boot.pbl => sf probe 0 => sf erase => sf write $filesize Step 10: write ucode to espi from offset 0x =>tftp ucode.bin =>sf erase =>sf write $filesize Step 11: Turn off the power supply and change the RCW source to espi interface RCW Source : espi => CFG_RCW_SRC[0:4] =0_0101 (SW1[5:1] = OFF OFF ON OFF ON) Step 12: Power on the P2041RDB and check the RCW source from the console Validate the RCW source in PORSR1[RCW_SRC], CCSRBAR + 0xE0000 => md fe0e0000 fe0e0000: 85fbff02 b Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

30 Some workarounds can be applied to processor using PBI commands Here are 2 workarounds added in form of PBI commands: A : CoreNet fabric (CCF) can exhibit a deadlock under certain traffic patterns causing the system to hang (affects P2041, P3041, and P4080) A : Internal tracking loop can falsely lock causing unrecoverable bit errors (affects P204x, P3041, P4080, P5020, and P5040) Pay attention to the sequence of these PBI commands 1) Workaround(s) first, and then 2) Common PBI commands. 30 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

31 Below are PBI commands for workaround of A : Workaround PBI Command #workaround of A C C C C C C D C C4 890B C C4 890B C C4 890B C C4 890B C C4 890B C C4 890B C C4 890B C C4 31 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

32 Below are PBI commands for workaround of A for P2041 for a given platform with a given Serdes protocol Workaround PBI Command # for p2041rdb/rr_px_0x09/rcw_14g_1500mhz (a given platform with a given Serdes protocol) #define A4580_HAS_B2_LCD #B1TTLCRC0 090ea4a0 1b ea4a ea4b #B1TTLCRD0 090ea4e0 1b ea4e ea4f #B1TTLCRE0 090ea520 1b ea ea #B1TTLCRF0 090ea560 1b ea ea #B1TTLCRG0 090ea5a0 1b ea5a ea5b #B1TTLCRH0 090ea5e0 1b ea5e ea5f Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

33 #B1TTLCRI0 090ea620 1b ea ea #B1TTLCRJ0 090ea660 1b ea ea #B2TTLCRA0 090ea820 1b ea ea #B2TTLCRB0 090ea860 1b ea ea #ifdef A4580_HAS_B2_LCD #B2TTLCRC0 090ea8a0 1b ea8a ea8b #B2TTLCRD0 090ea8e0 1b ea8e ea8f #endif 1) PBI commands wrapped by #ifdef are needed specifically, should copy them according to the defines for a given platform and a given SerDes protocol; 2) PBI commands not wrapped by #ifdef are needed generally, they are needed for all platforms and all SerDes protocols; 33 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMAROS, Tower, TurboLink, Vybrid and

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