How to use imxrt Low Power feature

Transcription

1 NXP Semiconductors Document Number: AN12085 Application Note Rev. 0, 11/2017 How to use imxrt Low Power feature 1. Introduction This document discusses about low power application design and power consumption measurement on i.mxrt. Low power is a very important feature on i.mxrt. 2. Chip overview This section provides main features of i.mx RT chips i.mx RT chip overview The i.mx RT chip is a Cortex-M7 based chip that operates at speeds up to 600MHz to provide high CPU performance and best real-time response. Cortex-M7 based processor which can operates at speed up to 600MHz. Contents 1. Introduction Chip overview i.mx RT chip overview Low Power Overview Power Supply Run Mode Low Power Mode Power Mode Switch example Application Description Low Power Application Design General description Low Power Mode Enter & Exit Sequence Low Power Design Point Conclusion Revision history Reference KB on-chip RAM which can be flexibly configured as TCM or general-purpose on chip RAM. Advanced power management module with DCDC and LDO to reduces complexity of external power supply and simplifies power sequencing. Various memory interfaces, including SDRAM, Raw NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI NXP B.V.

2 Low Power Overview A wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. Rich audio & video features, including LCD display, basic 2D graphics, camera interface, SPDIF and I2S audio interface. Provide rich peripheral modules, such as SPI, I2C, Can, Ethernet, Flex-Timers, ADC, etc. Target at Industrial HMI, Motor Control and Home Appliance areas. 3. Low Power Overview 3.1. Power Supply Table 1 shows the external power supply rails of i.mxrt. Table 1. External power supply rails Power Rail Description DCDC_IN Power for DCDC. VDD_HIGH_IN Power for analog. VDD_SNVS_IN Power for SNVS and RTC. USB_OTG1_VBUS Power for USB VBUS. USB_OTG2_VBUS VDDA_ADC Power for 12-bit ADC. VDDA_IN Power for LDO_2P5 and 1P1. NVCC_SD0 Power for GPIO in SDIO1 bank (3.3V mode). Power for GPIO in SDIO1 bank (1.8V mode). NVCC_SD1 Power for GPIO in SDIO2 bank (3.3V mode). Power for GPIO in SDIO2 bank (1.8V mode). NVCC_GPIO IO Power for GPIO in GPIO bank. NVCC_EMC IO Power for GPIO in EMC bank. 2 NXP Semiconductors

3 Low Power Overview 3.2. Run Mode Run Mode Definition Table 2. Run Mode Definition Run Mode Definition Overdrive Run CPU runs at 600MHz, overdrive voltage to 1.25V Bus frequency at full speed All the peripheral is enable and runs at target frequency Full Speed Run CPU runs at 528MHz, full loading, lower voltage to 1.15V Bus frequency at full speed All the peripheral is enable and runs at target frequency Low Speed Run CPU runs at 132MHz, lower voltage to 1.15V Internal bus frequency at half speed Some PLL are powered down 20% peripheral are active, others are in low power mode Low Power Run CPU runs at 24MHz, lower voltage to 0.95V Internal bus frequency at 12MHz All PLLs are powered down, OSC24M powered down, RCOSC24 enabled High-speed peripherals are power down In general, we divide RUN mode into those four modes. The Low Speed Run mode uses bus clock in Full Speed Run mode as core clock and Low Power Run mode uses 24MHz internal OSC as core clock source Run Mode Configuration Table 3. Run Mode Configuration Overdrive Run Full Speed Run Low Speed Run Low Power Run CCM LPM Mode RUN RUN RUN RUN NXP Semiconductors 3

4 Low Power Overview CPU Core 600MHz 528MHz 132Mhz 24MHz L1 Cache ON ON ON ON FlexRAM ON ON ON ON SOC Voltage 1.25V 1.15V 1.15V 0.95V Analog LDO ON ON ON In Weak Mode 24MHz XTAL OSC ON ON ON OFF 24MHz RC OSC OFF OFF OFF ON System PLL ON ON ON OFF All Other PLLs ON ON On as needed On as needed Module Clock ON ON On as needed Peripheral clock off RTC32K ON ON ON ON 3.3. Low Power Mode Low Power Mode Definition Table 4. Low Power Mode Definition Low Power Mode System Idle Low Power Idle Suspend Definition CPU can automatically enter this mode when no thread running All the peripheral can remain active CPU only enter WFI mode, it will have its state retained so the interrupt response can be very short Much lower power than System Idle mode, with longer exit time All PLLs are shut off, analog modules running in low power mode All high-speed peripherals are power gated, low speed peripherals can remain running at low frequency The most power saving mode with longest exit time All PLLs are shut off, XTAL are off, all clocks are shut off except 32K clock 4 NXP Semiconductors

5 Low Power Overview All high-speed peripherals are power gated, low speed peripherals are clock gated SNVS All SOC digital logic, analog modules are shut off only except SNVS domain 32KHz RTC is alive Low Power Mode Configuration Table 5. Low Power Mode Configuration System Idle Low Power Idle Suspend SNVS CCM LPM Mode WAIT WAIT STOP - ARM Core (PDM7) WFI WFI Power Down OFF L1 Cache ON ON Power Down OFF FlexRAM (PDRET) ON ON ON OFF FlexRAM (PDRAM0) ON ON Power Down OFF FlexRAM (PDRAM1) ON/OFF ON/OFF Power Down OFF VDD_SOC_IN Voltage 1.15V 0.95V 0.925V OFF 528 PLL ON Power Down Power Down OFF Other PLL Power Down Power Down Power Down OFF 24MHz XTAL OSC ON OFF OFF OFF 24MHz RC OSC OFF ON OFF OFF LDO2P5 ON OFF OFF OFF LDO1P1 ON OFF OFF OFF WEAK2P5 OFF ON OFF OFF WEAK1P1 OFF ON OFF OFF Bandgap ON OFF OFF OFF Low Power Bandgap ON ON ON OFF AHB clock 33MHz 12MHz OFF OFF NXP Semiconductors 5

6 Power Mode Switch example IPG clock 33MHz 12MHz OFF OFF PER clock 33MHz 12MHz OFF OFF Module Clocks ON as needed ON as needed OFF OFF RTC32K ON ON ON ON NOTE Before entering low power mode, each module will be enabled or disable as the configuration table describes. But don't forget to restore those settings when wakeup Wake up source Table 6. Wake up source System Idle Low Power Idle Suspend SNVS GPIO wakeup YES YES YES - YES (1 PIN only) RTC wakeup YES YES YES YES USB remote wakeup YES YES YES NO Other wakeup source YES YES ON NO NOTE No matter in System Idle, Low Power Idle or Suspend mode, user need to enable the wakeup interrupt in GPC module, or, the wakeup will fail. The only pin that can wakeup the system in SNVS is IOMUXC_SNVS_WAKEUP_GPIO5_IO00. This document will not discuss about USB remote wakeup. 4. Power Mode Switch example 4.1. Application Description The power mode switch example is designed to simulate a customer low power application case. Features: FreeRTOS & Tickless feature support. 6 NXP Semiconductors

7 Power Mode Switch example Support all RUN and low power modes switch. Support run after WFI instruction and reset in suspend reset (controlled by macro). Simulate two running tasks and show task status in power mode switch.application usage Power Mode Switch Menu NXP Semiconductors 7

8 Power Mode Switch example In this menu, user can switch power modes and wakeup from idle, suspend modes Task status show When user select to transfer to a new power mode. The task status will be shown. 1. Start working 2. Power mode transition e.g. Overrun => System Idle Wakeup transfer back to Overrun Wakeup Source Two wakeup source can be selected for System Idle, Low Power Idle and Suspend mode, SW8 key (on EVK board) and GPT timer. SW8 user key wakeup. GPT timer wakeup. When choose GPT timer as wakeup source, another menu will ask user to input a durat ion from 1s to 9s to wake up. 8 NXP Semiconductors

9 5. Low Power Application Design This chapter will give some guides in designing a low power application. Also, we ll give some code examples about low power module enable & disable General description Enter a low power mode is a set of enable/disable modules operations. Here we should pay attention to the low power mode configuration again. Because that s what we will do in each low power entry. Table 7. Low Power Configuration System Idle Low Power Idle Suspend SNVS CCM LPM Mode WAIT WAIT STOP - ARM Core (PDM7) WFI WFI Power Down OFF L1 Cache ON ON Power Down OFF FlexRAM (PDRET) ON ON ON OFF FlexRAM (PDRAM0) ON ON Power Down OFF FlexRAM (PDRAM1) ON/OFF ON/OFF Power Down OFF VDD_SOC_IN Voltage 1.15V 0.95V 0.925V OFF 528 PLL ON Power Down Power Down OFF Other PLL Power Down Power Down Power Down OFF 24MHz XTAL OSC ON OFF OFF OFF 24MHz RC OSC OFF ON OFF OFF NXP Semiconductors 9

10 LDO2P5 ON OFF OFF OFF LDO1P1 ON OFF OFF OFF WEAK2P5 OFF ON OFF OFF WEAK1P1 OFF ON OFF OFF Bandgap ON OFF OFF OFF Low Power Bandgap ON ON ON OFF AHB clock 33MHz 12MHz OFF OFF IPG clock 33MHz 12MHz OFF OFF PER clock 33MHz 12MHz OFF OFF Module Clocks ON as needed ON as needed OFF OFF RTC32K ON ON ON ON 5.2. Low Power Mode Enter & Exit Sequence On i.mxrt, we can enter each low power mode and exit to run. System Idle SNVS RUN Low Power Idle Suspend Figure 1. Low Power Mode Enter & Exit Sequence 10 NXP Semiconductors

11 Enter System Idle mode Low Power Application Design System Idle mode is a simple mode that we don t need to change many modules. Most modules default settings can be kept How to enter To enter system idle mode, we need to change core frequency and disable unused PLLs. The voltage need to be changed accordingly. Before executing WFI instruction, used modules DOZE bits need to be set. Set Clock Mode Change CLPCR[LPM] to WAIT Change PLL settings Change arm PLL to 132MHz Disable unused PLLs Refer to and Adjust voltage Adjust core voltage to 1.15V Execute WFI instruction Set peripheral to enter DOZE mode, IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12. Refer to Execute WFI How to exit The exit of System Idle mode is also simple. We need to adjust the core frequency and enable PLLs first and then increase the core voltage if needed. NXP Semiconductors 11

12 Resume peripheral back Clear DOZE bits in IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12. Refer to Restore PLL settings Restore arm PLL to 600MHz Enable needed PLLs. Refer to and Adjust voltage Adjust core voltage to 1.25V (for 600MHz frequency) Set Clock Mode Change CLPCR[LPM] to RUN Enter Low Power Idle mode How to enter To enter Low Power Idle mode, we need to do a dozen of things. Please refer to the diagram below. 12 NXP Semiconductors

13 Set Clock Mode Change CLPCR[LPM] to WAIT Switch DCDC Switch DCDC to use internal OSC Power down USBPHY Power down USBPHY Change PLL settings Change arm PLL to use 24MHz OSC Disable all other PLLs Refer to and Enable weak LDO Enable weak 2P5 and 1P1 LDO. Turn off regular 2P5 and 1P1 LDO. Refer to Switch to RC- OSC Switch to24mhz RC-OSC Turn off external 24Mhz OSC Adjust voltage Adjust core voltage to 0.95V Disable regular bandgap Disable regular bandgap and enable low powe r bandgap Refer to Execute WFI instruction Set peripheral to enter DOZE mode, refer to Execute WFI NXP Semiconductors 13

14 How to exit To exit Low Power Idle mode, please refer to the diagram below. Clear DOZE bits Clear DOZE bits in IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12. Refer to Adjust voltage Adjust core voltage back to 1.25V (for 600MHz) Switch DCDC Switch DCDC to use external OSC Switch to external OSC Init 24MHz external OSC Switch to external OSC Change PLL settings Change arm PLL to use 24MHz OSC Disable all other PLLs Refer to and Enable regular bandgap Turn on regular bandgap and disable low power bandgap. Refer to Enable refular LDO Enable regular 2P5 and 1P1 LDO. Turn off weak 2P5 and 1P1 LDO. Refer to Set Clock Mode Change CLPCR[LPM] to RUN Enter Suspend mode In suspend mode, as when set CLPCR[LPM] to STOP, the system will help us to power down PLLs, we don t need to adjust frequency. 14 NXP Semiconductors

15 How to enter Set Clock Mode Change CLPCR[LPM] to STOP Set resume entry If use ROM code to handle the resume, set SRC->GPR[0] and SRC- >GPR[1] If boot from APP, set IOMUXC_GPR->GPR16 to vector table. Turn off FlexRAM Turn off FlexRAM per APP request. Refer to Power down USBPHY Power down USBPHY Adjust voltage Adjust core voltage to 0.95V Switch DCDC Switch DCDC to use internal OSC Send power down CPU request Send power down CPU request Execute WFI instruction Set peripheral to enter DOZE mode, refer to Execute WFI NXP Semiconductors 15

16 How to exit Reset Wakeup CPU reset wakeup Turn on FlexRAM Turn on FlexRAM per APP request. Refer to Clear resume entry If use ROM code to handle the resume, set SRC->GPR[0] and SRC- >GPR[1] to 0 If boot from APP, set IOMUXC_GPR->GPR16 to rom code entry. Switch DCDC Switch DCDC to use external OSC Clear CPU Power Down request bit Clear CPU power down request bit Change CLPCR[LPM] to RUN Set Clock Mode 16 NXP Semiconductors

17 SNVS mode How to enter To enter SNVS mode, we need to set SNVS_LPCR[TOP] to 1. Example code: SNVS->LPCR = SNVS_LPCR_TOP_MASK; while (1) /* Shutdown */ { } How to exit Long pressing ON/OFF button (SW2 on EVK board) Low Power Design Point How to change core frequency When need to change core, we also need to consider adjusting the voltage. There s a rule in changing core frequency and voltage. When increasing core frequency, voltage first, frequency second. When decreasing core frequency, frequency first, voltage second How to change PLL frequency The sequence in changing PLL frequency is listed below: Clear POWERDOWN bit. Set ENABLE and BYPASS bits to use bypass clock. Set PLL clock divider. Clear PLL BYPASS bit. Wait for CCM operation finishes by testing CCM_CDHIPR register Example code: /* Wait CCM operation finishes */ while (CCM->CDHIPR!= 0) NXP Semiconductors 17

18 { } NOTE Remember that each time when we need to change PLL frequency, we should use BYPASS clock first, then change PLL frequency and at last, switch PLL back How to enable Tickless Low Power feature in FreeRTOS The FreeRTOS tickless idle mode stops the periodic tick interrupt during idle periods (periods when there are no application tasks that are able to execute), then makes a correcting adjustment to the RTOS tick count value when the tick interrupt is restarted. Stopping the tick interrupt allows the microcontroller to remain in a deep power saving state until an interrupt occurs. NOTE MCU-SDK have already provided fsl_tickless_systick.c and fsl_tickless_gpt.c to implement tickles low power feature. User need to define configuse_tickless_idle in FreeRTOSConfig.h Choose a FreeRTOS Tick timer Normally, we ll use system tick module as tick timer in FreeRTOS. On i.mxrt, the system tick module in Cortex-M7 core can support two timer sources, core clock and 100KHz clock, which is derived from 24M oscillator and divided to 100KHz. As in FreeRTOS, the time consumed in tickless stop will be compensated. The time consumed in tickles stop should not exceed maximum time duration (or FreeRTOS won t be able to know how much time to compensate). The code to calculate maximum duration counts is in function vportsetuptimerinterrupt() in tickless code. ultimercountsforonetick = ( configsystick_clock_hz / configtick_rate_hz ); xmaximumpossiblesuppressedticks = portmax_32_bit_number / ultimercountsforonetick; For system tick module, portmax_32_bit_number is 0x00FFFFFF and normally configtick_rate_hz is set to 1000, meaning that each time tick duration is 1ms. So, in case we choose core clock 600MHz as clock source for system tick module, ultimercountsforonetick will be and xmaximumpossiblesuppressedticks will be , which is also ms ms is too short for a tickless duration. It means when in tickles stop, the system need to wake up every ms to compensate the time. 18 NXP Semiconductors

19 So, when we consider using tickles low power in a FreeRTOS application, we d better not use core clock as systick clock source, but use 100KHz clock source. In this case, ultimercountsforonetick will be 100 and xmaximumpossiblesuppressedticks will be ms, which is about 168s. It s an acceptable duration here. To use 100KHz clock, we just need to define configsystick_clock_hz in FreeRTOSConfig.h. #define configsystick_clock_hz (10000U) Choose a Tickless timer As in tickless mode, FreeRTOS also need to compensate the consumed time, we need to use a timer with maximum time ticks that FreeRTOS can hold. Systick is the first choice for this timer. But in i.mx RT, systick interrupt is not imported in GPC module. So systick interrupt can t wakeup the system, but only the arm core. We need to select another timer as tickless timer. The requirement for a tickless timer will be: Timer. Imported in GPC and can wake up the system. Work in System Idle, Low Power Idle and Suspend mode, even when core and all PLLs are power down. So, we use GPT as tickles timer. GPT module can use 32K RTC (by setting GPT_CR[CLKSRC] = 4) as clock source which can work in System Idle, Low Power Idle and Suspend mode Hook functions before and after WFI instruction FreeRTOS Tickless Idle mode provide two methods. vportsuppressticksandsleep function. In Tickless mode, the system will call vportsuppressticksandsleep function in idle task and pass the expect sleep time in microsecond as parameter. User can implement a customized vportsuppressticksandsleep and Idle task will call this function periodically. Advantage: Can handle WFI instruction as user required. For example, as in suspend mode, the core is power down and thus, the wakeup is indeed a core reset. But as context can be saved, user can run code from WFI after reset. User need to setup a restore point to restore when reset. In this case, it is easier for user to handle the WFI instruction in customer function. Disadvantage: User function need to calculate the tickles period and call vtasksteptick to compensate the consumed time. Note: User can take the vportsuppressticksandsleep function in fsl_tickless_systick.c and fsl_tickless_gpt.c as a reference to compensate the time. NXP Semiconductors 19

20 Two hook functions to call before and after WFI instruction, configpre_sleep_processing and configpost_sleep_processing. If user want to reuse vportsuppressticksandsleep in fsl_tickless_systick.c and fsl_tickless_gpt.c, configpre_sleep_processing and configpost_sleep_processing can be implemented to change and restore modules for a lower power consumption. Advantage: Don t need to care about time compensation. vportsuppressticksandsleep function in fsl_tickless_systick.c and fsl_tickless_gpt.c will do it for you. Disadvantage: Not very flexible. User can t proceed WFI instruction in own function. In Power Mode Switch example, we use the second method to reuse vportsuppressticksandsleep Doze and IPG STOP signal On i.mx RT, before entering low power mode, in order to reduce power, we need to set Doze and Stop bits to ask each module to enter Doze of Stop status. In the example code, we ll enable all supported peripherals DOZE bit, but in an application, the developer should know what modules are needed and enable corresponding modules DOZE bits Doze mode For each module in doze mode, the AHB clock and serial clock domain will be gated off internally, but IPS Bus clock is not gated off. This mode is entered by setting corresponding doze bits in IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12, and exited by clear corresponding bits in IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12. Example code: NOTE The Doze mode works in all low power modes. So, the Doze bits should be set before entering any low power mode. Before enter low power mode: After wakeup: IOMUXC_GPR->GPR8 = 0xaaaaaaaa; IOMUXC_GPR->GPR12 = 0x a; IOMUXC_GPR->GPR8 = 0x ; IOMUXC_GPR->GPR12 = 0x ; 20 NXP Semiconductors

21 Stop mode When system requires a peripheral device to enter stop mode, it will wait for all transactions to complete and return ACK handshake to system. After ACK handshake returned, the system can gate the AHB Bus clock, IPS Bus clock and serial clock in system level. There is no clock gating action internally. The mode is entered by setting corresponding doze and stop bits in IOMUXC_GPR_GPR8 and IOMUXC_GPR_GPR12, and system should wait for the accordingly bits in IOMUXC_GPR_GPR4 and IOMUXC_GPR_GPR7 to be set. The stop mode works only in Suspend mode. So, the Stop and Doze bits should be set before entering Suspend mode. In the example code, we ll enable all supported peripherals STOP and DOZE bit, but in an customer application, the developer should be aware of what modules are needed and enable corresponding modules STOP and DOZE bits. Example code: Before enter suspend mode: IOMUXC_GPR->GPR4 = 0x ; While ((IOMUXC_GPR->GPR4 & 0x )!= 0x ){}; IOMUXC_GPR->GPR4 = 0x000036ff; IOMUXC_GPR->GPR7 = 0x0000ffff; IOMUXC_GPR->GPR8 = 0xfffcffff; IOMUXC_GPR->GPR12 = 0x a; while ((IOMUXC_GPR->GPR4 & 0x36f90000)!= 0x36f90000) {}; while ((IOMUXC_GPR->GPR7 & 0xffff0000)!= 0xffff0000) {}; After wakeup: IOMUXC_GPR->GPR4 = 0x ; IOMUXC_GPR->GPR7 = 0x ; IOMUXC_GPR->GPR8 = 0x ; IOMUXC_GPR->GPR12 = 0x ; Looking at the codes above, we can see that we send STOP request to EDMA and ENET first. IOMUXC_GPR->GPR4 = 0x ; While ((IOMUXC_GPR->GPR4 & 0x )!= 0x ){}; The reason is that EDMA and ENET are two modules that can act as a master on BUS and initiate transfer. As our code is on SPI Flash, we will not send stop request to SPI Flash. NXP Semiconductors 21

22 For example, CAUTION Please be careful that before entering Suspend mode, if corresponding module s STOP request is asserted, the system should wait for the acknowledge bit to be set. Or, the system may fail to enter the Suspend mode. If the code is in SDRAM and user need to enter Suspend mode. SDRAM need to STOP signal to enter self-refresh mode. Here if we send STOP request to SDRAM and polling for the acknowledge bit to be asserted, we might never get the bit asserted. Because we re running code on SDRAM and the transaction on SDRAM can t STOP. In this way, we should put the code and data to OCRAM or SPI Flash. NOTE: Depending on whether clock gate and IP module s enable bit is set, each IP module may have a different behavior when we send stop signal to it. Some modules can acknowledge to stop signal even clock gate is OFF, for example, PIT. Some modules can t acknowledge to stop signal when clock gate is OFF. But when clock gate is ON, it can acknowledge to stop signal, e.g. EDMA. Some modules can acknowledge to stop signal when clock gate is ON and the module s enable bit is ON. Currently, as we know, only CAN is of this type. So, we ask user to know used modules in their application and set correspondingly bits How to enable weak analog LDO There re two Analog LDO on i.mx RT, regular LDO and low power weak LDO. In Low Power Idle mode, we ll use weak LDO to save power. Enable Weak Analog LDO /* Enable regular 2P5 and wait for stable */ PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_LINREG_MASK; while ((PMU->REG_2P5 & PMU_REG_2P5_OK_VDD2P5_MASK) == 0) { } /* Turn off weak 2P5 */ PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; 22 NXP Semiconductors

23 /* Enable regular 1P1 and wait for stable */ PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_LINREG_MASK; while ((PMU->REG_1P1 & PMU_REG_1P1_OK_VDD1P1_MASK) == 0) { } /* Turn off weak 1P1 */ PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; Low Power Application Design Disable Weak Analog LDO /* Enable weak 2P5 and turn off regular 2P5 */ PMU->REG_2P5 = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; PMU->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK; /* Enable weak 1P1 and turn off regular 1P1 */ PMU->REG_1P1 = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; PMU->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK; How to disable OCRAM power This SoC has 512 KB of on-chip RAM which is shared by I-TCM, D-TCM and general purpose On Chip RAM (OCRAM). The FlexRAM manages the big on-chip RAM array. The OCRAM have 16 RAM banks, which are divided into Bank0, FlexRAM0 (bank 1-7) and FlexRAM1 (bank 8-16). Description of OCRAM banks is listed below: Table 8. Description of OCRAM banks Bank 0 Bank 1-7 Bank 8-16 Alias Name Bank0 FlexRAM0 FlexRAM1 Power Domain SNVS PDRAM0 PDRAM1 Power Gate Bit N/A GPC_CNTR[PDRAM0_PGE] PGC_MEGA_CTRL[PCR] Power Gate Default Value N/A 1 (Will power down in low power mode) 0 (Won t power down) LPM MODE ON/OFF Status ON Controllable Controllable NXP Semiconductors 23

24 Power down moment In SNVS mode, bank0 is power d own. GPC_CNTR[PDRAM0_PG E] is set and Bank 1 7 will be off when core executes W FI instruction PGC_MEGA_CTRL[PCR] is set and Bank 8 16 will be off immediately NOTE Please pay attention to that when the power gate bit is set, FlexRAM0 won t be OFF immediately, unless core execute WFI instruction. But FlexRAM1 will be OFF immediately. 24 NXP Semiconductors

25 Code examples: Power Down FlexRAM0 and FlexRAM1 /* Turn off FlexRAM1 */ PGC->MEGA_CTRL = PGC_MEGA_CTRL_PCR_MASK; /* Turn off FlexRAM0*/ GPC->CNTR = GPC_CNTR_PDRAM0_PGE_MASK; Power on FlexRAM0 and FlexRAM1 /* Turn on FlexRAM1 */ PGC->MEGA_CTRL &= ~PGC_MEGA_CTRL_PCR_MASK; /* Turn on FlexRAM0*/ GPC->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; Bandgap switch In i.mxrt, there re two bandgap, regular bandgap and low power bandgap. In low power application, we need to switch bandgap to low power bandgap before entering low power wait or stop state. Code example: NOTE In suspend mode, as we ll set STOP mode in CLPCR, which will help to switch bandgap to low power bandgap automatically in low power stop. We don't need to switch bandgap in Suspend mode. Switch bandgap to low power bandgap: /* Switch bandgap */ PMU->MISC0_SET = 0x ; XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; PMU->MISC0_SET Switch bandgap back to regular bandgap: /* Restore bandgap */ = CCM_ANALOG_MISC0_REFTOP_PWD_MASK; /* Turn on regular bandgap and wait for stable */ CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_REFTOP_PWD_MASK; while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) == 0) { } /* Low power band gap disable */ NXP Semiconductors 25

26 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; PMU->MISC0_CLR = 0x ; Enable DCM mode of DCDC DCDC module provides a Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM). In run mode, it can operate on the continuous conduction mode or discontinuous conduction mode, depending on the level of the load current. And the discontinuous conduction mode need be enabled by the register configuration. NOTE Normally, we ll use DCDC in RUN mode and DCM mode in low power mode. (User can also use DCM mode in RUN mode if the current in RUN is low). DCM mode can reduce current of DCDC_IN, but DCDC_OUT current will not change. The DCM mode can reduce about 2mA current (3mA to 1mA) in low power mode on DCDC_IN. The DCM mode should be set before entering low power mode. Here s the code example: static void LPM_DCDC_Set_DCM_Mode(void) { /* DCDC Power saving LDO */ DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; DCDC->REG0 &= ~(DCDC_REG0_PWD_CMP_OFFSET_MASK DCDC_REG0_PWD_CMP_BATT_DET_MASK DCDC_REG0_OVERCUR_TRIG_ADJ_MASK DCDC_REG0_PWD_ZCD_MASK); DCDC->REG0 = DCDC_REG0_PWD_CMP_BATT_DET_MASK; /* DCDC Power saving enable DCM mode */ DCDC->REG2 = 0x ; /* Disable Step mode, speed up transition */ DCDC_LockTargetVoltage(DCDC); } Don t forget to restore to CCM mode when waked up. User can refer to DCDC chapter in RM for more details on DCM mode. 26 NXP Semiconductors

27 Enable and disable RBC bit Low Power Application Design In Suspend mode, the RBC bit need to set before executing WFI instruction and cleared after wakeup. The RBC bit is in CCM_CCR register. VSTBY bit in CCM_CLPCR will change voltage to standby voltage. This bit need to be set in all low power modes. Enabling RBC_EN and VSTBY will ask analog to enter low power in STOP. Two points need to be noted in enabling and disabling RBC_EN bit. GPC interrupts need to be masked before setting the bit. A delay (3us) is needed after setting the bit. Code example: Enable RBC_EN: /* Mask all GPC interrupts before enabling the RBC counters to */ avoid the counter starting too early if an interupt is already pending. for (i = 0; i < LPM_GPC_IMR_NUM; i++) { } gpcimr[i] = GPC->IMR[i]; GPC->IMR[i] = 0xFFFFFFFFU; /* Enable the RBC bypass counter here to hold off the interrupts. RBC counter * = 32 (1ms). Minimum RBC delay should be 400us. */ CCM->CCR = (CCM_CCR_RBC_EN_MASK CCM_CCR_COSC_EN_MASK CCM_CCR_OSCNT(0xAF)); /* Recover all the GPC interrupts. */ for (i = 0; i < LPM_GPC_IMR_NUM; i++) { GPC->IMR[i] = gpcimr[i]; } NXP Semiconductors 27

28 /* Now delay for a short while (3usec) ARM is at 528MHz at this point * so a short loop should be enough. This delay is required to ensure that * the RBC counter can start counting in case an interrupt is already pending * or in case an interrupt arrives just as ARM is about to assert DSM_request. */ for (i = 0; i < 22 * 24; i++) { } NOP(); Disable RBC_EN: /* Mask all GPC interrupts before disabling the RBC counters */ for (i = 0; i < LPM_GPC_IMR_NUM; i++) { } gpcimr[i] = GPC->IMR[i]; GPC->IMR[i] = 0xFFFFFFFFU; /* Disable the RBC bypass counter */ CCM->CCR &= ~CCM_CCR_RBC_EN_MASK; CCM->CCR &= ~CCM_CCR_REG_BYPASS_COUNT_MASK; /* Now delay for 2 CKIL cycles (61usec). ARM is at 528MHz at this point * so a short loop should be enough. */ for (i = 0; i < 528 * 22; i++) { } NOP(); 28 NXP Semiconductors

29 /* Recover all the GPC interrupts. */ for (i = 0; i < LPM_GPC_IMR_NUM; i++) { GPC->IMR[i] = gpcimr[i]; } Workaround for ERR Errata ERR describes about a case that SoC may fail to enter a low power mode. ERR007265: CCM: When improper low-power sequence is used, the SoC enters low power mode before the ARM core executes WFI. Software workaround: 1) Software should trigger GPR_IRQ to be always pending by setting IOMUX_GPR1_GINT. 2) Software should then unmask GPR_IRQ in GPC before setting CCM Low-Power mode. 3) Software should mask GPR_IRQ right after CCM Low-Power mode is set (set bits 0-1 of CCM_CLPCR). Please search ERR as keyword in example project for code examples How to run after WFI instruction in suspend reset Introduction Suspend mode is a low power mode with least power. But as the core will power down, the wakeup is a reset wakeup. In System Idle and Low Power Idle, when wakeup, the code can continue run after WFI instruction which is convenient but can t get least power consumption. As in Suspend mode, we can get least power consumption, we want the code to continue run after WFI instruction in suspend reset. We need to do some hack for this purpose Why it can run after WFI instruction in suspend reset When SOC enters suspend mode, core is power down, but SDRAM and all other peripherals will retain. When core reset, only core registers will reset, that is, NVIC, SCB, Systick and FPU, etc. About OCRAM power management, please refer to Chapter to control it. SDRAM provide a self-refresh mechanism that in suspend mode, when system enter STOP mode, SDRAM will enter self-refresh mode automatically and data on SDRAM won t lost. NXP Semiconductors 29

30 NOTE Make sure your data can be retained when core is power down Sequence description Save Restore Point Save R4-R12, MSP, PSP, LR, PRIMASK, CONTROL register Save NVIC registers Save SCB registers Execute WFI CPU execute WFI instruction Reset & Restore from Restore Point Reset Restore the system to run after WFI Hook definition in FreeRTOS Tickless mode In the case that we reuse vportsuppressticksandsleep function in fsl_tickless_systick.c or fsl_tickless_gpt.c, we need to implement configpre_sleep_processing and configpost_sleep_processing. Normally, configpre_sleep_processing and configpost_sleep_processing can be defined as functions or macros. But when we want code to run after WFI instruction in suspend reset, we d better define configpre_sleep_processing and configpost_sleep_processing as macros. The reason is as below: 1. The WFI instruction executed in vportsuppressticksandsleep function is not handled by user code. 2. The restore point will be setup in configpre_sleep_processing. 3. When restore, we need to restore the restore point and jump over the WFI instruction. 4. In a function call, the program will jump to an address that will not be located before WFI. So, we can t setup the restore point there. 30 NXP Semiconductors

31 See the diagram below: Setup restore point in configpre_sleep_processing. When restore, jump over WFI. WFI instruction configpost_sleep_processing Figure 2. Suspend Reset Procedure Setup a restore point The restore point is a snapshot of core status that will be restored after reset. What we will do here is to save core registers that need to be saved. General purpose registers, R4-R12 General purpose registers for data operations. Normally, R0-R3 are used to store parameters in a function call, R4-12 stores data that need to be restored in a function call. So here, we will store R4-R12. MSP, PSP MSP, PSP, LR are all very important in this stage. MSP (Main SP) and PSP (Process SP) are banked version of SP. In the system, user can only see one SP register at one time. NXP Semiconductors 31

32 In Thread mode, SPSEL of the CONTROL register indicates the Stack Pointer to use: Table 9. SPSEL bit description CONTROL[SPSEL] Description LR 0 Main Stack Pointer (MSP). This is the reset value. 1 Process Stack Pointer (PSP). In task context of FreeRTOS, PSP will be used. And on reset, the processor will use MSP with the value from address 0x In an application, PSP indicates the task stack pointer and the task stack contains important data of a task. MSP indicates the main stack pointer. Main stack is used in system reset and interrupt context. We need to save both MSP and PSP and in restore operation, we ll restore both MSP and PSP. In a function call, LR stores the return address. In context save function, LR indicates the program address of the point. We need to use LR to set PC register value. Special registers, PRIMASK, CONTROL PRIMASK and CONTROL are used in FreeRTOS. CONTROL register contains information about current stack point. We need to save them. NVIC registers NVIC registers stores interrupt settings. We need to store ISER, STIR and IP. SCB registers The System Control Block (SCB) provides system implementation information, and system control. We will store ACTLR, SCR, CCR, SHCSR, SHPR. Please pay attention to CCR register which contains settings of L1 cache. When CCR register need to restored, DSB and ISB function need to be called, or the system may abnormal. Code example: SCB->CCR = s_corecontext.ccr; /* Cache MUST be invalidated after setting CCR, OR, data access could be failed. */ DSB(); ISB(); 32 NXP Semiconductors

33 Save the context As we need to access SP register, it s better to implement the function in assembly language. Also, as we need to save SP register and any stack operation will change the value of SP, we d better not to touch stack in this function. But as a function call, we also need to restore R4-R12 registers and set LR register s value to PC at the end of the function. Here we describe the implementation method in power mode switch example. 1. Define two array to store general purpose registers and special registers. /* R4, R5, R6, R7, R8, R9, R10, R11, R12, LR */ #define CORE_SAVE_COMMON_REGS_NUM (10) /* PRIMEMASK, CONTROL, MSP, PSP */ #define CORE_SAVE_SPECIAL_REGS_NUM (4) uint32_t s_common_regs_context_buf[core_save_common_regs_num] = { 0 }; uint32_t s_special_regs_context_buf[core_save_special_regs_num] = { 0 }; uint32_t *gpcomregscontextstacktop = s_common_regs_context_buf + CORE_SAVE_COMMON_REGS_NUM; uint32_t *gpcomregscontextstackbottom = s_common_regs_context_buf; uint32_t *gpspecregscontextstacktop = s_special_regs_context_buf + CORE_SAVE_SPECIAL_REGS_NUM; uint32_t *gpspecregscontextstackbottom = s_special_regs_context_buf; 2. Use STMDB instruction to save registers to arrays. LDR LDR STMDB R1, =gpcomregscontextstacktop R0, [R1] R0!, {R4-R12, LR} LDR LDR R1, =gpspecregscontextstacktop R0, [R1] MRS R2, MSP ; MSP => R2 MRS R3, PSP ; PSP => R3 MRS R4, PRIMASK ; PRIMASK => R4 MRS R5, CONTROL ; CONTROL => R5 STMDB R0!, {R2-R5} NXP Semiconductors 33

34 3. Call LPM_IrqStateSave and LPM_CoreStateSave to save NVIC and SCB registers to other data structure. BL BL LPM_IrqStateSave LPM_CoreStateSave 4. Don t forget to restore R4-R12 and set LR value to PC. LDR LDR LDMIA MOV R1, =gpcomregscontextstackbottom R0, [R1] R0!, {R4-R12, LR} PC, LR Where to do the context restores On i.mx RT, there re two methods to do the context restore. We can do the restore either in ROM Code or in Reset procedure. User can set IOMUXC_GPR_GPR16[CM7_INIT_VTOR] to select to boot in rom code or application entry directly. By default, the value of IOMUXC_GPR_GPR16[CM7_INIT_VTOR] is rom code start address. Here re the descriptions of these two methods. Wakeup in ROM Code In this way, we don't need to modify IOMUXC_GPR_GPR16[CM7_INIT_VTOR], but need to set SRC_GPR1 and SRC_GPR2. Code example: /* Set resume entry */ //SRC->GPR[0] = (uint32_t)lpm_resumedsm; //SRC->GPR[1] = context; SRC_GPR1 holds the function entry pointer and SRC_GPR2 holds the argument of the entry function. The ROM code will help to detect whether it is a suspend reset (via PGC->CPU_SR[PSR]) and run the entry function. NOTE There s a big limitation in this way that the function entry pointer must in the OCRAM Bank0 area (0x x20207fff) and thus this way is not recommended. Wakeup in application entry In this way, we ll change IOMUXC_GPR_GPR16[CM7_INIT_VTOR] to wake up in application entry. 34 NXP Semiconductors

35 Code Example: /* Set resume entry */ IOMUXC_GPR->GPR16 = (uint32_t)((uint32_t) VECTOR_TABLE 3); We recommend to wake up in application entry. In the recommended way, we ll detect suspend reset and call the restore function in SystemInit() function. Note: We can t call the restore function in Main. In the startup_mimxrt1052.s, we can see the Reset_Handler function. Reset_Handler CPSID I ; Mask interrupts LDR LDR STR LDR MSR LDR BLX R0, =0xE000ED08 R1, = vector_table R1, [R0] R2, [R1] MSP, R2 R0, =SystemInit R0 CPSIE I ; Unmask interrupts LDR BX R0, = iar_program_start R0 We can see the SystemInit() function is called before iar_program_start. In iar_program_start, all r/w memory spaces will be reset and the context will be destroyed. Thus, if we call restore function in main function, the restore will fail. So we d better detect the suspend reset and do restore in SystemInit() function Restore the context In this stage, we ll reverse the operation that we do in setup the point. Code example: LPM_LoadContextPoint BL LPM_CoreStateRestore NXP Semiconductors 35

36 BL LPM_IrqStateRestore LDR LDR R1, =gpspecregscontextstackbottom R0, [R1] LDMIA R0!, {R2-R5} ; Pop registers MSP, PSP, PRIMASK, CONTROL MSR MSR MSR MSR MSP, R2 PSP, R3 PRIMASK, R4 CONTROL, R5 LDR LDR R1, =gpcomregscontextstackbottom R0, [R1] LDMIA R0!, {R4-R12, LR} ; Pop registers R4-R12, LR MOV R0, LR ADD LR, LR, #12 ; Add a constant to run after WFI MOV PC, LR Here we ll load register values from arrays using LDMIA instruction. NOTE Please pay attention to the immediate operand #12. This constant is an offset which is added to LR and will make PC to run to the program address after WFI instruction. This value might be different in different environment. Please calculate the constant in different applications. The constant can be known in disassembly window in IAR SDRAM Data Storage Suggestion In power mode switch example, we put code on SPI Flash and Data on FlexRAM0. But in most applications, user may want to use SDRAM to store data. SDRAM can enter self-refresh mode automatically in Suspend and data won t be lost. CAUTION Before entering Suspend mode, we need to send STOP request to SDRAM to ask SDRAM to enter self-refresh mode. Here we should avoid accessing SDRAM and use variable in OCRAM. 36 NXP Semiconductors

37 6. Conclusion This document mainly describes how to measure power consumption on i.mx RT and give a lot of design details in designing a low power application. 7. Revision history Reference Revision number Date Substantive changes 0 11/2017 Initial release 8. Reference 1. i.mx RT 1050 Reference Manual. 2. ARM Cortex M7 Reference Manual.. NXP Semiconductors 37

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