CEC 450 Real-Time Systems

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1 CEC 450 Real-Time Systems Lecture 1 Introduction Part 2 August 27, 2018 Sam Siewert

2 Questions on Final Projects? Examples here - Creative Projects - Duck Hunter, Robotic arms, Tilt/Pan trackers, etc. Standard Project - 1 Hz, 10 Hz Clock Image Capture and Processing Verifies well - o/appendix6_1hz_samples.zip Has glitch - o/clock.zip Choose Standard or Creative in Ex #5 and start Complete first try, testing, and report in Ex #5 Debug during last week of class Demonstrate for Final Exam Sam Siewert 2

3 Questions on Ex #1? Follow Ex #1 submission guidelines - I may build and run, but report so I don t need to, and comment so you can walk-through confidently Turn in on Canvas Next Week Friday For coding standards, pick one and follow - RTES are most often C code and ASM (Lewis book). C is old, but still favored for OS kernel and ES firmware - standards for C: Ganssle or similar CMU, GNU or NASA guides. If you must code in C++ (for good reason like OpenCV or ROS, or you work at Apple on OS-X kernel and drivers, etc.) then use Google C++ or Stroustrup. You can complete this course using nothing but simple C Focus is on invariant LCM schedules - this will take some time to master! Theory, practice (with services as threads or tasks) and careful design are required for ultimate success. This is practice - do your best and I will help you improve - points on practice exercises are based on: Completeness Thoughtfulness (be honest, ask questions if you get stuck, what works, what does not) Good documentation for repeatability - like you would submit to QA Makefile, report as doc or PDF (in format of how you tested), and zip up code Sam Siewert 3

4 NUC/Jetson Linux - Go To Lab, Verify Login Option #1 Use King 122 NUC / Jetson Lab Learn Host and Embedded Linux Getting Started Jetson - Used for Self-Driving Cars NUC - Way Cool! ssh -X ubuntu@ [from Host 121] Optoin #2 - Raspberry Pi 3b+ $80 kit You own it, can be used for entire course Dev Option #3 Virtual-Box Linux with Ubuntu LTS Use Windows or Mac PC Learn Linux, it s Easy Real-time Testing must be done on native Linux Sam Siewert 4

168.122.112] B72-122-NUC9 [192.168.122.191] => B72-TK1-192 [192.

5 Questions on Lab Resources? B NUC1 [ ] => B72-TK1-112 [ ] B NUC9 [ ] => B72-TK1-192 [ ] #5 & #6 Left Side - #1 to #4 Left Side - #7 to #9 Sam Siewert 5

Shared P: Windows drive and access from NUC Getting Files from NUC to Jetson (Testing) Use Connect to Server from

6 Downloading and Copying Files Getting Files to NUC Option #1 - Bring files to Lab on USB Memory Stick, Plug into NUC (or Jetson) Option #2 - Download files from NUC Web browser (right click, Save-Link-as) Option #3 - Put files on a Shared P: Windows drive and access from NUC Getting Files from NUC to Jetson (Testing) Use Connect to Server from Places and use SSH to Jetson IP, using ubuntu, ubuntu Drag and drop files from NUC folder to Jetson folder Sam Siewert 6

Now Drag and Drop Files on NUC Desktop Transfer

native on Jetson (like PRClab) Possible to

7 Now Drag and Drop Files on NUC Desktop Transfer files to/from NUC Take code with you on memory stick or copy to P: drive before you leave (backed up) Remove test files from Jetson Compile code native on Jetson (like PRClab) Possible to crosscompile, cross-debug if you want with NVIDIA tools Sam Siewert 7

RT Terminology Firmware Embedded Systems Real-Time Theory and Practice See - http://mercury.pr.erau.

8 RT Terminology Firmware Embedded Systems Real-Time Theory and Practice See - Lectures/Terminology.pdf Also in Book (Notes) in Appendix For all S: C i, T i, D i, Compute U, m=number of S m U = ( Ci / Ti) m(2 1) Sam Siewert i= m

9 Typical RTOS Scheduling Policies Fixed Priority Preemptive Tasks State Based on Resources Required Needs CPU Only = Ready Non-CPU Resource Required = Pending Task Context Switch on System Call or Interrupt Dispatch from Ready Queue Dispatch with Rate Monotonic Priority RM LUB Feasibility Feasibility Tests Scheduling Point Algorithm Completion Test Algorithm Over LCM of Periods pending Dispatch Wait on Resource (semtake(), pause()) Note: Different from Chapter 7 In VxWorks Kernel Programmer s Guide executing ready Interference (preemption) Suspend (unhandled exception, tasksuspend()) Yield (taskdelay()) delayed Dynamic Priority Premptive Earliest Deadline First Least Laxity First Suspended, +Delayed, +Pending Sam Siewert 9

https://www.mathsisfun.com/numbers/fibonacci-sequence.html CPU Loading = % Feasible Schedule? Safe?

10 POSIX RT Task Example S 1 Computes Fibonacci for 10 milliseconds and quits S 2 Computes Fibonacci for 20 milliseconds and quits C 1 =10, C 2 =20 milliseconds T 1 =D 1 =20 & T 2 =D 2 =50 milliseconds CPU Loading = % Feasible Schedule? Safe? Easy to Emulate? Violates Rate Monotonic Feasibility Test? U m = ( Ci / Ti) i= 1 m(2 1 m 1) Sam Siewert 10

11 What Does Theory Tell Us? Look over LCM of Periods (J Lehoczky, L Sha, Y Ding) If Schedule Feasible over LCM, Feasible for All Time Example 5 T1 2 C1 1 U1 0.5 LCM = 10 T2 5 C2 2 U2 0.4 T3 10 C3 1 U3 0.1 Utot = 1 RM Schedule S1 S2 S3 EDF Schedule S1 S2 S3 TTD S1 2 X 2 X 2 X 2 X 2 X S X X X S LLF Schedule S1 S2 S3 Laxity S1 1 X 1 X 1 X 1 X 1 X S X X X S Sam Siewert 11

12 Questions to Ponder What Does Theory Tell Us? Can We Emulate the Fibonacci Workload Accurately In Linux? In FreeRTOS? With VxWorks - hint, hint - here s a VxWorks solution With an ISR and Interrupts Asserted by a Programmable Interval Timer? Or a timing sequencer that gives semaphores to services? - Example What are Pitfalls? - Linux common mistakes Why Would I want to Do This? Sam Siewert 12

Services Multiple Sensor Input and Actuator Output Interfaces Intermediate

13 Complex Multi-Service Systems Multiple Software Services (Dynamic Admission Reconfigurable) Synchronization Between Services Communication Between Services Multiple Sensor Input and Actuator Output Interfaces Intermediate IO, Shared Memory, Messaging Ph.D. Dissertation, CU Boulder, January 2000 Sam Siewert 13

14 Multi-Service Pipelines framerdy interrupt RT Management Event releases / Service control framerdy Control Plane tbtvid (30 Hz) RGB32 buffer tfrmdisp (10 Hz) grayscale buffer tfrmlnk (2 Hz) frame Remote Display tnet (2 Hz) Data Plane P0 topnav (15 Hz) ttlmlnk (5 Hz) TCP/IP pkts P1 tthrustctl (15 Hz) P2 Bt878 PCI NTSC decoder (30 Hz) tcamctl (3 Hz) Serial A/B ISA ethernet Sam Siewert 14 P3 SW HW

15 Why are RT Embedded Systems a Challenge? Real-Time Services Correct Results on time Deadlines! Multi-service Concurrency Required, for Software, Multi-threaded Multiple interfaces to service in addition to data processing Multi-threaded compared to Main Loop + ISR Executive Supports RT analysis and design (Rate Monotonic) Function/Service Allocation HW Service Off-load Management of CPU, IO, and Memory Resources CPU Resource Modern architecture high throughput, less deterministic pipelines, super-scalar, branch prediction, VM, split-transaction and burst transfer bus interfaces, multi-level caches I/O Interface Resources Sensors / Actuators (Interaction with Real World) Networks (Latency and QoS) Off-load and Memory Devices (e.g. Flash, FPGAs, DSP) Memory Hierarchy Resources Register file, L1/L2 cache, SRAM, dynamic RAM, Flash Sam Siewert 15

16 How to Make RT Embedded Systems Easier! RT Service and CPU Resource Management RT Theory, Practice, and Pitfalls (Theory -> System) RMA and DMA Resource Theory Prediction and Measurement of Performance When to Allocate Services/Functions to HW, FW, or SW Multi-threaded RTOS Systems Design Methods (DFD, SDL, EFSM and MSC methods) RTOS Mechanisms (e.g. message queue, signal, semaphore) Analysis Tools (e.g. Windview) HW/FW Debug Tools (e.g. ICE / JTAG) I/O Device Interfaces and Drivers Abstracted SW-HW Interfaces Interaction with Memory System (MMIO, DMAs, Plug-n-Play) Memory Hierarchy Analysis and Abstraction Multi-level Cache Performance Models Abstracted Non-Volatile Memory Filesystems Sam Siewert 16

17 So Why SW for HRT Systems? ASIC and FPGA State-Machine Solutions Offer Hardware Clocked Deterministic Solutions FPGAs Can be Updated with New Bit-streams (Synthesized HDL to Reconfigurable Logic Elements) Software (Firmware) Remains Simplest for Field Upgrade (Reconfigurable at Run-time) FPGAs Can be Costly Per Unit Cost of Software Engineering vs. Hardware Engineering Sam Siewert 17

CEC 450 Real-Time Systems

CEC 450 Real-Time Systems Lecture 1 - Introduction August 23, 2015 Sam Siewert Dr. Sam Siewert UC Berkeley Philosophy/Physics 1984-85 University of Notre Dame, BS - Aerospace/Mechanical Engineering Johnson