CEC 450 Real-Time Systems

Transcription

1 CEC 450 Real-Time Systems Lecture 3 Real-Time Service Implementation Part 1 September 7, 2018 Sam Siewert

2 More Embedded Systems Summer - Analog, Digital, Firmware, Software Reasons to Consider Catch up over summer Cultural mind expansion High Tech Jobs abroad Fairly affordable Full Stack HW -> SW CEC495 - Zephyr RTOS Beautiful West Coast English and Irish Language Weather nice in summer! Sam Siewert 2

3 Quick Review Last Week Service Utility, Qualitative Utility over Time Week Before RM Policy, Feasibility, Safety Timing Diagrams over LCM Use Cheddar to Check Work - Overview Assignment #1 - My Solution (not ideal, but basically works) - Lab 1 Sequencer Better solution for sequencing (one delay) - Generic Sequencer Sam Siewert 3

4 Theory to RTOS to Linux Compare RM Theory with 10 msec units S 1 =fib10, C 1 =1, T 1 =D 1 =2; S 2 =fib20, C 2 =2, T 2 =D 2 =5 Lab 1 T1 2 C1 1 U1 0.5 LCM = 10 T2 5 C2 2 U2 0.4 Utot = 0.9 RM Schedule S1 S2 FREE VxWorks RTOS equivalent with synthetic workload S 1 S 2 Idle Jetson Linux equivalent with synthetic workload (float msec) Sam Siewert 4

5 3 Approaches to RT Systems Cyclic Exec E.g. Shuttle Flight Software, Network elements, process control, Ada CE RTOS VxWorks, QNX, ThreadX, TI RTOS, FreeRTOS, Zephyr, Nucleus, RTEMS, etc. OS + RT POSIX RT Linux, Solaris, LynxOS, FSM Labs, Concurrent, RTAI, Linux Foundation RT, etc. Custom, Deeply Embedded Systems Embedded Systems, Scalable and Portable RT Services for Scalable Apps and Systems Low over-head, purpose-built Medium overhead, quick to market Highest overhead, mixed RT + SRT + BE Costly to develop License costs Maintenance costs Sam Siewert 5

6 Brief History of Unix, Linux, OS-X vs RTOS TI Intel RAM Zilog Z80 Intel 8051 Wind River C/ASM & CE, Fortran, Ada RTEMS VxWorks OS-less Linux, Zephyr, FreeRTOS Sam Siewert 6

7 RTOS - Proprietary vs Open Source New Projects - Open Source Today Embedded Linux and FreeRTOS are future VxWorks, etc. are Legacy Embedded Systems Next Sam Siewert 7

8 Software is primary job function along with Firmware & System Integration Embedded Systems HW System, PCB, and least-most Chip Design Industrial control and IoT (sensor networks) Consumer electronics and communications Sam Siewert 8

9 Embedded Programming C/C++ ASM Python - prototyping and verification Real-time is most common capability with DSP and Networking Analog signal processing for Sensor AFE (Analog Front End) Sam Siewert 9

10 Real-Time Service Types Types of Services Hard Real-Time (Flight Software, Anti-Lock Braking) Soft Real-Time (Multi-media, Audio, Video, Virtual Reality) Best Effort (E.g. Desktop Applications) Isochronal Hard Real-Time (Digital Feedback Control Systems) Isochronal Soft Real-Time (Continuous Media, Video, Audio) Real-Time Service Types in Terms of Utility Utility Curve Shows Value/Harm of Response Over Time From Release Both Before and After Deadline Relative to Release Full Utility - Service Performs as Required Zero Utility- Service is Not Provided Drop-out Causes No Harm Negative Utility Harm to System and/or User and Significant Loss of Assets Sam Siewert 10

11 Hard Real-Time Service Utility Release Deadline 100% Utility 0% Time After Deadline, Utility is Negative Sam Siewert 11

12 Soft Real-Time Service Utility Release Deadline 100% Utility F(t) 0% Time After Deadline, Utility Diminishes According to Some Function F(t) Sam Siewert 12

13 Best Effort Service Utility Release 100% Utility Deadline Does Not Exist 0% Time Sam Siewert 13

14 Isochronal Hard Real-Time Utility Release Deadline 100% Utility 0% Time Before Deadline, Utility is Negative After Deadline, Utility is Negative Sam Siewert 14

15 Isochronal Soft Real-Time Utility Release Deadline 100% Utility F(t) F(t) 0% Time Before Deadline, Utility is < 100% After Deadline, Utility is < 100% Sam Siewert 15

16 Anytime Utility Curve Release Utility Deadline 100% F(t) 0% Time Before Deadline, Utility is </= 100% After Deadline, Utility is Negative or Zero Sam Siewert 16

17 Outline Real-Time Services The RT Embedded System Resource Space CPU IO Memory Service Release Timeline Intro to Timing diagrams Intro to Traces Safe Real-Time Resource Utilization Bounds High-Level Design Input Interfaces Output Interfaces Services Real-Time Requirements (C i, T i, D i for S i ) Decomposition from Services to Functions and Vice Versa Methodologies Structured Analysis/Design UML SDL Sam Siewert 17

18 View of RT CPU Resources CPU How Fast? - Clock Rate How Efficient? - CPI = Clocks Per Instruction or IPC = Instructions Per Clock Pipeline Stalls Due to Hazards e.g. Read Data Dependency Cache Misses, Write Buffer Stalls, Branch Mispredicts How Complex? C i = Instruction Count on Service Longest Path Ideally C i Deterministic WCET Worst-Case Execution Time Longest, Most Inefficiently Executed Path for Service Not Directly Related to Response Time IO Latency Interference by Higher Priority Services and Interrupts How Often? T i = Service Release Period Sam Siewert 18

19 View of RT IO Resources IO Latency? Arbitration Latency for Shared IO Interfaces e.g. Bus Read Latency Time For Data Transit From Device to CPU Core Register, TCM or L1 Cache Register, Tightly-Coupled-Memory, and L1 Cache Considered Zero Wait-State Single Cycle Access Bus Interface Read Requests and Completions Split Transaction Delay Write Latency Time for Data Transit From CPU Core to Device Posted Writes Prevent CPU Stalls Posted Writes Require Bus Interface Queue Bandwidth? Average Bytes or Words Per Unit Time Says Nothing About Latency Queue Depth? Write Buffer Stalls Read Buffer Most Often Stalled by Need for Data to Process CPU Coupling? DMA Programmed IO Cycle Stealing Sam Siewert 19

20 View of RT Memory Resources Memory Hierarchy From Least to Most Latency Level-1 Cache Single Cycle Access Typically Harvard Architecture Separate Data and Instruction Cache Locked for Use as TCM, Unlocked for Set-Associative or Direct Mapped Cache Level-2 Cache or TCM Few or No Wait-States (e.g. 2 Cycle Access) Typically Unified Locked for Use as TCM, Unlocked to Back L1 MMR Memory Mapped Registers Main Memory SRAM, SDRAM, DDR Processor Bus Interface and Controller Multi-Cycle Access Latency On-Chip Many-Cycle Access Latency Off-Chip MMIO Memory Mapped IO Devices Non-Volatile Memory Processor Bus Interface and Controller Slowest Read/Write Access, Most Often Off-Chip Requires Algorithm for Block Erase Interrupt Upon Completion Poll for Completion Total Capacity for Code, Data, Stack, Heap Allocation of Data, Code, Stack, Heap to Physical Hierarchy Most Frequently Accessed In Lowest Latency Segment Moving Blocks or Cache Lines/Sets Prefetches Sam Siewert 20

21 Conceptual View of RT Resources Memory-Util CPU-Util IO-Util Three-Space View of Utilization Requirements CPU Margin? IO Latency (and Bandwidth) Margin? Memory Capacity (and Latency) Margin? Upper Right Front Corner Low-Margin Origin High-Margin Sam Siewert 21

22 A Service Release and Response C i WCET Input/Output Latency Interference Time Response Time = Time Actuation Time Sensed (From Release to Response) Event Sensed Interrupt Dispatch Preemption Dispatch Completion (IO Queued) Actuation (IO Completion) Interference Time Input-Latency Dispatch-Latency Execution Execution Output-Latency Sam Siewert 22

23 Real-Time Services Theoretical Timing Diagrams Lehoczky, Shah, and Ding Theorem (Timing over Longest T) Look at Timing Over LCM of All Periods Simple for Small Number of Services Necessary and Sufficient Proof of Feasibility Trace Tools for Real Timing Software Trace Tools (WindView), SystemViewer Linux Trace Toolkit C.I. Given: Services S1, S2 with periods T1 and T2 and C1 and C2, Assume T2 > T1 E.g. T1=2, T2=5, C1=1, C2= 1, then if prio(s1) > prio(s2), we can see that the service set is feasible by diagramming. T / T 2 1 C + C T T / T 2 1 C + C T S 1 S 2 T 2 T 1 LCM Sam Siewert 23

24 Safe Resource Utilization Bounds CPU How Much Margin to Guarantee Deadlines Will Be Met for a Set of Services? Accounting for Interference How Well Can CPU Be Scheduled? Sufficient RM LUB Necessary and Sufficient Lehoczky, Shah, Ding Theorem If CPU Was the Only Resource Needed Priority Inversion Efficiency IO Is Bandwidth a Guarantee? What About Latency? Memory Allocation in Hierarchy By Latency Requirements Total Capacity Dynamic Memory Allocation? Queue Depths Producer/Consumer Rates Matched? Sam Siewert 24

25 High-Level Design Input Interfaces HW Design and Characterization Output Interfaces HW Design and Characterization Services What Are They? Real-Time Requirements (C i, T i, D i for S i ) Identification of Services Frequency of Service Requests Execution/Processing Complexity Deadline for Response Decomposition from Services to Functions and Vice Versa System-Level Methodologies Structured Analysis/Design UML SDL Sam Siewert 25

26 Space Transportation System Shuttle Example ( ) Ascent and Entry Guidance - PASS Architecture of the Space Shuttle Primary Avionics Software System Gene D. Carlow [Canvas] Phases of Flight Divided into Major Modes [E.g. 601] Each Mode Has Real-Time Scheduling Cyclic Executive with High, Medium and Low Frequency Each Executive is a Loop with Interrupts to Preempt it Services are Implemented on an Executive E.g. Control and Sensors in HFE (Stability, Monitoring, Health & Safety) E.g. Navigation in MFE (State Estimation from Multiple Sensors over Time) E.g. Guidance in LFE (Long Term Targets) Sam Siewert 26

27 DATA CHASER Shuttle Payload Example ( ) Rapid Development 1 Year from Concept to Launch Demonstration of AI Real-Time Automation for Payloads Anytime Algorithms Used for On-Line Planning/Re-planning Services Motorola 68EC030 Custom FPGA IO Boards for 3 Instruments Fairly Low Resource Utilization (Low Frame Rates) RS baud Command/Telemetry RS422 1 Mbit / sec Downlink for Science Data Flown on STS-85 Automation Demonstration Successful Science Return Minimal Developed by CU for JPL Sam Siewert 27

28 SIRTF High Level Design Example ( ) CPU Bound 95%+ Loading for Sky-Scan Mosaic Images Data Compression Synchronization Between Space Telescope Slew and Imaging IO Bound 95%+ VME Bus Loading for Sky-Scan 3 Synchronized Detectors Operating Concurrently FIFO interface Block Transfer Write-through DMA prevented use of DMA Read/Write Multiple Instruction on PowerPC (Programmed IO) Data Compression and Grouping for Downlink Allocation of Functions/Service to: 2 Hardware State Machines (Actel FPGA) 23 VxWorks Tasks In Operation Now ( Sam Siewert 28