ReconOS: An RTOS Supporting Hardware and Software Threads

Transcription

1 ReconOS: An RTOS Supporting Hardware and Software Threads Enno Lübbers and Marco Platzner Computer Engineering Group University of Paderborn

2 Overview the ReconOS project programming model system architecture case study ongoing / future work

3 The ReconOS Project goal: try to bridge the gap between application developers and modern reconfigurable architectures three key components programming model provides abstractions to facilitate application development execution model provides hw/sw implementation of OS services and supports partial reconfiguration Programming Model System Description Generation of of Runtime System automated generation of the runtime system facilitates adaptation of the OS to different target architectures and application domains Execution Model Application OS

4 RTOS-like Programming Model applications are modelled with a set of objects tasks/threads, semaphores, FIFOs, shared memory, timers, etc. these objects, their semantics and possible relationships form kind of a programming model their implementations are provided by the runtime system

5 RTOS-like Programming Model classic (RT)OS programming model threads interact with the OS through API functions eg. semaphore_post(), thread_create(), malloc() distinction between blocking and non-blocking calls sequential execution of threads challenges in translating this model to hardware hardware is inherently parallel "hardware thread" is actually a misnomer hardware has no notion of function calls or even blocking function calls parallel execution of several hardware threads and one software thread sw-hw and hw-hw synchronization and communication scheduling ReconOS approach: extend software RTOS delegate threads hardware threads with OS synchronization state machine

6 basic mechanism a delegate thread in software is associated with every hardware thread the delegate thread calls the OS kernel on behalf of the hardware thread all kernel responses are relayed back to the hardware thread advantages no modification of the kernel required extremely flexible transparent to kernel and other threads drawbacks increased overhead due to interrupt processing and context switch Delegate Threads

7 ReconOS Hardware Threads a hardware thread consists of two parts an OS synchronization state machine synchronizes thread with operating system calls serializes access to OS objects via the OS interface can be blocked by the OS interface parallel user processes communicate with OS synchronization state machine can directly access local memory blocks is not necessarily blocked

8 ReconOS API for Hardware Threads VHDL function library may only be used in the OS synchronization state machine

9 OS Interface Implementation processes requests from hardware thread memory accesses are handled directly OS object interactions are relayed to delegate thread master interface single word and burst transfers direct access to entire system s address space (memory and peripherals) slave interface CPU addressable registers used for OS communication dedicated CPU interrupt used to signal pending OS interaction request

10 OS Call Implementation shared memory semaphore notify available CPU delegate blocking SW-OS (ecos) cyg_sem_wait() interrupt read unblock OS request notify (OS request pending) write system bus blocking hardware thread request = sem_wait

11 System Architecture development platforms Xilinx ML40 (Virtex-4FX) Xilinx XUPV2P (Virtex-II Pro) embedded PowerPC 40 CPU(s) CoreConnect bus architecture FPGAs support partial reconfiguration real-time operating system ecos for PowerPC ported to development platforms ecos is a widely-used open source RTOS modular, extensible design supplemented with OS interface for hardware threads

12 Toolchain software threads are written in C compiled against the ecos libraries ecos extensions hardware thread objects encapsulating delegate thread and OS interface driver hardware initialization routines profiling support to track the state of the hardware threads' OS synchronization state machines hardware threads are written in VHDL using the ReconOS API for accessing OS functions generation of the hardware architecture automatic insertion of OS interfaces and hardware threads into the Xilinx EDK platform descriptions synthesis of interface structures necessary for partial reconfiguration

13 three threads Case Study - Image Processing Filter capture image from Ethernet apply LaPlacian filter display image on VGA monitor platform Xilinx XUPV2P (Virtex-II Pro) 00MHz, 100MHz OS interface takes 101 slices (7% of FPGA) threads communicate through shared memory image resolution: 20x240 pixels, 8 bit grayscale image data organized into blocks (e.g. 40 lines = 1 block) a block is protected by two semaphores ready semaphore: data can be safely written into this block new semaphore: new data is available in this block

14 all threads in software Case Study - Implementation #1 performance depends on block and window size window size block size [lines] w config SW-SW-SW SW-SW-SW performance [frames/s]

15 Case Study - Implementation #2 move filter thread to hardware convolution filters allow for efficient parallelization block size [lines] w config SW-SW-SW SW-HW-SW SW-SW-SW SW-HW-SW performance [frames/s]

16 Case Study - Implementation # move also display thread to hardware display thread can output data concurrently with capture thread block size [lines] w config SW-SW-SW SW-HW-SW SW-HW-HW SW-SW-SW SW-HW-SW SW-HW-HW performance [frames/s]

17 Case Study - Implementation #4 parallel hardware threads double-buffer image data w config SW-SW-SW SW-HW-SW SW-HW-HW SW-HW-HW double buffered SW-SW-SW SW-HW-SW SW-HW-HW SW-HW-HW

18 Ongoing / Future Work include (again) partial reconfiguration extend ecos scheduler preemption, task migration add monitoring infrastructure for debugging and performance tuning prototypes Virtex-4FX: Xilinx ML40 Virtex-II Pro: Xilinx XUPV2P Virtex-II: ESM front-ends for ReconOS image processing real-time task scheduling (integrate own previous work) POSIX (for comparability)

19 Collaboration with the "Hybrid Threads" Project group of Prof. David Andrews, U Kansas, USA execution of hardware and software threads on a CPU/FPGA hybrid RTOS services in hardware for low jitter and fast response times C hardware tool flow based on POSIX threads API joint efforts quantitative comparisons partial reconfiguration multiple CPUs David Andrews et al. Programming Models for Hybrid FPGA-CPU Computational Components. A Missing Link. IEEE Micro, July 2004