FABRICATION TECHNOLOGIES

Transcription

1 FABRICATION TECHNOLOGIES

2 DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general purpose * Design domain of EEC 281 lower design time lower one-time cost B. Baas 5

3 VLSI Design Technologies Characterized by their minimum feature length (length of transistor s gate) Some typical state-of-the-art fabrication technologies in 2018: 14 nm Mature production for logic chips 7 nm Example to be presented at ISSCC Feb 2018: A 7nm FinFET SRAM Using EUV Lithography with Dual Write-Driver-Assist Circuitry for Low- Voltage Applications B. Baas 6

4 Full Custom All transistors and interconnect drawn by hand Full control over sizing and layout [figure from S. Hauck] B. Baas 7

5 Full Custom Multiplier chip Multiplier I/O pads Clock generator Control logic Buffers B. Baas 8

6 Standard Cell Constant-height cells Regular pin locations Regular layout allows CAD tools to much more easily automatically place and route cells [figure from S. Hauck] B. Baas 9

7 Standard Cell Channels for routing only in older technologies (not necessary with modern processes with many levels of interconnect) [figure from S. Hauck] B. Baas 10

8 Standard Cell Wireless LAN chip Ten major standard cell blocks Many embedded memory arrays Horizontal power grid stripes B. Baas 11

9 Combination Standard Cell and Dense, regular fullcustom blocks Random logic implemented with standard cells and automatic place and route Full Custom B. Baas 12 [figure from S. Hauck]

10 Typical Standard Cell, Gate Array, or FPGA Design Flow Involves synthesizing Verilog source code to generate a gate netlist made up of elements from the Standard Cell library Design Compiler (DC) by Synopsys is the most popular synthesis tool used in industry The same Verilog design could be synthesized to various libraries; for example: Standard cell (NAND, NOR, Flip-Flop, etc.) FPGA library (CLBs, LUTs, etc.) Verilog (or VHDL) Quartus Synopsys Design Compiler compile script(s) Synthesis CAD Tool cell library Std Cell: gate netlist FPGA: config bitfile Hardware Implementation reports B. Baas 13

11 Simplified diagram of Standard Cell design flow after synthesis Gate Netlist Verilog from Synthesis Place & Route Final Layout (could be fabricated) Gate-level Verilog DRC LVS Design rule check Layout vs. schematic Timing Information Gate level dynamic and/or static analysis B. Baas 14

12 Gate Array Polysilicon and diffusion are the same for all designs Metal layers customized for particular chips PMOS transistor p-type diffusion polysilicon n-type diffusion NMOS transistor B. Baas 15

13 Gate Array Polysilicon and diffusion the same for all designs um example [figure from LETI] B. Baas 16

14 Field Programmable Gate Array (FPGA) Metal layers now programmable with SRAM instead of hardwired during manufacture as with a gate array Cells contain general programmable logic and registers [figure from S. Hauck] B. Baas 17

15 Field Programmable Gate Array (FPGA) Chips now designed with software User pays for up-front chip design costs All: full-custom, standard cell Half: gate array Shared: FPGA User writes code (e.g., verilog), compiles it, and downloads into the chip The flexibility comes at a great cost however; FPGAs are over 10x slower, less energy efficient, and greater area than a Standard Cell design B. Baas 18

16 Programmable DSP Processor TI C64X 600 MHz, 0.13 um, V 8-way VLIW core 2-level memory system 64 million transistors [figure from S. Agarwala] B. Baas 19

17 General Purpose Processor Intel 8086 First released mm µm 4 12 MHz 29,000 transistors B. Baas 20

18 4.80 GHz General- Purpose Processor Intel i9 (formerly called Coffee Lake) [i9-8950hk] 14 nm CMOS 6 cores (12 threads) 2.90 GHz base frequency 4.60 GHz standard turbo frequency 4.80 GHz maximum turbo frequency possible only if the CPU is below 53 C 12 MB on-die cache 45 Watts TDP (Thermal Design Power) EEC 281, B. Baas 21

19 Massive General-Purpose Server Processor Itanium Poulson 32 nm 3.1 Billion Transistors 18.2 mm x 29.9 mm = 544 mm 2 8 multi-threaded cores 54 MB total on-die cache 170 Watts TDP [ISSCC 2011] B. Baas 22

20 Massive Special- Purpose Processor Nvidia V100 TSMC 12 nm FinFET 21.1 Billion Transistors 815 mm 2 Approximately 37.9 mm x 21.5 mm At the reticle limit 1.45 GHz 80 streaming multiprocessors 300 Watts TDP Memory interface to HBM GHz, 4096-bit bus, 900 GB/s [HotChips 2017] B. Baas 23