Digital Integrated Circuits
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1 Digital Integrated Circuits Lecture Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University
2 Design/manufacture Process Chung EPC655 2
3 Design/manufacture Process Chung EPC655 3
4 Layout Design Design -> Layout Chung EPC655 4
5 Mask Making (in Manufacturing Phase) Mask Chung EPC655 5
6 Fabrication Imprint Chung EPC655 6
7 Fabrication Fabrication Technology Chung EPC655 7
8 Fabrication Fabrication Technology Wafer Die Chung EPC655 8
9 Fabrication Test Automatic Test Equipment Chung EPC655 9
10 Design/manufacture Process In chip production, every chip will be manufactured and tested. A chip is shipped to customers, if it works according to specification Chung EPC655
11 Fabrication Test for What? Particle Chung EPC655
12 Fabrication Test for What? Metal Break Chung EPC655 2
13 Fabrication Test for What? Bridge Chung EPC655 3
14 Package If Test Passes Chung EPC655 4
15 Design For Test DFT Chung EPC655 5
16 CHAPTER Chapter Hardware Testing and Design for Testability Manufacturing Test Manufacturing Yields Less Than % Many Ways Defects Can Be Introduced Dust Particles on Mask, Pin-Holes in Oxide, Opens in Metal Vias, etc. Must Thoroughly Test Hardware Before Using or Selling to Customer Chung EPC655 6
17 MANUFACTURING TEST Design Verification Check that Design Meets Specifications Look for Design Bugs Done Using Software Simulation E.g., Using Test Bench in HDL Can Observe All Nodes Manufacturing Test Check that Each Manufactured Part Matches Design Look for Manufacturing Faults Done Using External Tester Can Only Observe Chip Pins Chung EPC655 7
18 FAULT MODEL Fault Model Models Effect of Defects on Logic Values in Circuit Stuck-At Fault Model Most Commonly Used Fault Model Each Line in Circuit Can Be Stuck-at or Stuck-at Chung EPC655 8
19 DETECTING FAULTS To Detect Fault Need to Use Test Pattern That Causes Output to Be Different if Fault Present Chung EPC655 9
20 TESTING AND-OR CIRCUIT Applying Exhaustive Test Requires 52 Patterns c, f, i, p, q, r b, e, h, p, q, r a, d, g, p, q, r g, h, i, r d, e, f, q a, b, c, p Faults Tested i h g f e d c b a c, f, i, p, q, r b, e, h, p, q, r a, d, g, p, q, r g, h, i, r d, e, f, q a, b, c, p Faults Tested i h g f e d c b a Chung EPC655 2
21 PATH SENSITIZATION Chung EPC655 2
22 TEST GENERATION Select Untested Fault Determine Input Assignments to Provoke Fault Put Opposite Value on Fault Site From Fault Value Assign Additional Inputs to Propagate Fault Sensitize Path from Fault Site to Primary Output Identify Additional Faults Tested Repeat for All Undetected Faults Chung EPC655 22
23 EAMPLE Vectors Normal Gate Inputs A B C D a b p c q r d s t u v w F Faults Tested a p c v f a b p q r d u v w f b c s t v w f a b d s t u w f a b q r s t u w f Chung EPC655 23
24 FAULT SIMULATION Fault Simulation Input Set of Test Patterns Fault List Output Fault Coverage Percentage of Faults Detected Chung EPC655 24
25 ATPG Automatic Test Pattern Generation (ATPG) Input Fault List Output Set of Test Patterns NP-Complete Problem Cannot Always Get % Fault Coverage Redundant Faults Aborted Faults Test Efficiency = Detected Detected+Aborted Chung EPC655 25
26 TESTING SEQUENTIAL LOGIC Behavior of Sequential Logic Depends on Sequence of Inputs Testing More Difficult Than Combinational Circuits Chung EPC655 26
27 SCAN TESTING Chung EPC655 27
28 TESTERS Automated Test Equipment (ATE) Very Expensive Each Second on Tester Adds Significantly to Cost of Chip Test Time Very Important Limited Amount of Memory, Channels, Speed Chung EPC655 28
29 BOUNDARY SCAN Board Testing Bed-of-Nails Not Practical for High Density PC Boards Fine Traces and Complex ICs Boundary Scan IEEE 49. aka JTAG Chung EPC655 29
30 Pins for IEEE 49. BOUNDARY SCAN TDI Test Data Input TCK Test Clock TMS Test Mode Select TDO Test Data Output TRST Test Reset (Optional) Chung EPC655 3
31 BOUNDARY SCAN Chung EPC655 3
32 BOUNDARY SCAN ARCHITECTURE Chung EPC655 32
33 BOUNDARY SCAN ARCHITECTURE Chung EPC655 33
34 IEEE 49. INSTRUCTIONS BYPASS TDI Goes Through Bypass Register SAMPLE/PRELOAD Shift Scan Chains without Changing Output of Scan Cells ETEST Apply Vector to Output Pins Capture Data from Input Pins INTEST Apply Vector to Core Logic Capture Data from Core Output RUNBIST (Optional) Executes Special BIST Logic Chung EPC655 34
35 BUILT-IN SELF-TEST (BIST) Built-In Self-Test (BIST) Chung EPC655 35
36 BUILT-IN SELF-TEST (BIST) Built-In Self-Test (BIST) Add Hardware so Chip can Test Itself Test Pattern Generator Output Response Analyzer Chung EPC655 36
37 MEMORY BIST Memory BIST (MBIST) Widely Used Very Useful for Embedded RAMs Chung EPC655 37
38 MEMORY BIST Can Use Multiple-Input Signature Analyzer (MISR) Chung EPC655 38
39 MEMORY BIST Memory Test Algorithms Checkerboard and Complement Tests Stuck-at Faults Tests Bi-Directional Bridge Faults March 4N Test Algorithm 4N Means 4 Operations Per Memory Location Tests Uni-Directional Bridge Faults Also Address () -> Address(MA): W() Address () -> Address(MA): R(), W(), R() Address () -> Address(MA): R(), W(), R() Address (MA) -> Address(): R(), W(), R() Address (MA) -> Address(): R(), W(), R() Address (MA) -> Address(): R() Chung EPC655 39
40 After this course More details on digital chips ASIC designs A lower level of abstraction Circuit-level, transistor-level, layout-level INU does not offer this course for undergraduate Chung EPC655 4
41 After this course Broader study on digital systems System designs using components/chips System-on-chips Focus on systems with OS A higher level of abstraction (higher than architecture-level) System-level, Board-level, Operating System-level Interface/Interactions between hardware and software Important concepts of OS EPC67 Embedded System Design Chung EPC655 4
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