SoC Design Flow & Tools: SoC Testing

Transcription

1 SoC Design Flow & Tools: SoC Testing Jiun-Lang Huang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University

2 Outline l SoC Test Challenges l Test Access Mechanism l Core Test Wrapper l IEEE P1500 l Test Optimization l Analog/Mixed-Signal Testing 2

3 SoC Test Challenges

4 VLSI Realization Process Customer Needs Determine Requirements Write Specifications Design Synthesis and Verification Test Development Fabrication Manufacturing Test Chips to Customers 4

5 The Role of Testing l The role of testing is to detect whether something went wrong. l Diagnosis, on the other hand, tries to determine exactly what went wrong & where the process has to be altered. l Test objectives Design verification Ensure product quality Diagnosis & repair 5

6 What are we after? l Design errors Violations of design rules. Incorrect mapping between different levels of design Incomplete or inconsistent specification l Fabrication errors (caused by human errors) Wrong components Incorrect wiring Shorts caused by improper soldering 6

7 l Fabrication defects (caused by imperfect manufacturing process) Mask alignment errors Improper doping profiles l Physical failures Electro-migration or corrosion Aging/Wear-out of components Infancy failures 7

8 Types of Testing System specifications Architecture design Logic & Circuit design Physical design Layout Fabrication Packaging l l l l Transformation of customer requirements to system specifications is audited. The design is verified against the system specifications to ensure its correctness. Fabricated parts are subjected to characterization/production testing and/or incoming inspection to detect process defects. Failure mode analysis (FMA) is applied to failed parts 8

9 Characterization Testing l For design debug and verification Usually performed on a new design prior to mass production. Verify the correctness of the design & determine exact device limits. Comprehensive functional, DC and AC parametric tests are applied to a set of samples. Use of specialized equipment Scanning electron microscope (SEM) Electron beam tester l Results are used for setting final spec. and developing production testing program. 9

10 Production Testing l To enforce quality requirements Applied to every fabricated part. The test set is short but verify all relevant specifications, i.e., high coverage of modeled faults. l Test cost and time are the main drivers. 10

11 Burn-In Testing l Occurrence of potential failures can be accelerated at elevated temperature The main purpose is to screen out infant mortality l Methods of burn-in Static burn-in Dynamic burn-in Test during burn-in High-voltage stress burn-in The combinations of the above 11

12 Bathtub Curve of IC s Failure Rate l Early failure detection reduces cost Burn-in to isolate infant mortality failures Infant mortality period Normal lifetime Wear-out period Failure rate ~ 20 weeks 5 25 yrs Time 12

13 Incoming Inspection l Type of tests May be similar to or more comprehensive than production testing. May be tuned to specific applications. l May be performed by test house. l May be applied to random samples only. 13

14 The Principle of Testing 14

15 Test Quality Number of acceptable parts Yield Y = Number of fabricated parts Number of detected faults Fault CoverageT = Number of all possible faults Defect Level DL = 1- Y 1-T 15

16 Test Economy Cost of Manufacturing Testing in 2000 l GHz analog instruments with 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second 16

17 Technology Trend: System-on-Board to System-on-Chip Physical components System on Board Virtual components System on Chip 17

18 The Impact l SoC components are only manufactured and tested in the final system. SoB Process SoC Process IC Design ASIC Design Core Design UDL Design IC Fab. ASIC Fab. IC Test ASIC Test SOB Design SOB Fab. SOB Test SOC Design SOC Fab. SOC Test 18

19 Separation of Responsibilities l The core provider Test pattern generation for the cores. Core internal design-for-testability. l The core user Test generation for the chip Reuse of core-level test patterns. Additional test patterns for non-core circuitry. Chip-level design-for-testability. 19

20 SoC Test Challenges l Distributed design & test l Test access l Test optimization 20

21 Distributed Design & Test l In general, the core provider develops the core test including DfT & test patterns. l However, the core provider does not know the system chip environment Which test method to use? What type of faults to target? What level of fault coverage? which may lead to inadequate test quality, or waste of resources. 21

22 l Need a set of standardized set of deliverables. Test methods Test modes and protocols Fault models and fault coverage Test pattern data Core-internal design-for-test Core-internal design-for-diagnosis Diagnostics and failure analysis information 22

23 Test Access l Direct access to deeply embedded cores is difficult. l It s not uncommon that core s I/O pin count > SoC s I/O pin count l To test each core, we need to provide core test access, and core isolation mechanism. 23

24 Test Optimization l l Test access infrastructure optimization Test quality vs. overhead Constrained test scheduling Overall test time Power consumption Test access bandwidth Available test resources Other considerations Core a Core b Core c Core d Core e Core g Core f Time 24

25 A Conceptual SoC Test Architecture

26 A Conceptual SoC Architecture Source TAM CUT TAM Sink Wrapper l l l Test pattern source and sink The source generates the test stimuli for the embedded core. The sink compares the responses to the expected responses. Test access mechanism (TAM) Test data transport from the test source to the CUT and from the CUT to the test sink. Core test wrapper Connects the terminals of the core to the rest of the IC and the TAM. [Zorian, Marinissen, Dey ITC98] 26

27 A Conceptual Test Architecture DAC mp SRAM Source PCI TAM Wrapper CUT TAM Sink ROM DSP 27

28 On/Off-Chip Test Source/Sink Source DAC PCI ROM mp CUT DSP SRAM Sink On-chip Source/Sink Closer to CUT Less TAM area Less dependence on ATE BIST area overhead Off-chip Source/Sink Bandwidth limited by pin count More TAM area More expensive ATE Src. DAC PCI src mp CUT SRAM snk Snk. ROM DSP 28

29 Test Access Mechanism (TAM)

30 TAM l Function Deliver test stimuli from the test source to the CUT. Transport test responses from the CUT to the test sink. l TAM design involves making trade-offs among data transport capacity, test time, and TAM overhead. 30

31 TAM Width l Determines the test data transport bandwidth. l Considerations A wider TAM shortens the test time, but consumes more wiring area. The width of the test source and sink. Available IC pins if external test source/sink. l Constraints to meet Test time Area overhead 31

32 TAM Length l Physical distance l Ways to reduce TAM length On-chip test sources and/or sinks. Sharing TAM among cores can shorten the total TAM length. Reduced wiring area. Possibly reduced test concurrency. Reusing functional hardware as TAM. May not meet the desired test time constraint. 32

33 TAM Implementations l l l l l Direct access scheme Immaneni, Raman ITC90 Bus-based scheme Varma, Bhatia ITC98, Harrod ITC99 Transparency Beenker D&T86, Beenker 95, Marinissen TECS97, Ghosh et al. ITC97, CAC98 Boundary-scan based Whetsel ITC97, Bhattacharya VTS98, Touba, Pouya D&T97, ITC97 Test Rail Marinissen et al. ITC98 33

34 Direct Access Scheme l Map all core inputs, outputs, and I/O onto package pins. l In test mode, the I/Os of the selected core are accessible through a group of package pins. Each core can be tested with its standard test program. l Test isolation provided and cores are tested independently. [Immaneni, Raman ITC90] 34

35 Direct Access Scheme l Modification to user logic block. TSEL TMODE > Embedded Output Embedded Bidirectional User In Test In Primary Input Input > > User Logic Block > <> > Dir Ctrl Bi-Dir Embedded Bidirectional Control Primary Output <> Primary Bidirectional Output 35

36 Direct Access Scheme l An implementation example UIN TIN TMODE Out TSEL TSEL1 Output Pad Input Pad UIN TIN TMODE Out TSEL TSEL2 User Signal Output Pad Input Pad Input Pad TMODE UIN TIN TMODE Out TSEL TSEL3 Test Control Logic 36

37 Remarks l Advantages Embedded cores can be tested and debugged as a stand-alone device. Transition from core-level test to chip level test is simple. A slight increase in overall package pin count and design complexity. l Drawbacks Not scalable. The complexity of control logic and test circuitry grows with the number of embedded cores. Long test time. Blocks are tested sequentially. 37

38 Bus-Based TAM l Utilizing on-chip system bus or dedicated test bus for test data transport. Varma, Bhatia ITC98 Harrod ITC99 Src. DAC mp SRAM ROM DSP Sink 38

39 Test Bus l Architecture overview. TDI/O Core Core TDI TDO Test Ctrl Test Bus [Varma, Bhatia ITC98] 39

40 Test Bus l An example Core Core Input Test Bus Core 72 Core Output Test Bus 40

41 Remarks l Advantages Compatible with IEEE Flexible, scalable. l Drawbacks Performance degradation. Area overhead. 41

42 AMBA Bus-Based Testing l Test vectors produced for an AMBA-compliant IP block can be reused in any AMBA-based system. l The AMBA Test Interface Controller (TIC) is responsible for test application and response capture. l In test mode TIC becomes the AMBA bus master. The external bus interface (EBI) is reconfigured to provide a high-speed, 32-bit, parallel vector interface. [Harrod ITC99] 42

43 AMBA Bus-Based Testing l Peripheral test harness Access to I/O s not connected to the bus. Isolate the core under test from its environment. 43

44 AMBA Bus-Based Testing 44

45 Remarks l Advantages Reusing system bus reduces TAM overhead. Transition from core-level test to chip-level test is simple. l Drawbacks Fixed bus width may be insufficient for some cores. Difficult to integrate full-scanned cores. 45

46 Transparency DAC mp SRAM Source PCI CUT Sink ROM DSP 46

47 Transparency l Transparent path A path from input to output which propagates data without information loss. l Examples Scan chains Arithmetic functions: + 0, x1 Embedded memories Basic gates: AND, OR, INV, MUX l Past techniques Beenker D&T86, Beenker 95, Marinissen TECS97, Ghosh et al. ITC97, CAC98 47

48 Remarks l Advantages Low area overhead l Drawbacks Transport latency through cores The desired transparency is not guaranteed. Too much transparency waste. Too little transparency TAM needed. Non-trivial transition of core-level test to chip-level test. 48

49 Boundary Scan l An IEEE compliant chip. l board-level view. TCK TMS TDI TDI Digital circuit TDO TDI TDI TMS TAP controller TDO TCK TDO TDI : Boundary scan cell TDO TDO : Boundary scan path 49

50 Remarks l Advantages Existing well-known, well-documented standard. Reuse IC level implementation. l Drawbacks Fixed 1-bit TAM width. Complexity of test control and test data wiring grows with the number of cores. Multiple TAP controllers. 50

51 Test Rail l IC level view. Core A Core B1 Core C Core E1 8 Core D1 Core 1F 4 12 [Marinissen et al. ITC98] 51

52 Test Rail l Core level view. Core Parallel Serial Decompression Core Compression Compressed Core 52

53 Test Rail l An example. A: 4 scan chains. B: BIST C: Functional test A Decomp. B Comp. C 53

54 Remarks l Advantages Flexible Enables integration of various core test techniques. Scalable Allows trade-offs between area, quality, and test time. l Drawbacks Difficult to find optimal solution. 54

55 Multiplexing Architecture Core A Core B Core C [Aerts & Marinissen ITC98] 55

56 Daisy Chain Architecture Core A Core B Core C [Aerts & Marinissen ITC98] 56

57 Distributed Architecture Core A Core B Core C [Aerts & Marinissen ITC98] 57

58 Remarks l Different types of TAMs may coexist on a single chip. l Cores connected to different TAMs can be tested concurrently. l Cores connected to the same TAM cannot be tested concurrently. 58

59 Core Test Wrapper

60 Core Test Wrapper l Function Interface between the core and its environment. Width adaptation Provision of the following modes Normal: function mode InTest: inward-facing core test mode ExTest: outward-facing interconnect test mode l Considerations Test time. Performance degradation. Area overhead. 60

61 Functional Only Connection Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C 61

62 Wrapper & TAM Bypass Bypass Bypass Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C est Control Test Control Test Control 62

63 Normal Operation Bypass Bypass Bypass Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C est Control Test Control Test Control 63

64 InTest Bypass Bypass Bypass Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C est Control Test Control Test Control 64

65 ExTest Bypass Bypass Bypass Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C est Control Test Control Test Control 65

66 Bypass Bypass Bypass Bypass Scan Chain Scan Chain Core A Scan Chain Scan Chain Core B Scan Chain Scan Chain Core C est Control Test Control Test Control 66

67 IEEE P1500 Standard for Embedded Core Test (SECT)

68 Core-Based Test l The core provider delivers the core design itself, and a set of tests for the core. l The core user assembles a chip-level test from the pre-defined tests for the various cores, and additional tests for non-core circuitry. l A test as described above, in which cores are tested as stand-alone units, is called a corebased test. 68

69 P1500 Overview l l IEEE P1500 SECT is a standard under development that aims at improving ease of reuse, and facilitating interoperability with respect to the test of core-based ICs, especially when they are from different sources. Main components Standardized, scalable core test wrapper Core test Information Model Core Test Language (CTL) Two Compliance levels IEEE 1500 Unwrapped IEEE 1500 Wrapped 69

70 A System Chip with P1500 Wrapped Cores 70

71 P1500 Wrapper l Modes Transparent functional mode Inward-facing for core-internal tests (InTest) Outward-facing for core-external tests (ExTest) l Interface One Single-bit TAM plug is mandatory. Optional Multi-bit TAM plug. Optional width adaptation for TAM plugs. Optional modes similar to JTAG s preload and clamp. 71

72 The P1500 Wrapper Architecture 72

73 The P1500 Wrapper Boundary Cell l l Cell modes Normal, Inward facing, Outward facing, Safe Cell events Shift, Capture, Apply, Update, Transfer 73

74 P1500 Wrapper Parameters l Bandwidth Number and/or width of WPI-WPO pairs. l Instructions Optional instructions User-defined instructions OpCodes of instructionse l WBR functionality Shared or dedicated wrapper cells Shift-only or Shift + Update cells Storage capacity (one or more bits) Ripple protection (w/ Update register or gate) Safe State output values 74

75 Test Optimization

76 Problem Statement l Given the test related information of each core, e.g., test pattern, I/O, etc., minimize the test cost. l Main test cost components DfT: Area overhead, performance degradation Test development Manufacturing test: test time l Other considerations Power dissipation Place & route constraints 76

77 Test Scheduling Techniques l Co-optimization of all HW/SW parameters is too expensive. l Most researches deal with a subset of the parameters. l Test scheduling approaches Tree growing [Jone et al. DAC89, Muresan et al., ITC00] List scheduling [Muresan et al. VTS00] ILP formulation [Chakrabarty et al. ICCAD99, Nourani et al. ITC00] Simulated annealing [Larsson et al. ICCAD01] 77

78 Tree Growing Approaches [Jone et al. DAC89, Muresan et al., ITC00] l Test time minimization under power constraints. l The test scheduling information is embedded in he tree structure. l Tree growing constraints (along a path from root to leaf) Test resources Test length Power constraint 78

79 t 1 t 7 t 8 t 3 t 5 t g1 t 4 t 2 t g2 t 6 t g3 t 1 t 7 t 8 t 3 t 5 t g1 t 4 t 2 t g2 t 9 t g3 79

80 ILP Formulation [Chakrabarty et al. ICCAD99, Nourani et al. ITC00] l The test optimization problem is described as: Minimize Ax + By subject to Cx + Dy E x 0 y 0 where A and B are cost vectors, C and D are constraint matrices, E is a column vector of constants, x is a vector of integer variables, and y is a vector of real variables. 80