Advancing Test and Measurement Instrumentation using New Transmission Line Technologies
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1 Advancing the High Speed Interconnect Ecosystem Advancing Test and Measurement Instrumentation using New Transmission Line Technologies ATE, Load Boards, Test Sockets, Device Interface, and Probes Jamal S. Izadian, Ph.D. RFCONNEXT, Inc., Patents Pending Materials 1
2 Outline Incremental PMTL/VMTL embedding into ATE A) Existing Test System B) Evolving Test System C) Overhaul of Current ATE Probes, Sockets, Cabling, Connectors N Port Network Analyzer Implications,Includeds Patents Pending Materials 2
3 ATE Systems Components ATE interface, POGO PINS bed/blindmate Load Cards Matching POGO PINS(or Blind Mate Connectors) contact array for ATE interface Device Interface for Test Sockets Probes Handlers/Trays/Mechatronics,Includeds Patents Pending Materials 3
4 Current ATE System Technology,Includeds Patents Pending Materials 4
5 Intermediate Solution,Includeds Patents Pending Materials 5
6 Interfacing to Existing ATE Footprint Using PMTL,Includeds Patents Pending Materials 6
7 Interface To Internal ATE Ports(Alternative to Probe Cards),Includeds Patents Pending Materials 7
8 Implementing Standardized PMTL 2D Connector Array,Includeds Patents Pending Materials 8
9 Standardized Connector Array with Footprint Mapping Allows all parts from ATE vendor, Device Interface (probes, Sockets) vendor, and spatial transformer vendors, all fit together perfectly Disengaged Engaged Third Party Connectorized Test Layers, i.e, embedded passives, active, interface mapped, etc,includeds Patents Pending Materials 9
10 Standardized Connector Array with Footprint Mapping, with uflex PMTL Engaged,Includeds Patents Pending Materials 10
11 Universal Test Socket For Quad Packs (UTS) With embedded PMTL
12 RFConnext s Reconfigurable Device Trying to Match Existing Socket Foot Print Oneto One (gray lines) Match the Boards Pad Foot Print Uses a Minimal Space Low Profile Modular Interface UTS,Includeds Patents Pending Materials 12
13 3D View, matching Foot print and Board Interface and Pad Pattern,Includeds Patents Pending Materials 13
14 Removing Layers, showing easily replaceable contactors,includeds Patents Pending Materials 14
15 Removing Next Layer, showing easily replaceable contactors,includeds Patents Pending Materials 15
16 The PMTL Connectivity, all replaceable parts DUT Individually or group Replaceable Contact mini Cards with patent pending PMTL,Includeds Patents Pending Materials 16
17 DUT removed,includeds Patents Pending Materials 17
18 In Quad Arrangement 1x4 array, shown with QFN DUT,Includeds Patents Pending Materials 18
19 3D View,Includeds Patents Pending Materials 19
20 Advantages of RFC Solution Because of patent pending PMTL, we can bring reference ground for Board pad to the DUT pins, reducing parasitic, and eliminating requirement for impedance re matching Impeccable single or differential signals with controlled impedance Special connector technology, distributes the contact energy to larger areas, thus helping to last longer,includeds Patents Pending Materials 20
21 Advantages of RFC Solution 2 Easy Access to Contactor and easy replacement from top, disposable No need to remove socket from Board for repair/replacement of contactor Ground Contact from side, and bottom, Heat Sinking are from Bottom Very low Foot Print, can increase DI density 64:1 for current performances board,includeds Patents Pending Materials 21
22 Advantages of RFC Solution 3 Modular construction can be very easy access Scaleable to various DUT, and Packages and types Reduces ATE down time We were limited by the Existing Footprint, if we are allowed to modify Performance Board Pad pattern, slightly, we could further improve utility of our GIGA LOW UTS,Includeds Patents Pending Materials 22
23 Increasing DUT Density 16:1 for a single Spot 64:1 for Quad Our Modular Technology allows Increasing Testing Parallelism On Exiting Load Cards
24 Comparing Present Foot Print with a Note that for the same Socket Foot Print, we can provide 4x4 interface or 16:1 For the quad board, this will be 64:1 Promises increased parallel testing 4x4 DI (QFN DUT),Includeds Patents Pending Materials 24
25 3D view of proposed 4x4 Socket Array,Includeds Patents Pending Materials 25
26 Close up of a single DUT,Includeds Patents Pending Materials 26
27 BGA/LGA test Universal Socket With MxN array with possible calibrated reference at DI, using SOLT, LRL, TRL, TOSR, and others Uniform Signaling, DC 65GHz, Power, control, Mixed Signal, High Speed, RF THE FUTURE OF MULTI PORT VNA,Includeds Patents Pending Materials 27
28 UTS with 2D Connection Array, of Single or Differential, or Hybrid of PMTL external to Test Head,Includeds Patents Pending Materials 28
29 Evolution of Integrated ATE and UTS Device Interface Outside ATE ATE Interface Connector Device Interface Inside ATE,Includeds Patents Pending Materials 29
30 The Future of ATE Standardized, Mapable INTERFACE 2D Connector of full bandwidth, TEM PMTL interface with uflex Printed PMTL Cables fan out/fan in,includeds Patents Pending Materials 30
31 The Benefits of New PMTL/VMTL Technologies for ATE s Standardized Footprint Multivendor, Multi user compatibility Controlled Impedance all the way to die pad Uniform Signaling contents, DC Control Digital RF Mixed Signals Single/ Diff Pairs Embedded Components(Third Party Products) L,C,R, Chips, Bias Tee s Superior Electrical Performance No or low cross talk No parasitic, PMTL /VMTL Confined Field Interconnect(CFI) Universal Test Probes Reconfigurable Footprint, Pitches 25u and up Variable force contact Reusable, replaceable, disposable, low cost Independent probes tips with + z Grouped in desired multiples Match a large families of die pad patterns,includeds Patents Pending Materials 31
32 The Benefits of New PMTL/VMTL Technologies for ATE s Flexible PMTL Fan out in, Complete mechanical decoupling, Provide fine and coarse Z movements Equal Delay, Minimum or no Skew Controlled Impedance, Excellent match Low Insertion loss Provides excellent phase linearity compared to traditional coaxial lines and connectors Standardized 2D PMTL Connection Array No more POGO pins Mapping any ATE to any Device footprint Cheaply Readily Cross Platform Utilization Wide bandwidth for the future PMTL /VMTL TEM transmission line technology provided DC 50GHz bandwidth and beyond at no significant cost More connectivity density per area,includeds Patents Pending Materials 32
33 Multi Port Vector Network Analysis Looking Beyond 12 Port Network Analysis to 65GHz The COST of ownership must come down, Only new technology can make this possible
34 Enabling Technologies Lower cost Full Bandwidth Printed uflex PMTL cabling Unmatched Phase Linearity under bending/twisting, Highly repeatable Use as internal VNA semi rigid routing Integrate on internal board signal routing Use as front end VNA test cable Use Low Cost Flat Printed PMTL End Connectors /Launcher(No precision machined needed),includeds Patents Pending Materials 34
35 Future Face of Full Bandwidth Network Analyzer(everything printed),includeds Patents Pending Materials 35
36 Enabling New Probe Technologies Increased Density, while increasing bandwidth and speed Contact Controllability and compliance designed in Re configurability Low cost disposability Field Repairable, all built in,includeds Patents Pending Materials 36
37 Handy Probes with Printed High Speed uflex,includeds Patents Pending Materials 37
38 Example of One to One Replacement for existing wafer Probes, and Any other(super Imposed for Comparison) DC 50GHz,Includeds Patents Pending Materials 38
39 Scalable, reconfigurable, printable matching any footprint, compliance,includeds Patents Pending Materials 39
40 Summary, Improving the ecosystem Testing is already expensive and complex Devices are becoming even more complex Testing must support a new high speed ecosystem Must do more, faster and cheaper over wider bandwidth at speed Must increase automation, parallelism, reduce TTM High Speed Interconnect is at the heart of it,includeds Patents Pending Materials 40
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